SCDCT1820 Rev F
DESCRIPTION
The Aeroflex Plainview CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the
interface between a MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal
parallel data bus. The unit can be employed as the mux bus interface for Remote Subsystems or Master Terminal
Bus Controllers, thus providing a common interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status
and Data words from the bus to parallel output lines, together with error information, bus status and
handshaking signals. It also contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal
Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words,
under subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation
between the unit and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional specification requirements of
MIL-STD-1553 A & B.
FEATURES
❑Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to MIL-STD-1553
specifications, including Address, Mode Code and Broadcast Decoding and Terminal Fail Safe
❑Flexibility - all control lines accessible
❑Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems
❑Dual rank l/O registers for versatile subsystem tlmlng
❑Operates from +5VDC @ 50mA
❑Self-contained +5Vdc oscillator and clock driver @ 13 mA
❑Look-ahead serial receive data output
❑Self-test, on-line wraparound, plus off-line capability
❑Full military (-55°C to +125°C) temperature range
❑Designed for commercial, industrial and aerospace applications
❑MIL-PRF-38534 compliant
❑Packaging – Metal hermetic
- 56 pin, plug-in, 1.155"W x 2.155"L x .200"Ht
- 60 lead, flat-pack, 1.015"W x 1.59"L x .147"Ht
❑DESC Standard microcircuit drawing (SMD): 5962-90636
CT1820
Data Terminal Bit Processor
www.aeroflex.com/Avionics
April 10, 2008
for MIL-STD-1553 A & B
2
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
Figure 1 – FUNCTIONAL DIAGRAM
43
36
12
SERIAL DATA OUT
32
8
9
10
13
14
16
33
31
37
7
45
46
47
48
50
44
42
41
2
3
4
5
6
54
56
56
43
43
43
53
11
34
20
21
22
19
25
26
15
27
28
24
23
38
35
30
29
18
17
1
FIRST
RANK
REC’V
REG
D0 - D7
SECOND
RANK
REC’V
REG
D0 - D7
FIRST
RANK
REC’V
REG
D8 - D15
SECOND
RANK
REC’V
REG
D8 - D15
FIRST
RANK
XMT
REG
DO - D7
SECOND
RANK
XMT
REG
DO - D7
FIRST
RANK
XMT
REG
D8 - D15
SECOND
RANK
XMT
REG
D8 - D15
MANCHESTER
DECODER
&
CONTROL LOGIC
MANCHESTER
ENCODER
&
CONTROL LOGIC
OSC
&
CLOCK
DRIVER
39
40
BROAD-
CAST
DECODE
RT ENABLE
(MSB) A4
A3
A2
A1
(LSB) A0
5 BIT
ADDRESS
{
BROADCAST
MODE CODE
VALID WORD
COMM/DATA SYNC
MODE
CODE
DECODE
DEC RST
TAKE DATA
DSC OUT
D1
(LSB) D0
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
(MSB) D15
(OPTIONAL)
SERIAL
INPUT
LATCH
DATA
2
LATCH DATA 1
LOAD
DATA 2
LOAD DATA 1
GND
GND
Vcc
+5V
CASE
DATA IN
DATA IN
BIT SELECT
DATA OUT
DATA OUT
FAIL SAFE
SEND DATA
ESCOUT
SYNC SEL
ENC ENA
OUTPUT INH
MRST
+5V OSC / CLOCK POWER
XTAL
CLOCK OUT
CLOCK IN
DATA SELECT 1
DATA
SELECT 2
BUILT IN
TEST
SELECT
ADDRESS
DECODE
FAIL SAFE
TIMER
&
CONTROL
(Plug-in Pins shown)
3
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
ABSOLUTE MAXIMUM RATINGS
Parameter Range Units
Supply Voltage +7.0 V
Logic Input Voltage -0.3 to +5.5 V
Clock Output Current (Pin 18 - Plug-in) 15 mA
Clock In (Pin 17 - Plug-in) -0.3 to VCC +0.3V V
Storage Temperature Range -65 to +150 °C
Operating Case Temperature Range -55 to +125 °C
ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TC = -55°C to +125°C)
Sym Parameter / Conditions Min Typ Max Units
VIH Logic "1" Input Voltage 2.0 - - V
VIL Logic "0" Input Voltage --0.7V
VOH Logic "1" Output Voltage See Pin assignments and Loading
VOL Logic "0" Output Voltage See Pin assignments and Loading
VIHC Logic "1" Input Voltage (CLOCK) VCC-0.5 - V
VILC Logic "0" Input Voltage (CLOCK) -GND+0.5V
VOHC Logic "1" Output Voltage (CLOCK) VCC-0.3 - V
VOLC Logic "0" Output Voltage (CLOCK) -GND+0.3V
lOC Logic Supply Current --50mA
lOSC Oscillator / Clock Supply Current 813mA
DATA
BUS
RX
DATA
IN
RX
DATA
IN
TX
DATA
OUT
TX
DATA
OUT
TX
DATA
IN
TX
DATA
IN
RX
DATA
OUT
RX
DATA
OUT
DATA
IN
DATA
IN
DATA
DATA
OUT
TX
INHIBIT
OUT
XTAL
12
MHz
CONTROL
DATA
16 BIT
OR
8 BIT
SUB-
SYSYEM
22
21
26
25
29
CT1820
BIT
PROCESSOR
1
25
2
26 10
7
33
32
31
CT3231
T/R
HYBRID
Figure 2 – TYPICAL MIL-STD-1553 DATA TERMINAL
4
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
ELECTRICAL CHARACTERISTICS – PIN ASSIGNMENTS AND LOADING
In the following table, the symbols are defined as follows:
IIH= maximum input HIGH current with VIH = 2.5 volts
IIL = maximum input LOW current with VIL = 0.4 volts
IOH = maximum output HIGH current for VOH = 2.5 volts minimum
IOL = maximum output LOW current for VOL = 0.4 volts maximum
* Indicates use of an internal pull-up resistor
Pin No Name CT1820 CT1820-2 Description
Plug
in
Flat
Pack
IIH
(μA)
IIL
(mA)
IOH
(μA)
IOL
(mA
IOL
(mA)
16VCC -- -- - +5V Power Input
27D8 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O
38D9
49D10
510D11
611D12
712DATA SELECT 1 20 -0.4 A LOW on this input applies the contents of the SECOND RANK REC’V
REG to the D8-D15 I/O pins
813A3* 20 -0.4 Part of 5 Bit ADDRESS INPUT
914A2*
10 15 A1*
11 16 GROUND Logic and power return
12 17 A4* 20 -0.4 MSB of 5 Bit ADDRESS INPUT
13 18 A0* LSB of 5 Bit ADDRESS INPUT
14 19 VALID WORD -400 4.0 4.0 A LOW on this output indicates receipt of avalid word
15 20 FAIL SAFE -400 4.0 4.0 A HIGH on this output indicates termination of a transmitted message
that exceeds 768μs.
16 21 COMM / DATA SYNC -400 4.0 4.0 A HIGH on this output indicates COMMAND (or STATUS) word
reception. A LOW indicates DATA word reception.
17 22 CLOCK IN +100 +0.1 Input for 12MHz clock (20pf load).
18 23 CLOCK OUT -1000 1.0 1.0 Output of OSCILLATOR AND CLOCK DRIVER.
19 24 S/T SELECT 20 -0.4 A HIGH on this input sets the unit in the self test mode.
20 25 CASE CASE CONNECTION
21 26 DATA IN 20 -0.4 A HIGH on this input represents a positive state on the bus.
22 27 DATA IN 20 -0.4 A HIGH on this input represents a negative state on the bus. (Pins 21
and 22 must both be high when the bus is inactive.)
23 28 ENC ENA 20 -0.4 A LOW on this input initiates a transmit cycle.
24 29 SYNC SEL 20 -0.4 Actuates COMMAND (or STATUS) sync for an input LOW and DATA
sync for an input HIGH.
25 32 DATA OUT -400 4.0 4.0 A HIGH on this output produces a positive state on the bus.
26 33 DATA OUT -400 4.0 4.0 A HIGH on this output produces a negative state on the bus.
27 34 SEND DATA -400 4.0 4.0 A HlGH on this output indicates data shifting during the transmit cycle.
28 35 ESC OUT -1000 1.2 1.2 LOW to HIGH transitions on thls output during HIGH SEND DATA cause
the transmit cycle data shifting to occur.
29 36 XTAL A 12MHz (parallel resonant) crystal is connected between this pin and
ground.
30 37 +5V (OSC/CLOCK) +5V power for OSCILLATOR AND CLOCK POWER DRIVER.
31 38 DSC OUT -1000 1.2 1.2 LOW to HIGH transitions on this output during LOW TAKE DATA cause
receive cycle data shifting to occur.
32 39 RT ENABLE -400 4.0 4.0 A HIGH on this output indicates reception of a valid COMMAND (or
STATUS) word containing the terminalís address. It also resets the FAIL
SAFE.
5
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
33 40 DEC RST 20 -0.4 A LOW on this input (for 1µs minimum) resets the decoder to a condition ready for
a new word, resets the COMM / DATA SYNC output LOW, and resets the VALID
WORD output HIGH.
34 41 GROUND Logic and Power Return.
35 42 OUTPUT INH 20 -0.4 A LOW on this input holds output pins 25 and 26 LOW.
36 43 SERIAL DATA OUT -400 4.0 4.0 The received serial data in NRZ format is available at this pin during
LOW TAKE DATA.
37 44 TAKE DATA -400 4.0 4.0 A LOW on this output indicates data shifting during the receive cycle.
38 45 MRST 20 -0.4 A LOW on this input (for 1μs minimum) interrupts and clears the
transmit cycle, resets the FAIL SAFE, and also performs the same
functions as DEC RST.
39 46 BROADCAST*-400 4.0 4.0 A HIGH on this output indicates reception of a valid COMMAND (or
STATUS) word containing all ONES in the address field.
40 47 MODE CODE*-600 6.0 6.0 A LOW on this output indicates reception of a valid COMMAND (or
STATUS) word containing all ONES or all ZEROS in the sub-address
field.
41 48 D6 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O
42 49 D7
43 50 DATA SELECT 2 20 -0.4 A LOW on this input applies the contents of the SECOND RANK REC’V
REG to the D0-D7 I/O pins.
44 51 D5 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O
45 52 D0 LSB of 16BIT TRI-STATE I/O
46 53 D1 Part of 16 Bit TRI-STATE l/O
47 54 D2 Part of 16 Bit TRI-STATE l/O
48 55 D3 Part of 16 Bit TRI-STATE l/O
49 56 LATCH DATA 2 -0.4 A HIGH on this input allows the l/O data on D0-D7 to appear at the
output of the FIRST RANK XMT REG. A LOW on this input holds the
register outputs in their last state.
50 57 D4 -0.4 -1000 6.0 10.0 Part of 16 Bit TRl-STATE l/O
51 58 LOAD DATA 2 -0.4 A LOW on this input loads the D0-D7 data into the SECOND RANK XMT
REG. A HIGH on this input then locks out the data inputs to permit serial
shifting.
52 59 LATCH DATA 1 A HIGH on this input allows the l/O data on D8-D15 to appear at the
output of the FIRST RANK XMT REG. A LOW on this input holds the
register outputs in their last state.
53 2 LOAD DATA 1 20 -0.4 A LOW on this input loads the D8-D15 data into the SECOND RANK
XMT REG. A HIGH on this input then locks out the data inputs to permit
serial shifting.
54 3 D13 -0.4 -1000 6.0 10.0 Part of 16 Bit TRl-STATE l/O.
OPTIONAL SERIAL INPUT.
55 4 D14
56 5 D15
-1NC -- -- - No Contact
-30NC -- -- -
-31NC -- -- -
-60NC -- -- -
ELECTRICAL CHARACTERISTICS – PIN ASSIGNMENTS AND LOADING con’t
In the following table, the symbols are defined as follows:
IIH= maximum input HIGH current with VIH = 2.5 volts
IIL = maximum input LOW current with VIL = 0.4 volts
IOH = maximum output HIGH current for VOH = 2.5 volts minimum
IOL = maximum output LOW current for VOL = 0.4 volts maximum
* Indicates use of an internal pull-up resistor
Pin No Name CT1820 CT1820-2 Description
Plug
in
Flat
Pack
IIH
(μA)
IIL
(mA)
IOH
(μA)
IOL
(mA
IOL
(mA)
6
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
TRANSMIT CYCLE OPERATION
ENCODER SHIFT CLOCK (ESC) (see Figure 3) operates at
the data rate (1MHz). A low at ENCODER ENABLE (ENC
ENA) during a falling edge of ESC ① starts the Transmit
cycle, which lasts for twenty ESC clock periods. The SYNC
SELECT (SYNC SEL) input is valid at the next low-to-high
transition of ESC . A high at SYNC SEL will produce a data
sync, or a low will produce a command sync for that word.
Parallel data must be stable at the second rank transmit
register before SEND DATA goes high ③. Since ENC ENA
is not synchronous with ESC, the minimum time to ③ is
3μsec from ENC ENA leading edge.
The first-rank transmit register may be operated
transparently (LATCH DATA always high), or may be used to
hold data ready for transmission, independent of the activity
on the 16-line subsystem l/O bus. As long as LATCH DATA
is held high, data present on the subsystem l/O bus appears
at the output of the first rank transmit register. Stable data
may be latched and held at the first rank register output by
bringing LATCH DATA low. Data to be transmitted may be
latched any time before the low-to high transition of SEND
DATA (SEND DATA, when appled to the LOAD DATA
inputs, locks out the data inputs to the second rank transmit
register.) For multiple word transmissions, the next word
may be inputted and latched any time after ③, but before
the next low to-high transition of SEND DATA.
SEND DATA remains high for 16 ESC periods, during which
the parallel transmit data is clocked to the MANCHESTER
ENCODER ③ to ④. After the sync and Manchester coded
data are transmitted through the DATA OUT and DATA OUT
outputs, the ENCODER adds on the parity bit for that word
⑤.
If the transmitted word is to be the last word of the
transmission, ENC ENA must go high by ⑤ to prevent
initiation of another transmit cycle.
At any time, a low applied to OUTPUT INHIBIT will force both
DATA OUT and DATA OUT to a low state without affecting
any other operations.
The entire transmit cycle may be interrupted and cleared by
applying a minimum of 1μsec negative pulse to the MASTER
RESET (MRST) input.
For 8-BlT I/O subsystems, D0 is tied to D8, D1 tied to D9,
etc., through D7 tied to D15, and data is inputted in 8-BlT
bytes by using LATCH DATA 1 and LATCH DATA 2 and/or
LOAD DATA 1 and LOAD DATA 2 independently.
For serial data applications, D15 input serves as the serial
transmit input. With LOAD DATA 1 held low and LATCH
DATA 1 held high, D15 input is applied to the ENCODERís
serial data input. Inputted data must be at the ESC rate with
the MSB starting at the low-to-high transition of SEND DATA.
If a message length ever exceeds 768μsec, the 768μsec
TIME OUT (FAIL SAFE) flag goes high, and DATA OUT and
DATA OUT are both forced to a low state. This condition will
remain until a valid command word (containing the
terminalís address) is received or until MRST goes low.
2
½ SYNC½ SYNC151413 210P½ SYNC½ SYNC151413 210P
½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P
4 5
012345 16171819012345 16 17 18 19
3
2
1
VALID
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
VALID
SEE
TEXT
SEE
TEXT
DON’T CARE
ESC
SYNC SEL
ENC ENA
LATCH DATA
DATA SELECT
SEND DATA
& LOAD DATA
DATA OUT
DATA OUT
IF USED
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
Figure 3 – TRANSMIT CYCLE TIMING
7
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
Symbol Description Min Max Units
TE1ENCODER ENABLE Set-up Time 100 - ns
TE2ENCODER ENABLE Hold Time 80 - ns
TE3SYNC SELECT Set-up Time 125 - ns
TE4SYNC SELECT Hold Time 150 - ns
TE5SEND DATA Delay Time -75ns
TE6LATCH DATA Hold Time 25 - ns
TE7LATCH DATA Set-up Time 50 - ns
TE8, TE12 1 /Parallel Data Set-up Time 40 - ns
TE9, TE13 1/Parallel Data Hold Time 60 - ns
TE10 DATA SELECT Disable Time 30 - ns
TE11 DATA SELECT Hold Time 0-ns
NOTE: 1/ TE12 and TE13 apply when LATCH DATA is not used.
Figure 4 – ENCODER TIMING DETAIL
8
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
RECEIVE CYCLE OPERATION
DECODER SHIFT CLOCK (DSC) (see Figure 5) operates at
the data rate (1MHz). When the DECODER recognises a
valid sync and two valid Manchester data bits ①, a receive
cycle is initiated. The new sync is indicated at the
COMMAND/DATA SYNC (C/D SYNC) output and the TAKE
DATA output goes low . The C/D sync output will remain
in its valid state until a new sync is detected on a
subsequent word or until DECODER RESET (DEC RST) or
MRST goes low. A low at DEC RST or MRST causes C/D
SYNC to go low.
TAKE DATA remains low for 16 DSC periods during which
time the 16 serial data bits appear at the SERIAL DATA
OUTPUT (SDO). This data is simultaneously loaded into the
first-rank receive register. The low-to-high transition of
TAKE DATA ③ makes the new data available at the output
of the second-rank receive register. This data remains
available until the next low-to-high transitions of TAKE
DATA. It is not reset or cleared by any other signals. This
data is applied to the D0 to D15 I/O bus by setting DATA
SELECT lines low.
After all data has been loaded into the receive registers, the
data is checked for odd parity. A low on VALID WORD (VW)
output ③, indicates successful reception of a word without
any Manchester or parity errors. For consecutive word
receptions, VW will go high again in 3 to 3.5μs. In the
absence of succeeding valid syncs, VW will return high in
20μs. A DEC RST (low) at any time will reset VW high.
All decoded commands, including RT ENABLE (address
recognition), BROADCAST and MODE CODE are enabled
internally by VW and remain valid only as long as VW is low.
For 8-BIT l/O subsystems (D0 tied to D8, through D7 tied to
D15), data may be extracted in 8 BIT bytes by selectively
activating DATA SELECT 1 and DATA SELECT 2.
For serial data systems, SERIAL DATA OUTPUT is available
at the DSC rate from to ③.
.
2
2
012345 16171819012345 16171819
½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P
½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 210P
FROM PREVIOUS WORD
15 43210 15 4321 0
4
3
2
1
FROM PREVIOUS WORD
UNDEFINED
VALID FOR CURRENT WORD VALID FOR CURRENT WORD
UNDEFINED
NOT VALID
FROM PREVIOUS WORD
OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15 OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15
NEW DATA
VALID NOT VALID VALID
NEW DATA
OSC
DATA IN
DATA IN
TAKE DATA
C/D SYNC
SDO
VW
DECODE COMMANDS
SECOND-RANK REC’V
DATA SELECT
(see text)
REGISTER CONTENT
Figure 5 – RECEIVE CYCLE TIMING
9
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
Symbol Description Min Max Units
TD1TAKE DATA Delay On Time -125ns
TD2TAKE DATA Delay Off Time -125ns
TD3Sync Delay Time -60ns
TD4VALID WORD Delay Time -125ns
TD5BROADCAST Delay Time -70ns
TD6RT ENABLE Delay Time -100ns
TD7MODE CODE Delay Time -100ns
TD8DATA SELECT Input Delay Time 1/0-ns
TD9Parallel Data Output Delay Time -60ns
NOTE: 1/ DATA SELECT may be applied at any tlme that the 16 line I/O is otherwise free. The parallel Data Out,
however, is not ’New Data’ until after TAKE DATA goes high.
Figure 6 – DECODER TIMING DETAIL
10
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
SELF TEST FUNCTION
A high on the S/T SELECT input sets the hybrid in the SELF
TEST mode. In this mode, the DATA and DATA output lines
are connected to the Decoder inputs so that the unit may
operate in the "wraparound" mode without actually going
through the data bus transceiver. Note that the DATA and
DATA output lines are active in this mode and the S/T
SELECT command must also be used to inhibit the data bus
transmitter to prevent arbitrary transmission on the data
bus.
TERMINAL FAIL SAFE
In order to satisfy the Terminal Fail Safe requirements of
MIL-STD-1553B, the DATA and DATA output lines are
continuously monitored for length of message. A
transmitted message in excess of 768μs sets the FAIL SAFE
output high and terminates the transmission by setting both
DATA and DATA output lines low. As a redundant safety
factor, the FAlLSAFE output may be applied to the lNHlBlT
input of the data bus transmitter (if so equipped). Further
transmissions are prevented until the FAIL SAFE flag is reset
either by reception of a valid command word containing the
terminal address or by a negative pulse on the MRST input.
Note: Transmissions containing gaps of 3μs or less are
considered continuous, even if the gap is caused by a MRST
pulse.
TERMINAL ADDRESS LINES
The five-bit terminal address is set by hard wiring the 5-BlT
ADDRESS lines. The hybrid contains internal pull-up
resistors so that logic "1" lines may be left open circuited.
Logic "0" lines must be grounded.
In operation, RT ENABLE goes high when a valid command
word containing the hard-wired address is received. See
"RECEIVE CYCLE OPERATION" for timing.
OSCILLATOR AND CLOCK DRIVER
The hybrid may be operated with either the internal clock
or an external clock source.
For internal clock operation, a 12MHz parallel-resonant
fundamental-mode crystal must be connected from XTAL
to ground. Power (+5V) must be applied to +5V
OSC/CLOCK POWER and CLOCK OUT must be connected
to CLOCK IN.
For external clock operation, no power is applied to +5V
OSC/CLOCK POWER and the external clock is applied to
CLOCK IN (CLOCK OUT not connected). The external clock
must be capable of driving a 20 picofarad load to within 0.5
volts of VCC and within 0.5 volts of ground with rise and fall
times of less than 10 nanoseconds. Standard TTL levels are
not satisfactory. For a normal 1MHz data rate, the clock
frequency must be 12MHz.
FALSE RT ENABLE
Terminals that continuously monitor their own
transmissions are subject to "END-AROUND" operation
due to a false RT ENABLE. The terminal can erroneously
interpret its own status word as a new command word. If no
measures are taken to prevent or re-set RT ENABLE, it will
remain high for 20μs or until the DECODER recognises a
new valid sync (whichever time is shorter).
RT ENABLE may be inhibited by interrupting the RECEIVE
CYCLE during a status word transmission. Inverted SEND
DATA applied to DEC RST will prevent reception of the
status word.
If continuous monitoring is required, RT ENABLE may be
reset immediately after it goes high by a 1μs (minimum) low
at DEC RST. The status word will then be available at the
second-rank receive register.
11
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
PIN OUT DESCRIPTION (FLAT PACK)
Pin
#Function Pin
#Function
1NC 31NC
2LOAD DATA 1 32 DATA OUT
3D13 33DATA OUT
4D14 34SEND DATA
5D15 35ESC OUT
6VCC 36 XTAL
7 D8 37 +5V (OSC/CLOCK)
8D9 38DSC OUT
9D10 39RT ENABLE
10 D11 40 DEC RST
11 D 12 41 G R O U N D
12 DATA SELEC T 1 42 OUTPUT INH
13 A3 43 SERIAL DATA OUT
14 A2 44 TAKE DATA
15 A1 45 MRST
16 GROUND 46 BROADCAST
17 A4 47 MODE CODE
18 A0 48 D6
19 VALID WORD 49 D7
20 FAIL SAFE 50 DATA SELECT 2
21 COMM/DATA SYNC 51 D5
22 CLOCK IN 52 D0
23 CLOCK OUT 53 D1
24 S/T SELECT 54 D2
25 CASE 55 D3
26 DATA IN 56 LATCH DATA 2
27 DATA IN 57 D4
28 ENC ENA 58 LOAD DATA 2
29 SYNC SEL 59 LATCH DATA 1
30 NC 60 NC
PIN OUT DESCRIPTION (PLUG-IN)
Pin
#Function Pin
#Function
1 VCC 29 XTAL
2 D8 30 +5V (OSC/CLOCK)
3D9 31DSC OUT
4 D10 32 RT ENABLE
5D11 33DEC RST
6D12 34GROUND
7DATA SELECT 1 35 OUTPUT INH
8A3 36 SERIAL DATA OUT
9A2 37TAKE DATA
10 A1 38 MRST
11 G R O U N D 3 9 B R O A D C A S T
12 A4 40 MODE CODE
13 A0 41 D6
14 VA LID W ORD 42 D7
15 FAI L SAFE 43 DATA SELECT 2
16 COMM/DATA SYNC 44 D5
17 CLOCK IN 45 D0
18 CLOCK OUT 46 D1
19 S/T SELECT 47 D2
20 CASE 48 D3
21 DATA IN 49 LATCH DATA 2
22 DATA IN 50 D4
23 ENC ENA 51 LOA D DATA 2
24 SYNC SEL 52 LATCH DATA 1
25 DATA OUT 53 LOAD DATA 1
26 DATA OUT 54 D13
27 SEND DATA 55 D14
28 ESC OUT 56 D15
12
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
Plug-In Package Outline
mm sehcnI
50. 200.
64. 810.
45.2 001.
80.5 002.
34.11 054.
68.22 009.
43.92 551.1
62.84 009.1
47.45
551.2
:SETON
.sehcni ni era snoisnemiD .1
.ylno noitamrofni lareneg rof nevig era stnelaviuqe cirteM
.2
ceps esiwrehto sselnU .3 ified, tolerances are ± .005 (0.13 mm) for three place decimals.
Top View
13
SCDCT1820 Rev F 4/10/08 Aeroflex Plainview
Flat Package Outline
mm sehcnI
50. 200.
31. 500.
83. 510.
98.8 053.
87.52 510.1
38.63 054.1
93.04 095.1
:SETON
.sehcni ni
era snoisnemiD .1
.ylno noitamrofni lareneg rof nevig era stnelaviuqe cirteM .2
Top View
.065
.065
±.005
.147
.147
1.65
3.73
.010 .254
MAX
14
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Aeroflex Microelectronic Solutions reserves the right to
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parameters must be validated for each customer's application
by engineering. No liability is assumed as a result of use of
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SCDCT1820 Rev F 4/10/08
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This product is controlled for export under the International Traffic in
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ORDERING INFORMATION
Aeroflex Part # DSCC SMD # Screening Package
CT1820 -Military Temperature, -55°C to +125°C
Screened in accordance with
MIL-PRF-38534, Class H
Plug-in
CT1820-FP -Flat Pack
CT1820-2 -Plug-in
CT1820-2-FP -Flat Pack
CT1820-001-1
CT1820-001-2
5962-9063601HXC
5962-9063601HXA Per DSCC SMD 5962-90636 Plug-in
CT1820-2-001-1
CT1820-2-001-2
5962-9063602HXC
5962-9063602HXA
CT1820-201-1 5962-9063601HYC Flat Pack
CT1820-2-201-1 5962-9063602HYC
