TMS320F28377SZWTS - TEXAS INSTRUMENTS

September 2015 I

ProASIC3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)†

• FlashLock® Designed to Secure FPGA Contents

Low Power

• Low Power ProASIC®3 nano Products

• 1.5 V Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†

• True Dual-Port SRAM (except ×18 organization)†

Enhanced Commercial Temperature Range

•T

j = –20°C to +85°C

† A3PN030 and smaller devices do not support this feature.

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices A3PN010 A3PN0151A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices1A3PN030Z1,2 A3PN060Z1A3PN125Z1A3N250Z1

System Gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000

Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048

VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144

RAM Kbits (1,024 bits)2– – – – 18 36 36

4,608-Bit Blocks2––– – 4 8 8

FlashROM Kbits 1 1 1 1 1 1 1

Secure (AES) ISP2––– – YesYesYes

Integrated PLL in CCCs2––– – 1 1 1

VersaNet Globals 4 4 4 6 18 18 18

I/O Banks 2 3 3 2 2 2 4

Maximum User I/Os (packaged device) 34 49 49 77 71 71 68

Maximum User I/Os (Known Good Die) 34 – 52 83 71 71 68

Package Pins

QFN

VQFP

QN48 QN68 QN68 QN48, QN68

VQ100 VQ100 VQ100 VQ100

Notes:

1. Not recommended for new designs. Few devices/packages are obsoleted. For more information on obsoleted devices/packages, refer

to the PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.

2. A3PN030Z and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the DS0097: ProASIC3 Family Flash FPGAs Datasheet and DS0098:

ProASIC3E Flash Family FPGAs Datasheet.

Revision 12

DS0111

II Revision 12

I/Os Per Package

ProASIC3 nano Device Status

ProASIC3 nano Devices A3PN010 A3PN0151A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices1A3PN030Z1A3PN060Z1A3PN125Z1A3PN250Z1

Known Good Die 34 – 52 83 71 71 68

QN48 34 – – 34 – – –

QN68 – 49 49 49 – – –

VQ100 – – –77717168

Notes:

1. Not recommended for new designs.

2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide

to ensure compliance with design and board migration requirements.

3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G"

in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other

packages are RoHS-compliant only.

Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions

Packages QN48 QN68 VQ100

Length × Width (mm\mm) 6 x 6 8 x 8 14 x 14

Nominal Area (mm2) 36 64 196

Pitch (mm) 0.4 0.4 0.5

Height (mm) 0.90 0.90 1.20

ProASIC3 nano Devices Status ProASIC3 nano-Z Devices Status

A3PN010 Production

A3PN015 Not recommended for new designs.

A3PN020 Production

A3PN030Z Not recommended for new designs.

A3PN060 Production A3PN060Z Not recommended for new designs.

A3PN125 Production A3PN125Z Not recommended for new designs.

A3PN250 Production A3PN250Z Not recommended for new designs.

ProASIC3 nano Flash FPGAs

Revision 12 III

ProASIC3 nano Ordering Information

Devices Not Recommended For New Designs

A3PN015, A3PN030Z, A3PN060Z, A3PN125Z, and A3PN250Z are not recommended for new designs. For more information on

obsoleted devices/packages, refer to the PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.

Device Marking

Microsemi® normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some

of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited.

Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a

subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by

character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications

markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.

Figure 1 on page 1-IV shows an example of device marking based on the AGL030V5-UCG81.

Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt

trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input.

For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the

device.

A3PN010 = 10,000 System Gates

A3PN015 = 15,000 System Gates (A3PN015 is not recommended for new designs)

A3PN020 = 20,000 System Gates

A3PN030 = 30,000 System Gates

A3PN060 = 60,000 System Gates

A3PN125 = 125,000 System Gates

A3PN250 = 250,000 System Gates

Speed Grade

Blank = Standard

Feature Grade

Z = nano devices without enhanced features* (Not recommended for new designs)

3PN250 Z1VQ

Part Number

ProASIC3 nano Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

DIELOT =Known Good Die

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

100 YI

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (–20°C to +85°C Junction Temperature)

I = Industrial (–40°C to +100°C Junction Temperature)

Blank = Standard Packaging

G= RoHS-Compliant Packaging

PP= Pre-Production

ES= Engineering Sample (Room Temperature Only)

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Note: Only devices with packages greater than or equal to 5x5 are supported.

IV Revision 12

The actual mark will vary by the device/package combination ordered.

ProASIC3 nano Products Available in the Z Feature Grade

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Contact your local Microsemi SoC Products Group representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Figure 1 • Example of Device Marking for Small Form Factor Packages

Devices A3PN030* A3PN060* A3PN125* A3PN250*

Packages QN48 – – –

QN68 – – –

VQ100 VQ100 VQ100 VQ100

Note: *Not recommended for new designs.

ProASIC3 nano Devices A3PN010 A3PN015* A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices* A3PN030Z* A3PN060Z* A3PN125Z* A3PN250Z*

QN48 C, I – – C, I – – –

QN68 – C, I C, I C, I – – –

VQ100 – – – C, I C, I C, I C, I

Note: *Not recommended for new designs.

C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature.

I = Industrial temperature range: –40°C to +100°C junction temperature.

Temperature Grade Std.

C1

I2

Notes:

1. C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature.

2. I = Industrial temperature range: –40°C to +100°C junction temperature.

ACTELXXX

AGL030YWW

UCG81XXXX

XXXXXXXX

Country of Origin

Date Code

Customer Mark

(if applicable)

Device Name

(six characters)

Package

Wafer Lot #

ProASIC3 nano Flash FPGAs

Revision 12 V

Table of Contents

ProASIC3 nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3 nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Revision 12 1-1

1 – ProASIC3 nano Device Overview

General Description

ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano

devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3

nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These

features enable designers to create high-density systems using existing ASIC or FPGA design flows and

tools.

ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller

devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates,

supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and

packages for greater customer value in high volume consumer, portable, and battery-backed markets.

Added features include smaller footprint packages designed with two-layer PCBs in mind, low power,

hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external

boot PROM is required. On-board security mechanisms prevent access to all the programming

information and enable secure remote updates of the FPGA logic. Designers can perform secure remote

in-system reprogramming to support future design iterations and field upgrades with confidence that

valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using

the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for

ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC

replacement solution, especially for applications in the consumer, networking/communications,

computing, and avionics markets.

With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of

programmable logic and quick time to market.

Security

Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which

provides a unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest

level of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the

industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was

adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977

DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES

key that make them the most comprehensive programmable logic device security solution available

today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field

updates over public networks such as the Internet, and are designed to ensure that valuable IP remains

out of the hands of system overbuilders, system cloners, and IP thieves.

ProASIC3 nano Device Overview

1-2 Revision 12

Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security,

are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is

protected with industry-standard security, making remote ISP possible. A ProASIC3 nano device

provides the best available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano

FPGAs do not require system configuration components such as EEPROMs or micro-controllers to load

device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and

system reliability.

Instant On

Microsemi flash-based ProASIC3 nano devices support Level 0 of the Instant On classification standard.

This feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.

The Instant On feature of flash-based ProASIC3 nano devices greatly simplifies total system design and

reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used

for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the

ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to

be reloaded when system power is restored. This enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from

the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and

design risk while increasing system reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors

occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection

and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an

ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.

Advanced Flash Technology

ProASIC3 nano devices offer many benefits, including non-volatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

ProASIC3 nano Flash FPGAs

Revision 12 1-3

Advanced Architecture

The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs.

The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3

to Figure 1-4 on page 1-4):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Advanced I/O structure

Note: *Bank 0 for the A3PN030 device

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM

(A3PN010 and A3PN030)

Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and

A3PN020)

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1*

Bank 1

Bank 0

Bank 1

CCC-GL

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1

Bank 2

Bank 0

Bank 1

CCC-GL

ProASIC3 nano Device Overview

1-4 Revision 12

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT)

equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are

connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the

device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is

possible for virtually any design.

Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125)

Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ProASIC3 nano Flash FPGAs

Revision 12 1-5

VersaTiles

The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3 nano VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-5 for VersaTile configurations.

User Nonvolatile FlashROM

ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface.

The core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in

security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3 nano development software solutions, Libero® System-on-Chip (SoC) software and

Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential

programming files for applications requiring a unique serial number in each part. Another feature enables

the inclusion of static data for system version control. Data for the FlashROM can be generated quickly

and easily using Libero SoC and Designer software tools. Comprehensive programming file support is

also included to allow for easy programming of large numbers of parts with differing FlashROM contents.

Figure 1-5 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3 nano Device Overview

1-6 Revision 12

SRAM and FIFO

ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along

their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available

memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port. For

example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM

blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro

(except in A3PN030 and smaller devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures

provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and

A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices

use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any

PLLs or programmable delays.

For devices using the six CCC block architecture, these six CCC blocks are located at the four corners

and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the

FPGA core or from dedicated connections to the CCC block, which are located near the CCC.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC) (for PLL only)

Global Clocking

ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high fanout nets.

ProASIC3 nano Flash FPGAs

Revision 12 1-7

I/Os with Advanced I/O Standards

ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V).

The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of various single-data-rate applications for all versions of nano devices and double-data-

rate applications for the A3PN060, A3PN125, and A3PN250 devices.

ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support

cold-sparing and Schmitt trigger.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

ProASIC3 nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the

JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to

3.6 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-6 on page 1-8).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

ProASIC3 nano Device Overview

1-8 Revision 12

Z -Tri-State: I/O is tristated

6. Click OK to return to the FlashPoint – Programming File Generator window.

I/O States During programming are saved to the ADB and resulting programming files after completing

programming file generation.

Figure 1-6 • I/O States During Programming Window

Revision 12 2-1

2 – ProASIC3 nano DC and Switching Characteristics

General Specifications

The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing,

and hot-swap I/O capability. Refer to the "ProASIC3 nano Ordering Information" section on page III for

more information.

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Tabl e 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V V

TSTG 1Storage temperature –65 to +150 °C

TJ1Junction temperature +125 °C

Notes:

1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

3. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

ProASIC3 nano DC and Switching Characteristics

2-2 Revision 12

Table 2-2 • Recommended Operating Conditions 1, 2

Symbol Parameter

Extended

Commercial Industrial Units

TJJunction temperature –20 to +852–40 to +1002°C

VCC 31.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP 4Programming voltage Programming Mode43.15 to 3.45 3.15 to 3.45 V

Operation 50 to 3.6 0 to 3.6 V

VCCPLL 6Analog power supply (PLL) 1.5 V DC core supply voltage 31.425 to 1.575 1.425 to 1.575 V

VCCI and

VMV 71.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.3 V Wide Range supply voltage 82.7 to 3.6 2.7 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to

+85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures,

Microsemi recommends using custom settings for temperature range before running timing and power analysis tools.

For more information regarding custom settings, refer to the New Project Dialog Box in the Libero Online Help.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.

4. The programming temperature range supported is Tambient = 0°C to 85°C.

5. VPUMP can be left floating during operation (not programming mode).

6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.

7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for

further information.

8. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product

Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3 nano Flash FPGAs

Revision 12 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric

User’s Guide for information on clock and lock recovery.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle 2

Maximum Overshoot/

Undershoot 2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

ProASIC3 nano DC and Switching Characteristics

2-4 Revision 12

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional but slower because

VCCI / VCC are below specification.

For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min

VCCI

datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

eactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

but slower because VCCI

is below specification. For the

same reason, input buffers do

not meet VIH / VIL levels, and output

buffers do not meet VOH/VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3 nano Flash FPGAs

Revision 12 2-5

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

TJ = Junction Temperature = T + TA

EQ 1

where:

TA = Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = ja * P

ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is

ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

EQ 2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. (C)–

ja(C/W)

------------------------------------------------------------------------------------------------------------------------------------------ 100C70C–

20.5C/W

------------------------------------- 1.463 W

===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count jc

ja

UnitsStill Air 200 ft./min. 500 ft./min.

Quad Flat No Lead (QFN) All devices 48 TBD TBD TBD TBD C/W

68 TBD TBD TBD TBD C/W

100 TBD TBD TBD TBD C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 100°C

1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013

1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930

1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875

ProASIC3 nano DC and Switching Characteristics

2-6 Revision 12

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-7 • Quiescent Supply Current Characteristics

A3PN010 A3PN015 A3PN020 A3PN060 A3PN125 A3PN250

Typical (25°C) 600 µA 1 mA 1 mA 2 mA 2 mA 3 mA

Max. (Commercial) 5 mA 5 mA 5 mA 10 mA 10 mA 20 mA

Max. (Industrial) 8 mA 8 mA 8 mA 15 mA 15 mA 30 mA

Note: IDD includes VCC, VPUMP, and VCCI, currents.

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

VCCI (V) Dynamic Power, PAC9 (µW/MHz)1

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.45

3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.93

3.3 V LVCMOS wide range23.3 16.45

3.3 V LVCMOS wide range – Schmitt Trigger 3.3 18.93

2.5 V LVCMOS 2.5 4.73

2.5 V LVCMOS – Schmitt Trigger 2.5 6.14

1.8 V LVCMOS 1.8 1.68

1.8 V LVCMOS – Schmitt Trigger 1.8 1.80

1.5 V LVCMOS (JESD8-11) 1.5 0.99

1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.96

Notes:

1. PAC9 is the total dynamic power measured on VCCI.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

ProASIC3 nano Flash FPGAs

Revision 12 2-7

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD (pF) 2VCCI (V) Dynamic Power, PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 162.01

3.3 V LVCMOS wide range410 3.3 162.01

2.5 V LVCMOS 10 2.5 91.96

1.8 V LVCMOS 10 1.8 46.95

1.5 V LVCMOS (JESD8-11) 10 1.5 32.22

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. Values for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 correspond to a

default loading of 35 pF.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

ProASIC3 nano DC and Switching Characteristics

2-8 Revision 12

Power Consumption of Various Internal Resources

Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Dynamic Contributions

(µW/MHz)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PAC1 Clock contribution of a Global Rib 11.03 11.03 9.3 9.3 9.3 9.3

PAC2 Clock contribution of a Global Spine 1.58 0.81 0.81 0.4 0.4 0.4

PAC3 Clock contribution of a VersaTile row 0.81

PAC4 Clock contribution of a VersaTile used as a

sequential module

0.12

PAC5 First contribution of a VersaTile used as a

sequential module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a

combinatorial Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 2-8 on page 2-6.

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Table 2-9 on page 2-7.

PAC11 Average contribution of a RAM block during a read

operation

25.00 N/A

PAC12 Average contribution of a RAM block during a write

operation

30.00 N/A

PAC13 Dynamic contribution for PLL 2.60 N/A

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power

spreadsheet calculator or SmartPower tool in Libero SoC.

Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Static Power (mW)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PDC1 Array static power in Active mode See Table 2-7 on page 2-6.

PDC4 Static PLL contribution 12.55 N/A

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.

Notes:

1. Minimum contribution of the PLL when running at lowest frequency.

2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet

calculator or SmartPower tool in Libero SoC.

ProASIC3 nano Flash FPGAs

Revision 12 2-9

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock generated

• The number of combinatorial and sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on

page 2-11.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-13 on

page 2-11.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-13 on page 2-11. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's

Guide.

NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's

Guide.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

ProASIC3 nano DC and Switching Characteristics

2-10 Revision 12

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.

1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-11.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on page 2-11.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.

ProASIC3 nano Flash FPGAs

Revision 12 2-11

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

1Toggle rate of VersaTile outputs 10%

2I/O buffer toggle rate 10%

Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

1I/O output buffer enable rate 100%

2RAM enable rate for read operations 12.5%

3RAM enable rate for write operations 12.5%

ProASIC3 nano DC and Switching Characteristics

2-12 Revision 12

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case

VCC = 1.425 V, with Default Loading at 10 pF

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVCMOS 2.5V Output Drive

Strength = 8 mA High Slew Rate

Input LVCMOS 2.5 V

LVCMOS 1.5 V

LVTTL 3.3 V Output drive

strength = 8 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTLOutput drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 2 mA

High slew rate

LVTTLOutput drive strength = 4 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 0.56 ns t

= 0.49 ns

= 2.25 ns

= 0.87 ns t

= 2.87 ns

= 0.51 ns

= 2.21 ns

= 0.47 ns t

= 3.02 ns

= 0.47 ns

= 0.84 ns

CLKQ

= 0.55 ns t

OCLKQ

= 0.59 ns

SUD

= 0.43 ns t

OSUD

= 0.31 ns

= 2.21 ns

= 0.84 ns

= 1.14 ns

CLKQ

= 0.55 ns

SUD

= 0.43 ns

= 0.84 ns

ICLKQ

= 0.24 ns

ISUD

= 0.26 ns

= 1.04 ns

ProASIC3 nano Flash FPGAs

Revision 12 2-13

Figure 2-3 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDIN

(R)

DIN

GND tDIN

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3 nano DC and Switching Characteristics

2-14 Revision 12

Figure 2-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3 nano Flash FPGAs

Revision 12 2-15

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

Vtrip

50%

90% VCCI

Vtrip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%t

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

Vtrip

50%

ZHS

Vtrip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

VCC

VCCI

VCC

VOH

VOL

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3 nano DC and Switching Characteristics

2-16 Revision 12

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

I/O Standard

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option2

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min.

Max

Min.

Max.

V Max. V

Min.

VmAmA

3.3 V LVTTL/

3.3 V

LVCMOS

8 mA 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

3.3 V

LVCMOS

Wide Range

100 µA 8 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100

µA

100

µA

2.5 V

LVCMOS

8 mA 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V

LVCMOS

4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V

LVCMOS

2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

Table 2-15 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial 1Industrial 2

IIL 3IIH 4IIL 3IIH 4

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

Notes:

1. Commercial range (–20°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

ProASIC3 nano Flash FPGAs

Revision 12 2-17

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-16 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

3.3 V LVCMOS Wide Range 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

Table 2-17 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3 nano DC and Switching Characteristics

2-18 Revision 12

Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF)

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

For A3PN060, A3PN125, and A3PN250

I/O Standard

Drive Strength (mA)

Equivalent Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

3.3 V LVTTL /

3.3 V LVCMOS

8 8 mA High 35 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14

3.3 V LVCMOS

Wide Range

100 µA 8 mA High 35 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35

2.5 V LVCMOS 8 8 mA High 35 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98

1.8 V LVCMOS 4 4 mA High 35 0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89

1.5 V LVCMOS 2 2 mA High 35 0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF)

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

For A3PN020, A3PN015, and A3PN010

I/O Standard

Drive Strength (mA)

Equivalent Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

3.3 V LVTTL /

3.3 V LVCMOS

8 8 mA High 10 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14

3.3 V LVCMOS

Wide Range

100µA8mA High 10 0.603.940.041.572.180.433.943.163.724.35

2.5 V LVCMOS 8 8 mA High 10 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98

1.8 V LVCMOS 4 4 mA High 10 0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89

1.5 V LVCMOS 2 2 mA High 10 0.60 3.76 0.04 1.56 2.14 0.43 3.74 3.76 2.66 2.83

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-19

Detailed I/O DC Characteristics

Table 2-20 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-21 • I/O Output Buffer Maximum Resistances 1

Standard Drive Strength

RPULL-DOWN

()2

RPULL-UP

()3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

3.3 V LVCMOS Wide Range 100 µA Same as equivalent

software default drive

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models, located at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

()

R(WEAK PULL-DOWN)2

()

Min. Max. Min. Max.

3.3 V 10 K 45 K 10 K 45 K

3.3 V (wide range I/Os) 10 K 45 K 10 K 45 K

2.5 V 11 K 55 K 12 K 74 K

1.8 V 18 K 70 K 17 K 110 K

1.5 V 19 K 90 K 19 K 140 K

Notes:

1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN)

ProASIC3 nano DC and Switching Characteristics

2-20 Revision 12

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-23 • I/O Short Currents IOSH/IOSL

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

3.3 V LVCMOS Wide Range 100 µA Same as equivalent software

default drive

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

1.5 V LVCMOS 2 mA 13 16

Note: *TJ = 100°C

Table 2-24 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

–20°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

ProASIC3 nano Flash FPGAs

Revision 12 2-21

Table 2-25 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS

(Schmitt trigger

disabled)

No requirement 10 ns * 20 years (100°C)

LVTTL/LVCMOS

(Schmitt trigger

enabled)

No requirement No requirement, but input

noise voltage cannot exceed

Schmitt hysteresis

20 years (100°C)

Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Microsemi recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

ProASIC3 nano DC and Switching Characteristics

2-22 Revision 12

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-27 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA3

Max.

mA3µA4µA4

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-6 • AC Loading

Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.410

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

35 pF for tZH / tZHS / tZL / tZLS

35 pF for tHZ / tLZ

ProASIC3 nano Flash FPGAs

Revision 12 2-23

Timing Characteristics

Table 2-29 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 9.70 0.04 1.13 1.52 0.43 9.88 8.82 2.31 2.50 ns

–1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns

–2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns

4 mA Std. 0.60 9.70 0.04 1.13 1.52 0.43 9.88 8.82 2.31 2.50 ns

–1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns

–2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns

6 mA Std. 0.60 6.90 0.04 1.13 1.52 0.43 7.01 6.22 2.61 3.01 ns

–1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns

–2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns

8 mA Std. 0.60 6.90 0.04 1.13 1.52 0.43 7.01 6.22 2.61 3.01 ns

–1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns

–2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 7.19 0.04 1.13 1.52 0.43 7.32 6.40 2.30 2.62 ns

–1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns

–2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns

4 mA Std. 0.60 7.19 0.04 1.13 1.52 0.43 7.32 6.40 2.30 2.62 ns

–1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns

–2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns

6 mA Std. 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 ns

–1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns

–2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns

8 mA Std. 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 ns

–1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns

–2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-24 Revision 12

Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 5.48 0.04 1.13 1.52 0.43 5.58 5.21 2.31 2.50 ns

–1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns

–2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns

4 mA Std. 0.60 5.48 0.04 1.13 1.52 0.43 5.58 5.21 2.31 2.50 ns

–1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns

–2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns

6 mA Std. 0.60 4.33 0.04 1.13 1.52 0.43 4.40 4.14 2.61 3.01 ns

–1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns

–2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns

8 mA Std. 0.60 4.33 0.04 1.13 1.52 0.43 4.40 4.14 2.61 3.01 ns

–1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns

–2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 3.56 0.04 1.13 1.52 0.43 3.62 3.03 2.30 2.62 ns

–1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns

–2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns

4 mA Std. 0.60 3.56 0.04 1.13 1.52 0.43 3.62 3.03 2.30 2.62 ns

–1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns

–2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns

6 mA Std. 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 ns

–1 0.51 2.32 0.04 0.96 1.29 0.36 2.36 1.90 2.22 2.67 ns

–2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns

8 mA Std. 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 ns

–1 0.51 2.32 0.04 0.96 129 0.36 2.36 1.90 2.22 2.67 ns

–2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-25

3.3 V LVCMOS Wide Range

Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range

3.3 V LVCMOS

Wide Range

Equivalent

Software

Default

Drive

Strength

Option3

VIL VIH VOL VOH IOL IOH IIL1IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmAµA

4µA4

100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

100 µA 8mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

ProASIC3 nano DC and Switching Characteristics

2-26 Revision 12

Timing Characteristics

Table 2-34 • 3.3 V LVCMOS Wide Range Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38 ns

–1 0.51 12.53 0.04 1.33 1.85 0.36 12.53 11.19 2.77 2.87 ns

–2 0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52 ns

100 µA 4 mA Std. 0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38 ns

–1 0.51 12.53 0.04 1.33 1.85 0.36 12.53 11.19 2.77 2.87 ns

–2 0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52 ns

100 µA 6 mA Std. 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns

–1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns

–2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns

100 µA 8 mA Std. 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns

–1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns

–2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-27

Table 2-35 • 3.3 V LVCMOS Wide Range High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns

–1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns

–2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns

100 µA 4 mA Std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns

–1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns

–2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns

100 µA 6 mA Std. 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 ns

–1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns

–2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns

100 µA 8 mA Std. 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 ns

–1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns

–2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

3. Software default selection highlighted in gray.

ProASIC3 nano DC and Switching Characteristics

2-28 Revision 12

Table 2-36 • 3.3 V LVCMOS Wide Range Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 0.60 8.20 0.04 1.57 2.18 0.43 8.20 7.68 3.26 3.38 ns

–1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns

–2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns

100 µA 4 mA Std. 0.60 8.20 0.04 1.57 2.18 0.43 8.20 7.68 3.26 3.38 ns

–1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns

–2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns

100 µA 6 mA Std. 0.60 6.42 0.04 1.57 2.18 0.43 6.42 6.05 3.72 4.16 ns

–1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns

–2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns

100 µA 8 mA Std. 0.60 6.42 0.04 1.57 2.18 0.43 6.42 6.05 3.72 4.16 ns

–1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns

–2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-29

Table 2-37 • 3.3 V LVCMOS Wide Range High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Equivalent

Software

Default

Drive

Strength

Option1

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

100 µA 2 mA Std. 0.60 5.23 0.04 1.57 2.18 0.43 5.23 4.37 3.25 3.56 ns

–1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns

–2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns

100 µA 4 mA Std. 0.60 5.23 0.04 1.57 2.18 0.43 5.23 4.37 3.25 3.56 ns

–1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns

–2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns

100 µA 6 mA Std. 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 ns

–1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns

–2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns

100 µA 8 mA Std. 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 ns

–1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns

–2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

3. Software default selection highlighted in gray.

ProASIC3 nano DC and Switching Characteristics

2-30 Revision 12

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-38 • Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA3

Max.

mA3µA4µA4

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-39 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.210

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

35 pF for tZH / tZHS / tZL / tZLS

35 pF for tHZ / tLZ

ProASIC3 nano Flash FPGAs

Revision 12 2-31

Timing Characteristics

Table 2-40 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 11.29 0.04 1.43 1.63 0.43 10.64 11.29 2.27 2.29 ns

–1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns

–2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns

4 mA Std. 0.60 11.29 0.04 1.43 1.63 0.43 10.64 11.29 2.27 2.29 ns

–1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns

–2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns

6 mA Std. 0.60 7.73 0.04 1.43 1.63 0.43 7.70 7.73 2.60 2.89 ns

–1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns

–2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns

8 mA Std. 0.60 7.73 0.04 1.43 1.63 0.43 7.70 7.73 2.60 2.89 ns

–1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns

–2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-41 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.38 0.04 1.43 1.63 0.43 7.36 8.38 2.27 2.37 ns

–1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns

–2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns

4 mA Std. 0.60 8.38 0.04 1.43 1.63 0.43 7.36 8.38 2.27 2.37 ns

–1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns

–2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns

6 mA Std. 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 ns

–1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns

–2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns

8 mA Std. 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 ns

–1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns

–2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-32 Revision 12

Table 2-42 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 6.40 0.04 1.43 1.63 0.43 6.16 6.40 2.27 2.29 ns

–1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns

–2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns

4 mA Std. 0.60 6.40 0.04 1.43 1.63 0.43 6.16 6.40 2.27 2.29 ns

–1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns

–2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns

6 mA Std. 0.60 5.00 0.04 1.43 1.63 0.43 4.90 5.00 2.60 2.89 ns

–1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns

–2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns

8 mA Std. 0.60 5.00 0.04 1.43 1.63 0.43 4.90 5.00 2.60 2.89 ns

–1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns

–2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-43 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 3.70 0.04 1.43 1.63 0.43 3.66 3.70 2.27 2.37 ns

–1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns

–2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns

4 mA Std. 0.60 3.70 0.04 1.43 1.63 0.43 3.66 3.70 2.27 2.37 ns

–1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns

–2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns

6 mA Std. 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 ns

–1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns

–2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns

8 mA Std. 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 ns

–1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns

–2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-33

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-44 • Minimum and Maximum DC Input and Output Levels

1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA3

Max.

mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-45 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.910

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

35 pF for tZH / tZHS / tZL / tZLS

35 pF for tHZ / tLZ

ProASIC3 nano DC and Switching Characteristics

2-34 Revision 12

Timing Characteristics

Table 2-46 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 15.36 0.04 1.35 1.90 0.43 13.46 15.36 2.23 1.78 ns

–1 0.51 13.07 0.04 1.15 1.61 0.36 11.45 13.07 1.90 1.51 ns

–2 0.45 11.47 0.03 1.01 1.42 0.32 10.05 11.47 1.67 1.33 ns

4 mA Std. 0.60 10.32 0.04 1.35 1.90 0.43 9.92 10.32 2.63 2.78 ns

–1 0.51 8.78 0.04 1.15 1.61 0.36 8.44 8.78 2.23 2.37 ns

–2 0.45 7.71 0.03 1.01 1.42 0.32 7.41 7.71 1.96 2.08 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-47 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 11.42 0.04 1.35 1.90 0.43 8.65 11.42 2.23 1.84 ns

–1 0.51 9.71 0.04 1.15 1.61 0.36 7.36 9.71 1.89 1.57 ns

–2 0.45 8.53 0.03 1.01 1.42 0.32 6.46 8.53 1.66 1.37 ns

4 mA Std. 0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89 ns

–1 0.51 5.56 0.04 1.15 1.61 0.36 4.70 5.56 2.23 2.45 ns

–2 0.45 4.88 0.03 1.01 1.42 0.32 4.13 4.88 1.96 2.15 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-35

Table 2-48 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.52 0.04 1.35 1.90 0.43 7.99 8.52 2.23 1.78 ns

–1 0.51 7.25 0.04 1.15 1.61 0.36 6.80 7.25 1.90 1.51 ns

–2 0.45 6.36 0.03 1.01 1.42 0.32 5.97 6.36 1.67 1.33 ns

4 mA Std. 0.60 6.59 0.04 1.35 1.90 0.43 6.44 6.59 2.63 2.78 ns

–1 0.51 5.60 0.04 1.15 1.61 0.36 5.48 5.60 2.23 2.37 ns

–2 0.45 4.92 0.03 1.01 1.42 0.32 4.81 4.92 1.96 2.08 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-49 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 4.79 0.04 1.35 1.90 0.43 4.27 4.79 2.23 1.84 ns

–1 0.51 4.08 0.04 1.15 1.61 0.36 3.63 4.08 1.89 1.57 ns

–2 0.45 3.58 0.03 1.01 1.42 0.32 3.19 3.58 1.66 1.37 ns

4 mA Std. 0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89 ns

–1 0.51 2.74 0.04 1.15 1.61 0.36 2.75 2.74 2.23 2.45 ns

–2 0.45 2.40 0.03 1.01 1.42 0.32 2.42 2.40 1.95 2.15 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-36 Revision 12

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-50 • Minimum and Maximum DC Input and Output Levels

1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA3

Max.

mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-51 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 1.5 0.75 10

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

35 pF for tZH / tZHS / tZL / tZLS

35 pF for tHZ / tLZ

ProASIC3 nano Flash FPGAs

Revision 12 2-37

Timing Characteristics

Table 2-52 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 12.58 0.04 1.56 2.14 0.43 12.18 12.58 2.67 2.71 ns

–1 0.51 10.70 0.04 1.32 1.82 0.36 10.36 10.70 2.27 2.31 ns

–2 0.45 9.39 0.03 1.16 1.59 0.32 9.09 9.39 1.99 2.03 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-53 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83 ns

–1 0.51 6.68 0.04 1.32 1.82 0.36 5.49 6.68 2.26 2.41 ns

–2 0.45 5.87 0.03 1.16 1.59 0.32 4.82 5.87 1.99 2.12 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-54 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.01 0.04 1.56 2.14 0.43 8.03 8.01 2.67 2.71 ns

–1 0.51 6.81 0.04 1.32 1.82 0.36 6.83 6.81 2.27 2.31 ns

–2 0.45 5.98 0.03 1.16 1.58 0.32 6.00 5.98 2.10 2.03 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-55 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 3.76 0.04 1.52 2.14 0.43 3.74 3.76 2.66 2.83 ns

–1 0.51 3.20 0.04 1.32 1.82 0.36 3.18 3.20 2.26 2.41 ns

–2 0.45 2.81 0.03 1.16 1.59 0.32 2.79 2.81 1.99 2.12 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-38 Revision 12

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC3 nano Flash FPGAs

Revision 12 2-39

Table 2-56 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

Note: *See Figure 2-10 on page 2-38 for more information.

ProASIC3 nano DC and Switching Characteristics

2-40 Revision 12

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

Figure 2-11 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

ProASIC3 nano Flash FPGAs

Revision 12 2-41

Table 2-57 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

Note: *See Figure 2-11 on page 2-40 for more information.

ProASIC3 nano DC and Switching Characteristics

2-42 Revision 12

Input Register

Timing Characteristics

Figure 2-12 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

ISUE

50%

ISUD

IHD

50% 50%

ICLKQ

IHE

IRECPRE

IREMPRE

IRECCLR

IREMCLR

IWCLR

IWPRE

IPRE2Q

ICLR2Q

ICKMPWH

ICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-58 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-43

Output Register

Timing Characteristics

Figure 2-13 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

OSUE

50%

OSUD

OHD

50% 50%

OCLKQ

OHE

ORECPRE

OREMPRE

ORECCLR

OREMCLR

OWCLR

OWPRE

OPRE2Q

OCLR2Q

OCKMPWH

OCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-59 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-44 Revision 12

Output Enable Register

Timing Characteristics

Figure 2-14 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

OESUE

50%

OESUD

OEHD

50% 50%

OECLKQ

OEHE

OERECPRE

OEREMPRE

OERECCLR

OEREMCLR

OEWCLR

OEWPRE

OEPRE2Q

OECLR2Q

OECKMPWH

OECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-60 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.44 0.51 0.59 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-45

DDR Module Specifications

Input DDR Module

Figure 2-15 • Input DDR Timing Model

Table 2-61 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3 nano DC and Switching Characteristics

2-46 Revision 12

Timing Characteristics

Figure 2-16 • Input DDR Timing Diagram

DDRICLR2Q2

DDRIREMCLR

DDRIRECCLR

DDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

DDRICLKQ1

246

357

DDRIHD

DDRISUD

DDRICLKQ2

Table 2-62 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 ns

tDDRISUD Data Setup for Input DDR (Fall) 0.28 0.32 0.38 ns

Data Setup for Input DDR (Rise) 0.25 0.28 0.33 ns

tDDRIHD Data Hold for Input DDR (Fall) 0.00 0.00 0.00 ns

Data Hold for Input DDR (Rise) 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 ns

tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns

FDDRIMAX Maximum Frequency for Input DDR 350.00 350.00 350.00 MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-47

Output DDR Module

Figure 2-17 • Output DDR Timing Model

Table 2-63 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3 nano DC and Switching Characteristics

2-48 Revision 12

Timing Characteristics

Figure 2-18 • Output DDR Timing Diagram

116

910

28 3 9

DDROREMCLR

DDROHD1

DDROREMCLR

DDROHD2

DDROSUD2

DDROCLKQ

DDRORECCLR

CLK

Data_R

Data_F

CLR

Out

DDROCLR2Q

7104

Table 2-64 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 ns

FDDOMAX Maximum Frequency for the Output DDR 350.00 350.00 350.00 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-49

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing

characteristics are presented for a sample of the library. For more details, refer to the IGLOO, ProASIC3,

SmartFusion and Fusion Macro Library Guide.

Figure 2-19 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3 Y

NAND2

ProASIC3 nano DC and Switching Characteristics

2-50 Revision 12

Figure 2-20 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))

where edges are applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC3 nano Flash FPGAs

Revision 12 2-51

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a

data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a

representative sample from the library. For more details, refer to the IGLOO, ProASIC3, SmartFusion

and Fusion Macro Library Guide.

Table 2-65 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. Units

INV Y = !A tPD 0.40 0.46 0.54 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 ns

XOR2 Y = A Bt

PD 0.74 0.84 0.99 ns

MAJ3 Y = MAJ(A, B, C) tPD 0.70 0.79 0.93 ns

XOR3 Y = A  B Ct

PD 0.87 1.00 1.17 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for

derating values.

Figure 2-21 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC3 nano DC and Switching Characteristics

2-52 Revision 12

Timing Characteristics

Figure 2-22 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50% 50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-66 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.36 0.41 0.48 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-53

Global Resource Characteristics

A3PN250 Clock Tree Topology

Clock delays are device-specific. Figure 2-23 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-23 is driven by a CCC located on the west side of the A3PN250 device.

It is used to drive all D-flip-flops in the device.

Figure 2-23 • Example of Global Tree Use in an A3PN250 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC3 nano DC and Switching Characteristics

2-54 Revision 12

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-57. Ta bl e 2 -6 7 to Table 2-72 on page 2-56 present

minimum and maximum global clock delays within each device. Minimum and maximum delays are

measured with minimum and maximum loading.

Timing Characteristics

Table 2-67 • A3PN010 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2 Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.60 0.79 0.69 0.90 0.81 1.06 ns

tRCKH Input HIGH Delay for Global Clock 0.62 0.84 0.70 0.96 0.82 1.12 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.22 0.26 0.30 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-68 • A3PN015 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.66 0.91 0.75 1.04 0.89 1.22 ns

tRCKH Input HIGH Delay for Global Clock 0.67 0.96 0.77 1.10 0.90 1.29 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.29 0.33 0.39 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-55

Table 2-69 • A3PN020 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.66 0.91 0.75 1.04 0.89 1.22 ns

tRCKH Input HIGH Delay for Global Clock 0.67 0.96 0.77 1.10 0.90 1.29 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.29 0.33 0.39 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-70 • A3PN060 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.72 0.91 0.82 1.04 0.96 1.22 ns

tRCKH Input HIGH Delay for Global Clock 0.71 0.94 0.81 1.07 0.96 1.26 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.23 0.26 0.31 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-56 Revision 12

Table 2-71 • A3PN125 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.76 0.99 0.87 1.12 1.02 1.32 ns

tRCKH Input HIGH Delay for Global Clock 0.76 1.02 0.87 1.17 1.02 1.37 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-72 • A3PN250 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.79 1.02 0.90 1.16 1.06 1.36 ns

tRCKH Input HIGH Delay for Global Clock 0.78 1.04 0.88 1.18 1.04 1.39 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns

tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-57

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-73 • ProASIC3 nano CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Delay Increments in Programmable Delay Blocks 1,2 2003ps

Number of Programmable Values in Each Programmable Delay

Block

Serial Clock (SCLK) for Dynamic PLL 4,5 125 MHz

Input Cycle-to-Cycle Jitter (peak magnitude) 1.5 ns

Acquisition Time

LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter 7

LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay

11,2 1.25 15.65 ns

Delay Range in Block: Programmable Delay

21,2 0.025 15.65 ns

Delay Range in Block: Fixed Delay 1,2 2.2 ns

VCO Output Peak-to-Peak Period Jitter FCCC_OUT6Max Peak-to-Peak Jitter Data 6,8,9

SSO2 SSO4 SSO 8SSO 16

0.75 MHz to 50MHz 0.50% 0.50% 0.70% 1.00%

50 MHz to 250 MHz 1.00% 3.00% 5.00% 9.00%

250 MHz to 350 MHz 2.50% 4.00% 6.00% 12.00%

Notes:

1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.

2. TJ = 25°C, VCC = 1.5 V

3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help for more information.

4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

5. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.

6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying

the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For

example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.

7. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock

edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter

parameter.

8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI =

3.3 , VQ/PQ/TQ type of packages, 20 pF load.

9. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of

each other.

ProASIC3 nano DC and Switching Characteristics

2-58 Revision 12

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.

Figure 2-24 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC3 nano Flash FPGAs

Revision 12 2-59

Embedded SRAM and FIFO Characteristics

SRAM

Figure 2-25 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3 nano DC and Switching Characteristics

2-60 Revision 12

Timing Waveforms

Figure 2-26 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18.

Figure 2-27 • RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18.

CLK

[R|W]ADDR

BLK

WEN

DOUT|RD

CYC

CKH

CKL

BKS

ENS

ENH

DOH1

BKH

CKQ1

CLK

[R|W]ADDR

BLK

WEN

DOUT|RD

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC3 nano Flash FPGAs

Revision 12 2-61

Figure 2-28 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.

Figure 2-29 • RAM Write, Output as Write Data (WMODE = 1). Applicable to both RAM4K9 only.

CYC

CKH

CKL

BKS

ENS

ENH

CLK

BLK

WEN

[R|W]ADDR

DIN|WD

DOUT|RD

BKH

CYC

CKH

CKL

BKS

ENS

CLK

BLK

WEN

ADDR

DIN

BKH

DOUT

(pass-through) DI

DOUT

(pipelined) DI

ProASIC3 nano DC and Switching Characteristics

2-62 Revision 12

Figure 2-30 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.

CLK

RESET

DOUT|RD Dn

tCYC

tCKH tCKL

tRSTBQ

ProASIC3 nano Flash FPGAs

Revision 12 2-63

Timing Characteristics

Table 2-74 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tAS Address Setup time 0.25 0.28 0.33 ns

tAH Address Hold time 0.00 0.00 0.00 ns

tENS REN, WEN Setup time 0.14 0.16 0.19 ns

tENH REN, WEN Hold time 0.10 0.11 0.13 ns

tBKS BLK Setup time 0.23 0.27 0.31 ns

tBKH BLK Hold time 0.02 0.02 0.02 ns

tDS Input data (DIN) Setup time 0.18 0.21 0.25 ns

tDH Input data (DIN) Hold time 0.00 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on DOUT (output retained, WMODE = 0) 1.79 2.03 2.39 ns

Clock High to New Data Valid on DOUT (flow-through, WMODE = 1) 2.36 2.68 3.15 ns

tCKQ2 Clock High to New Data Valid on DOUT (pipelined) 0.89 1.02 1.20 ns

tC2CWWL1Address collision clk-to-clk delay for reliable write after write on same

address; applicable to closing edge

0.33 0.28 0.25 ns

tC2CWWH1Address collision clk-to-clk delay for reliable write after write on same

address; applicable to rising edge

0.30 0.26 0.23 ns

tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same

address; applicable to opening edge

0.45 0.38 0.34 ns

tC2CWRH1Address collision clk-to-clk delay for reliable write access after read on same

address; applicable to opening edge

0.49 0.42 0.37 ns

tRSTBQ RESET Low to Data Out Low on DOUT (flow through) 0.92 1.05 1.23 ns

RESET Low to Data Out Low on DOUT (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET Removal 0.29 0.33 0.38 ns

tRECRSTB RESET Recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns

tCYC Clock Cycle time 3.23 3.68 4.32 ns

FMAX Maximum Frequency 310 272 231 MHz

Notes:

1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for

Flash-Based FPGAs and SoC FPGAs App Note.

2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-64 Revision 12

Table 2-75 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tAS Address setup time 0.25 0.28 0.33 ns

tAH Address hold time 0.00 0.00 0.00 ns

tENS REN, WEN setup time 0.09 0.10 0.12 ns

tENH REN, WEN hold time 0.06 0.07 0.08 ns

tDS Input data (WD) setup time 0.18 0.21 0.25 ns

tDH Input data (WD) hold time 0.00 0.00 0.00 ns

tCKQ1 Clock High to new data valid on RD (output retained) 2.16 2.46 2.89 ns

tCKQ2 Clock High to new data valid on RD (pipelined) 0.90 1.02 1.20 ns

tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same

address; applicable to opening edge

0.50 0.43 0.38 ns

tC2CWRH1Address collision clk-to-clk delay for reliable write access after read on same

address; applicable to opening edge

0.59 0.50 0.44 ns

tRSTBQ RESET LOW to data out LOW on RD (flow-through) 0.92 1.05 1.23 ns

RESET LOW to data out LOW on RD (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET removal 0.29 0.33 0.38 ns

tRECRSTB RESET recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns

tCYC Clock cycle time 3.23 3.68 4.32 ns

FMAX Maximum frequency 310 272 231 MHz

Notes:

1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for

Flash-Based FPGAs and SoC FPGAs App Note.

2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3 nano Flash FPGAs

Revision 12 2-65

FIFO

Figure 2-31 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC3 nano DC and Switching Characteristics

2-66 Revision 12

Timing Waveforms

Figure 2-32 • FIFO Read

Figure 2-33 • FIFO Write

ENS

ENH

CKQ1

CKQ2

CYC

BKS

BKH

RCLK

RBLK

REN

(flow-through)

(pipelined)

WCLK

WEN

ENS

ENH

CYC

BKH

BKS

WBLK

ProASIC3 nano Flash FPGAs

Revision 12 2-67

Figure 2-34 • FIFO Reset

Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A

)

MPWRSTB

RSTFG

RSTCK

RSTAF

RCLK/

WCLK

RESET

EMPTY

AEMPTY

WA/RA

(Address Counter)

RSTFG

RSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

CKAF

RCKEF

EMPTY

AEMPTY

CYC

WA/RA

(Address Counter)

ProASIC3 nano DC and Switching Characteristics

2-68 Revision 12

Figure 2-36 • FIFO FULL Flag and AFULL Flag Assertion

Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 2-38 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

RCKEF

CKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

WCKF

CKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC3 nano Flash FPGAs

Revision 12 2-69

Timing Characteristics

Table 2-76 • FIFO

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tENS REN, WEN Setup Time 1.38 1.57 1.84 ns

tENH REN, WEN Hold Time 0.02 0.02 0.02 ns

tBKS BLK Setup Time 0.22 0.25 0.30 ns

tBKH BLK Hold Time 0.00 0.00 0.00 ns

tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns

tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.36 2.68 3.15 ns

tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns

tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns

tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns

tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns

tRSTFG RESET LOW to Empty/Full Flag Valid 1.69 1.93 2.27 ns

tRSTAF RESET LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns

tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns

RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET Removal 0.29 0.33 0.38 ns

tRECRSTB RESET Recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 ns

FMAX Maximum Frequency for FIFO 310 272 231 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3 nano DC and Switching Characteristics

2-70 Revision 12

Embedded FlashROM Characteristics

Timing Characteristics

Figure 2-39 • Timing Diagram

HOLD

CKQ2

CLK

Address

Data D

Table 2-77 • Embedded FlashROM Access Time

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 16.23 18.48 21.73 ns

FMAX Maximum Clock Frequency 15.00 15.00 15.00 MHz

ProASIC3 nano Flash FPGAs

Revision 12 2-71

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-12 for more details.

Timing Characteristics

Table 2-78 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time 0.53 0.60 0.71 ns

tDIHD Test Data Input Hold Time 1.07 1.21 1.42 ns

tTMSSU Test Mode Select Setup Time 0.53 0.60 0.71 ns

tTMDHD Test Mode Select Hold Time 1.07 1.21 1.42 ns

tTCK2Q Clock to Q (data out) 6.39 7.24 8.52 ns

tRSTB2Q Reset to Q (data out) 21.31 24.15 28.41 ns

FTCKMAX TCK Maximum Frequency 23.00 20.00 17.00 MHz

tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns

tTRSTREC ResetB Recovery Time 0.21 0.24 0.28 ns

tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for

derating values.

Revision 12 3-1

3 – Pin Descriptions and Packaging

Supply Pins

GND Ground

Ground supply voltage to the core, I/O outputs, and I/O logic.

GNDQ Ground (quiet)

Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise originated from the output buffer ground domain. This

minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always

be connected to GND on the board.

VCC Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine

in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,

both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.

VCCIBx I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to

eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a

separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,

1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied

to GND.

VMVx I/O Supply Voltage (quiet)

Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the

VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within

the package and improves input signal integrity. Each bank must have at least one VMV connection, and

no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to

provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or

3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV

and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to

the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).

VCCPLA/B/C/D/E/F PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V.

When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower

power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi

recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the

PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low

Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano FPGA Fabric User's

Guide for a complete board solution for the PLL analog power supply and ground.

There is one VCCPLF pin on ProASIC3 nano devices.

VCOMPLA/B/C/D/E/F PLL Ground

Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool

automatically disables the unused PLLs to lower power consumption. The user should tie unused

VCCPLx and VCOMPLx pins to ground.

There is one VCOMPLF pin on ProASIC3 nano devices.

VJTAG JTAG Supply Voltage

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank

Pin Descriptions and Packaging

3-2 Revision 12

gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG

interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to

GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can

be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals

will not be able to transition the device, even in bypass mode.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

VPUMP Programming Supply Voltage

ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For

programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming

power supply voltage (VPUMP) range is listed in the datasheet.

When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

User Pins

I/O User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os are instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

• Output buffer is disabled (with tristate value of high impedance)

• Input buffer is disabled (with tristate value of high impedance)

• Weak pull-up is programmed

GL Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power

Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano FPGA Fabric User's Guide. All

inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an

input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled

GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.

The inputs to the global network are multiplexed, and only one input can be used as a global input.

Refer to the I/O Structure chapter of the ProASIC3 nano FPGA Fabric User's Guide for an explanation of

the naming of global pins.

ProASIC3 nano Flash FPGAs

Revision 12 3-3

JTAG Pins

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to

operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a

separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB

design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST

pin could be tied to GND.

TCK Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-

up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor

placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Refer to Table 3-1

for more information.

TDI Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor

on the TDI pin.

TDO Test Data Output

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS Test Mode Select

The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST Boundary Scan Reset Pin

The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-

down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor

values must be chosen from Tab le 3- 1 and must satisfy the parallel resistance value requirement. The

values in Tab le 3- 1 correspond to the resistor recommended when a single device is used, and the

equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In

such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all VJTAG voltages, 500 W to 1 kW will satisfy the requirements.

Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG Tie-Off Resistance

VJTAG at 3.3 V 200  to 1 k

VJTAG at 2.5 V 200  to 1 k

VJTAG at 1.8 V 500  to 1 k

VJTAG at 1.5 V 500  to 1 k

Notes:

1. Equivalent parallel resistance if more than one device is on the JTAG chain

2. The TCK pin can be pulled up/down.

3. The TRST pin is pulled down.

Pin Descriptions and Packaging

3-4 Revision 12

Special Function Pins

NC No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

DC Do Not Connect

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.

Packaging

Semiconductor technology is constantly shrinking in size while growing in capability and functional

integration. To enable next-generation silicon technologies, semiconductor packages have also evolved

to provide improved performance and flexibility.

Microsemi consistently delivers packages that provide the necessary mechanical and environmental

protection to ensure consistent reliability and performance. Microsemi IC packaging technology

efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible

enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,

Microsemi offers a variety of packages designed to meet your most demanding application and economic

requirements for today's embedded and mobile systems.