TMS320F28377SZWTS - TEXAS INSTRUMENTS

September 2015 I

ProASIC3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)†

• FlashLock® Designed to Secure FPGA Contents

Low Power

• Low Power ProASIC®3 nano Products

• 1.5 V Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†

• True Dual-Port SRAM (except ×18 organization)†

Enhanced Commercial Temperature Range

•T

j = –20°C to +85°C

† A3PN030 and smaller devices do not support this feature.

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices A3PN010 A3PN0151A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices1A3PN030Z1,2 A3PN060Z1A3PN125Z1A3N250Z1

System Gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000

Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048

VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144

RAM Kbits (1,024 bits)2– – – – 18 36 36

4,608-Bit Blocks2––– – 4 8 8

FlashROM Kbits 1 1 1 1 1 1 1

Secure (AES) ISP2––– – YesYesYes

Integrated PLL in CCCs2––– – 1 1 1

VersaNet Globals 4 4 4 6 18 18 18

I/O Banks 2 3 3 2 2 2 4

Maximum User I/Os (packaged device) 34 49 49 77 71 71 68

Maximum User I/Os (Known Good Die) 34 – 52 83 71 71 68

Package Pins

QFN

VQFP

QN48 QN68 QN68 QN48, QN68

VQ100 VQ100 VQ100 VQ100

Notes:

1. Not recommended for new designs. Few devices/packages are obsoleted. For more information on obsoleted devices/packages, refer

to the PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.

2. A3PN030Z and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the DS0097: ProASIC3 Family Flash FPGAs Datasheet and DS0098:

ProASIC3E Flash Family FPGAs Datasheet.

Revision 12

DS0111

II Revision 12

I/Os Per Package

ProASIC3 nano Device Status

ProASIC3 nano Devices A3PN010 A3PN0151A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices1A3PN030Z1A3PN060Z1A3PN125Z1A3PN250Z1

Known Good Die 34 – 52 83 71 71 68

QN48 34 – – 34 – – –

QN68 – 49 49 49 – – –

VQ100 – – –77717168

Notes:

1. Not recommended for new designs.

2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide

to ensure compliance with design and board migration requirements.

3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G"

in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other

packages are RoHS-compliant only.

Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions

Packages QN48 QN68 VQ100

Length × Width (mm\mm) 6 x 6 8 x 8 14 x 14

Nominal Area (mm2) 36 64 196

Pitch (mm) 0.4 0.4 0.5

Height (mm) 0.90 0.90 1.20

ProASIC3 nano Devices Status ProASIC3 nano-Z Devices Status

A3PN010 Production

A3PN015 Not recommended for new designs.

A3PN020 Production

A3PN030Z Not recommended for new designs.

A3PN060 Production A3PN060Z Not recommended for new designs.

A3PN125 Production A3PN125Z Not recommended for new designs.

A3PN250 Production A3PN250Z Not recommended for new designs.

ProASIC3 nano Flash FPGAs

Revision 12 III

ProASIC3 nano Ordering Information

Devices Not Recommended For New Designs

A3PN015, A3PN030Z, A3PN060Z, A3PN125Z, and A3PN250Z are not recommended for new designs. For more information on

obsoleted devices/packages, refer to the PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.

Device Marking

Microsemi® normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some

of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited.

Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a

subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by

character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications

markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.

Figure 1 on page 1-IV shows an example of device marking based on the AGL030V5-UCG81.

Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt

trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input.

For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the

device.

A3PN010 = 10,000 System Gates

A3PN015 = 15,000 System Gates (A3PN015 is not recommended for new designs)

A3PN020 = 20,000 System Gates

A3PN030 = 30,000 System Gates

A3PN060 = 60,000 System Gates

A3PN125 = 125,000 System Gates

A3PN250 = 250,000 System Gates

Speed Grade

Blank = Standard

Feature Grade

Z = nano devices without enhanced features* (Not recommended for new designs)

3PN250 Z1VQ

Part Number

ProASIC3 nano Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

DIELOT =Known Good Die

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

100 YI

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (–20°C to +85°C Junction Temperature)

I = Industrial (–40°C to +100°C Junction Temperature)

Blank = Standard Packaging

G= RoHS-Compliant Packaging

PP= Pre-Production

ES= Engineering Sample (Room Temperature Only)

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Note: Only devices with packages greater than or equal to 5x5 are supported.

IV Revision 12

The actual mark will vary by the device/package combination ordered.

ProASIC3 nano Products Available in the Z Feature Grade

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Contact your local Microsemi SoC Products Group representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Figure 1 • Example of Device Marking for Small Form Factor Packages

Devices A3PN030* A3PN060* A3PN125* A3PN250*

Packages QN48 – – –

QN68 – – –

VQ100 VQ100 VQ100 VQ100

Note: *Not recommended for new designs.

ProASIC3 nano Devices A3PN010 A3PN015* A3PN020 A3PN060 A3PN125 A3PN250

ProASIC3 nano-Z Devices* A3PN030Z* A3PN060Z* A3PN125Z* A3PN250Z*

QN48 C, I – – C, I – – –

QN68 – C, I C, I C, I – – –

VQ100 – – – C, I C, I C, I C, I

Note: *Not recommended for new designs.

C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature.

I = Industrial temperature range: –40°C to +100°C junction temperature.

Temperature Grade Std.

C1

I2

Notes:

1. C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature.

2. I = Industrial temperature range: –40°C to +100°C junction temperature.

ACTELXXX

AGL030YWW

UCG81XXXX

XXXXXXXX

Country of Origin

Date Code

Customer Mark

(if applicable)

Device Name

(six characters)

Package

Wafer Lot #

ProASIC3 nano Flash FPGAs

Revision 12 V

Table of Contents

ProASIC3 nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3 nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Revision 12 1-1

1 – ProASIC3 nano Device Overview

General Description

ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano

devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3

nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These

features enable designers to create high-density systems using existing ASIC or FPGA design flows and

tools.

ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller

devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates,

supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and

packages for greater customer value in high volume consumer, portable, and battery-backed markets.

Added features include smaller footprint packages designed with two-layer PCBs in mind, low power,

hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external

boot PROM is required. On-board security mechanisms prevent access to all the programming

information and enable secure remote updates of the FPGA logic. Designers can perform secure remote

in-system reprogramming to support future design iterations and field upgrades with confidence that

valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using

the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for

ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC

replacement solution, especially for applications in the consumer, networking/communications,

computing, and avionics markets.

With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of

programmable logic and quick time to market.

Security

Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which

provides a unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest

level of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the

industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was

adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977

DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES

key that make them the most comprehensive programmable logic device security solution available

today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field

updates over public networks such as the Internet, and are designed to ensure that valuable IP remains

out of the hands of system overbuilders, system cloners, and IP thieves.

ProASIC3 nano Device Overview

1-2 Revision 12

Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security,

are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is

protected with industry-standard security, making remote ISP possible. A ProASIC3 nano device

provides the best available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano

FPGAs do not require system configuration components such as EEPROMs or micro-controllers to load

device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and

system reliability.

Instant On

Microsemi flash-based ProASIC3 nano devices support Level 0 of the Instant On classification standard.

This feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.

The Instant On feature of flash-based ProASIC3 nano devices greatly simplifies total system design and

reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used

for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the

ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to

be reloaded when system power is restored. This enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from

the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and

design risk while increasing system reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors

occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection

and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an

ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.

Advanced Flash Technology

ProASIC3 nano devices offer many benefits, including non-volatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

ProASIC3 nano Flash FPGAs

Revision 12 1-3

Advanced Architecture

The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs.

The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3

to Figure 1-4 on page 1-4):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Advanced I/O structure

Note: *Bank 0 for the A3PN030 device

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM

(A3PN010 and A3PN030)

Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and

A3PN020)

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1*

Bank 1

Bank 0

Bank 1

CCC-GL

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1

Bank 2

Bank 0

Bank 1

CCC-GL

ProASIC3 nano Device Overview

1-4 Revision 12

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT)

equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are

connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the

device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is

possible for virtually any design.

Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125)

Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ProASIC3 nano Flash FPGAs

Revision 12 1-5

VersaTiles

The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3 nano VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-5 for VersaTile configurations.

User Nonvolatile FlashROM

ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface.

The core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in

security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3 nano development software solutions, Libero® System-on-Chip (SoC) software and

Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential

programming files for applications requiring a unique serial number in each part. Another feature enables

the inclusion of static data for system version control. Data for the FlashROM can be generated quickly

and easily using Libero SoC and Designer software tools. Comprehensive programming file support is

also included to allow for easy programming of large numbers of parts with differing FlashROM contents.

Figure 1-5 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3 nano Device Overview

1-6 Revision 12

SRAM and FIFO

ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along

their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available

memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port. For

example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM

blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro

(except in A3PN030 and smaller devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures

provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and

A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices

use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any

PLLs or programmable delays.

For devices using the six CCC block architecture, these six CCC blocks are located at the four corners

and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the

FPGA core or from dedicated connections to the CCC block, which are located near the CCC.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC) (for PLL only)

Global Clocking

ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high fanout nets.

ProASIC3 nano Flash FPGAs

Revision 12 1-7

I/Os with Advanced I/O Standards

ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V).

The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of various single-data-rate applications for all versions of nano devices and double-data-

rate applications for the A3PN060, A3PN125, and A3PN250 devices.

ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support

cold-sparing and Schmitt trigger.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

ProASIC3 nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the

JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to

3.6 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-6 on page 1-8).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

ProASIC3 nano Device Overview

1-8 Revision 12

Z -Tri-State: I/O is tristated

6. Click OK to return to the FlashPoint – Programming File Generator window.

I/O States During programming are saved to the ADB and resulting programming files after completing

programming file generation.

Figure 1-6 • I/O States During Programming Window

Revision 12 2-1

2 – ProASIC3 nano DC and Switching Characteristics

General Specifications

The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing,

and hot-swap I/O capability. Refer to the "ProASIC3 nano Ordering Information" section on page III for

more information.

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Tabl e 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V V

TSTG 1Storage temperature –65 to +150 °C

TJ1Junction temperature +125 °C

Notes:

1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

3. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

ProASIC3 nano DC and Switching Characteristics

2-2 Revision 12

Table 2-2 • Recommended Operating Conditions 1, 2

Symbol Parameter

Extended

Commercial Industrial Units

TJJunction temperature –20 to +852–40 to +1002°C

VCC 31.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP 4Programming voltage Programming Mode43.15 to 3.45 3.15 to 3.45 V

Operation 50 to 3.6 0 to 3.6 V

VCCPLL 6Analog power supply (PLL) 1.5 V DC core supply voltage 31.425 to 1.575 1.425 to 1.575 V

VCCI and

VMV 71.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.3 V Wide Range supply voltage 82.7 to 3.6 2.7 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to

+85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures,

Microsemi recommends using custom settings for temperature range before running timing and power analysis tools.

For more information regarding custom settings, refer to the New Project Dialog Box in the Libero Online Help.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.

4. The programming temperature range supported is Tambient = 0°C to 85°C.

5. VPUMP can be left floating during operation (not programming mode).

6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.

7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for

further information.

8. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product

Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3 nano Flash FPGAs

Revision 12 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric

User’s Guide for information on clock and lock recovery.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle 2

Maximum Overshoot/

Undershoot 2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

ProASIC3 nano DC and Switching Characteristics

2-4 Revision 12

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional but slower because

VCCI / VCC are below specification.

For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min

VCCI

datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

eactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

but slower because VCCI

is below specification. For the

same reason, input buffers do

not meet VIH / VIL levels, and output

buffers do not meet VOH/VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3 nano Flash FPGAs

Revision 12 2-5

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

TJ = Junction Temperature = T + TA

EQ 1

where:

TA = Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = ja * P

ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is

ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

EQ 2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. (C)–

ja(C/W)

------------------------------------------------------------------------------------------------------------------------------------------ 100C70C–

20.5C/W

------------------------------------- 1.463 W

===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count jc

ja

UnitsStill Air 200 ft./min. 500 ft./min.

Quad Flat No Lead (QFN) All devices 48 TBD TBD TBD TBD C/W

68 TBD TBD TBD TBD C/W

100 TBD TBD TBD TBD C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 100°C

1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013

1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930

1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875

ProASIC3 nano DC and Switching Characteristics

2-6 Revision 12

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-7 • Quiescent Supply Current Characteristics

A3PN010 A3PN015 A3PN020 A3PN060 A3PN125 A3PN250

Typical (25°C) 600 µA 1 mA 1 mA 2 mA 2 mA 3 mA

Max. (Commercial) 5 mA 5 mA 5 mA 10 mA 10 mA 20 mA

Max. (Industrial) 8 mA 8 mA 8 mA 15 mA 15 mA 30 mA

Note: IDD includes VCC, VPUMP, and VCCI, currents.

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

VCCI (V) Dynamic Power, PAC9 (µW/MHz)1

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.45

3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.93

3.3 V LVCMOS wide range23.3 16.45

3.3 V LVCMOS wide range – Schmitt Trigger 3.3 18.93

2.5 V LVCMOS 2.5 4.73

2.5 V LVCMOS – Schmitt Trigger 2.5 6.14

1.8 V LVCMOS 1.8 1.68

1.8 V LVCMOS – Schmitt Trigger 1.8 1.80

1.5 V LVCMOS (JESD8-11) 1.5 0.99

1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.96

Notes:

1. PAC9 is the total dynamic power measured on VCCI.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

ProASIC3 nano Flash FPGAs

Revision 12 2-7

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD (pF) 2VCCI (V) Dynamic Power, PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 162.01

3.3 V LVCMOS wide range410 3.3 162.01

2.5 V LVCMOS 10 2.5 91.96

1.8 V LVCMOS 10 1.8 46.95

1.5 V LVCMOS (JESD8-11) 10 1.5 32.22

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. Values for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 correspond to a

default loading of 35 pF.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

ProASIC3 nano DC and Switching Characteristics

2-8 Revision 12

Power Consumption of Various Internal Resources

Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Dynamic Contributions

(µW/MHz)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PAC1 Clock contribution of a Global Rib 11.03 11.03 9.3 9.3 9.3 9.3

PAC2 Clock contribution of a Global Spine 1.58 0.81 0.81 0.4 0.4 0.4

PAC3 Clock contribution of a VersaTile row 0.81

PAC4 Clock contribution of a VersaTile used as a

sequential module

0.12

PAC5 First contribution of a VersaTile used as a

sequential module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a

combinatorial Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 2-8 on page 2-6.

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Table 2-9 on page 2-7.

PAC11 Average contribution of a RAM block during a read

operation

25.00 N/A

PAC12 Average contribution of a RAM block during a write

operation

30.00 N/A

PAC13 Dynamic contribution for PLL 2.60 N/A

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power

spreadsheet calculator or SmartPower tool in Libero SoC.

Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Static Power (mW)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PDC1 Array static power in Active mode See Table 2-7 on page 2-6.

PDC4 Static PLL contribution 12.55 N/A

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.

Notes:

1. Minimum contribution of the PLL when running at lowest frequency.

2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet

calculator or SmartPower tool in Libero SoC.

ProASIC3 nano Flash FPGAs

Revision 12 2-9

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock generated

• The number of combinatorial and sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on

page 2-11.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-13 on

page 2-11.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-13 on page 2-11. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's

Guide.

NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's

Guide.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

ProASIC3 nano DC and Switching Characteristics

2-10 Revision 12

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* 1 / 2