4S71WS256/128/064J_CSA0 October 27, 2004
Advance Information
DQ6: Toggle Bit I ................................................................................................83
Figure 7. Toggle Bit Algorithm.............................................. 84
DQ2: Toggle Bit II .............................................................................................. 84
Table 19. DQ6 and DQ2 Indications ..................................... 85
Reading Toggle Bits DQ6/DQ2 ..................................................................... 85
DQ5: Exceeded Timing Limits ....................................................................... 86
DQ3: Sector Erase Timer ................................................................................ 86
Table 20. Write Operation Status ......................................... 87
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .88
Figure 8. Maximum Negative Overshoot Waveform................. 88
Figure 9. Maximum Positive Overshoot Waveform .................. 88
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 10. Test Setup ......................................................... 91
Table 21. Test Specifications ............................................... 91
Key to Switching Waveforms . . . . . . . . . . . . . . . 91
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 91
Figure 11. Input Waveforms and Measurement Levels............. 91
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92
V
CC
Power-up ..................................................................................................... 92
Figure 12. V
CC
Power-up Diagram ........................................ 92
CLK Characterization ....................................................................................... 92
Figure 13. CLK Characterization ........................................... 92
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .93
Synchronous/Burst Read @ V
IO
= 1.8 V ......................................................93
Figure 14. CLK Synchronous Burst Mode Read
(rising active CLK).............................................................. 94
Figure 15. CLK Synchronous Burst Mode Read
(Falling Active Clock) .......................................................... 94
Figure 16. Synchronous Burst Mode Read.............................. 95
Figure 17. 8-word Linear Burst with Wrap Around................... 95
Figure 18. Linear Burst with RDY Set One Cycle Before Data.... 96
Asynchronous Mode Read @ V
IO
= 1.8 V ..................................................97
Figure 19. Asynchronous Mode Read with Latched Addresses ... 98
Figure 20. Asynchronous Mode Read..................................... 98
Figure 21. Reset Timings..................................................... 99
Erase/Program Operations @ V
IO
= 1.8 V ................................................100
Figure 22. Asynchronous Program Operation Timings: AVD#
Latched Addresses ........................................................... 101
Figure 23. Asynchronous Program Operation Timings: WE#
Latched Addresses ........................................................... 102
Figure 24. Synchronous Program Operation Timings: WE# Latched
Addresses ....................................................................... 103
Figure 25. Synchronous Program Operation Timings: CLK Latched
Addresses ....................................................................... 104
Figure 26. Chip/Sector Erase Command Sequence................ 105
Figure 27. Accelerated Unlock Bypass Programming Timing ... 106
Figure 28. Data# Polling Timings
(During Embedded Algorithm)............................................ 107
Figure 29. Toggle Bit Timings (During Embedded Algorithm).. 107
Figure 30. Synchronous Data Polling
Timings/Toggle Bit Timings................................................ 108
Figure 31. DQ2 vs. DQ6 .................................................... 108
Temporary Sector Unprotect .......................................................................109
Figure 32. Temporary Sector Unprotect Timing Diagram........ 109
Figure 33. Sector/Sector Block Protect and Unprotect Timing
Diagram.......................................................................... 110
Figure 34. Latency with Boundary Crossing.......................... 111
Figure 35. Latency with Boundary Crossing into Program/Erase
Bank .............................................................................. 112
Figure 36. Example of Wait States Insertion ........................ 113
Figure 37. Back-to-Back Read/Write Cycle Timings ............... 114
CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . .117
Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Asynchronous Operation (Page Mode) .......................................................118
Functional Description . . . . . . . . . . . . . . . . . . . . . 119
Synchronous Operation (Burst Mode) ........................................................119
State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Initial/Standby State ...........................................................................................120
Figure 38. Initial Standby State Diagram ............................ 120
Asynchronous Operation State ....................................................................120
Figure 39. Asynchronous Operation State Diagram............... 120
Synchronous Operation State ........................................................................121
Figure 40. Synchronous Operation Diagram ........................ 121
Functional Description . . . . . . . . . . . . . . . . . . . . . 121
Power-up ...............................................................................................................121
Configuration Register ......................................................................................121
CR Set Sequence ................................................................................................121
Power Down .......................................................................................................124
Burst Read/Write Operation .........................................................................124
Figure 41. Burst Read Operation........................................ 125
Figure 42. Burst Write Operation ....................................... 125
CLK Input Function ..........................................................................................125
ADV# Input Function .......................................................................................126
WAIT# Output Function ................................................................................126
Figure 43. Read Latency Diagram ...................................... 127
Address Latch by ADV# .................................................................................128
Burst Length ........................................................................................................128
Single Write .........................................................................................................128
Write Control ....................................................................................................129
Figure 44. Write Controls.................................................. 129
Burst Read Suspend ..........................................................................................129
Figure 45. Burst Read Suspend Diagram............................. 130
Burst Write Suspend ........................................................................................130
Figure 46. Burst Write Suspend Diagram ............................ 130
Burst Read Termination ..................................................................................130
Figure 47. Burst Read Termination Diagram........................ 131
Burst Write Termination .................................................................................131
Figure 48. Burst Write Termination Diagram........................ 131
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 132
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 132
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 133
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 134
Read Operation .................................................................................................134
Write Operation ...............................................................................................136
Synchronous Operation - Clock Input (Burst Mode) ............................ 137
Synchronous Operation - Address Latch (Burst Mode) ....................... 137
Synchronous Read Operation (Burst Mode) ............................................138
Synchronous Write Operation (Burst Mode) ..........................................139
Power Down Parameters ...............................................................................140
Other Timing Parameters ...............................................................................140
AC Test Conditions .........................................................................................140
AC Measurement Output Load Circuit ......................................................141
Figure 49. Output Load Circuit........................................... 141
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 50. Asynchronous Read Timing #1-1 (Basic Timing) ... 142
Figure 51. Asynchronous Read Timing #1-2 (Basic Timing) ... 142