TECHNICAL DATA
403
Octal 3-State Noninverting
Transparent Latch
High-Perform ance Silicon-Gate C MOS
The IN74HC573A is identical in pinout to the LS/ALS573. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC573A
ORDERING INFORMATION
IN74HC573AN Plastic
IN74HC573ADW SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Output
Output
Enable Latch
Enable DQ
LHH H
LHL L
L L X no change
HXX Z
X = don’t care
Z = high impedanc e
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
IN74HC573A
404
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IN74HC573A
405
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Max imu m Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 6.0 mA
IOUT ≤ 7.8 mA 4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Max imu m Low-Level
Output Voltage VIN= VIL or VIH
IOUT ≤ 20 µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
IOUT ≤ 6.0 mA
IOUT ≤7.8 mA 4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum In put
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three
State Leakage
Current
Output in High-I mpedance
State
VIN =VIH or VIL
VOUT= VCC or GND
6.0 ±0.5 ±5.0 ±10 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA6.0 4.0 40 160 µA
IN74HC573A
406
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C
to
-55°C
≤85°C≤125°CUnit
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5) 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH, tPHL Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5) 2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6) 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZH, tPZL Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6) 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5) 2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN Maximum Input Capacitance - 10 10 10 pF
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State) -151515pF
Power Dissipation Capacitance (Per Enabled
Output) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumpti on: P D=CPDVCC2f+ICCVCC
23 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C≤85°C≤125°CUnit
tSU Minimum Setup Time , Input D
to Latch Enable
(Figure 4)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
thMinimum Hold Time, Latch
Enable to Input D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
twMinimum Pulse Wid th, Latch
Enable (Figure 2) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, tfMaximum Input Rise and Fall
Times ( F igure 1) 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
IN74HC573A
407
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
