© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 2
1Publication Order Number:
P2027A/D
P2027A
General Purpose EMI
Reduction IC
Description
The P2027 is a versatile spread spectrum frequency modulator
designed specifically for digital camera and other digital video and
imaging applications. The P2027 reduces electromagnetic interference
(EMI) at the clock source, which provides system wide reduction of
EMI of all clock dependent signals. The P2027 allows significant
system cost savings by reducing the number of circuit board layers and
shielding that are traditionally required to pass EMI regulations.
The P2027 uses the most efficient and optimized modulation profile
approved by the FCC and is implemented in a proprietary all−digital
method.
The P2027 modulates the output of a single PLL in order to “spread”
the bandwidth of a synthesized clock and, more importantly, decreases
the peak amplitudes of its harmonics. This results in significantly
lower system EMI compared to the typical narrow band signal
produced by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread spectrum
clock generation.’
Applications
The P2027 is targeted towards DSC market as well as other imaging
and digital video applications like DVD and VCD players.
Features
•FCC Approved Method of EMI Attenuation
•Provides up to 20 dB of EMI Suppression
•Generates a Low EMI Spread Spectrum Clock of the Input
Frequency
•Optimized for 27 MHz Operation
•Internal Loop Filter Minimizes External Components and Board
Space
•3 Selectable Spread Ranges and 2 Modulation Rate Options
•SSON Control Pin for Spread Spectrum Enable and Disable Options
•Low Cycle−to−Cycle Jitter
•3.3 V Operating Voltage
•16 mA Output Drives
•TTL or CMOS Compatible Outputs
•Low Power CMOS Design
•Supports Digital Camera and Other Digital Video and Imaging
Applications
•Available in 8−pin SOIC and TSSOP Packages
•These are Pb−Free Devices
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SOIC−8
S SUFFIX
CASE 751BD
PIN CONFIGURATION
(Top View)
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
VDD
SR0
ModOUT
SSON
XOUT
MRA
XIN / CLKIN
1
VSS
TSSOP−8
T SUFFIX
CASE 948AL
P2027A
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VCO
PLL
VSS
ModOUT
VDD
Output
Divider
Loop Filter
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Modulation
MRA SR0 SSON
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin# Pin Name Type Description
1XIN / CLKIN ICrystal connection or external reference frequency input. This pin has dual functions. It can
be connected to either an external crystal or an external reference clock.
2 XOUT O Crystal connection. Input connection for an external crystal. If using an external reference,
this pin must be left unconnected.
3 MRA I Digital logic input used to select Modulation Rate (see Table 2). This pin has an internal
pull−up resistor.
4 VSS P Ground Connection. Connect to system ground.
5 SSON I Digital logic input used to enable Spread Spectrum function (Active Low). Spread Spectrum
function enable when low. This pin has an internal pull−low resistor.
6 ModOUT O Spread Spectrum Clock Output.
7 SR0 I Digital logic input used to select Spreading Range (see Table 2). This pin has an internal
pull−up resistor.
8 VDD P Connect to +3.3 V Power Supply.
Table 2. MODULATION AND SPREADING SELECTION
MRA SR0 Spread Range Modulation Rate
0 0 Reserve Reserve
0 1 ±0.30% (Fin/10)*34.72 KHz
1 0 ±0.20% (Fin/10)*20.83 KHz
1 1 ±0.60% (Fin/10)*20.83 KHz
P2027A
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Spread Spectrum Selection
Table 2 illustrates the possible spread spectrum options.
The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading
is described as a percentage deviation of the center
frequency (Note: the center frequency is the frequency of the
external reference input on CLKIN, Pin 1).
Example:
P2027 is designed for DSC and digital video and imaging
markets and is optimized for 27 MHz under minimum
deviation settings. Selecting P2027’s spread options to
MRA=1 and SR0=1 for a 27 MHz input signal provides
a percentage deviation of ±0.60% (see Table 2) from the
reference signal. This results in frequency on ModOUT
being swept from 27.16 MHz to 26.84 MHz at a modulation
rate of 56.24 KHz (see Table 2). This particular example (see
the below figure) given here is a new EMI reduction method
for DSC applications and is already gaining popularity
among leading manufacturers.
Figure 2. Application Schematic for Digital Still Camera
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Rating Unit
VDD, VIN Voltage on any pin with respect to Ground −0.5 to +4.6 V
TSTG Storage temperature −65 to +125 °C
TAOperating temperature 0 to 70 °C
TsMax. Soldering Temperature (10 sec) 260 °C
TJJunction Temperature 150 °C
TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
P2027A
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Table 4. DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
VIL Input Low Voltage GND−0.3 −0.8 V
VIH Input High Voltage 2.0 −VDD + 0.3 V
IIL Input Low Current (pull−up resistor on inputs FS0, SR0 and MRA) − − −35 mA
IIH Input High Current (pull−down resistor on input SSON) − − 35 mA
IXOL XOUT Output Low Current (@ 0.4 V, VDD = 3.3 V) −3−mA
IXOH XOUT Output High Current (@ 2.5 V, VDD = 3.3 V) −3−mA
VOL Output Low Voltage (VDD = 3.3 V, IOL = 20 mA) − − 0.4 V
VOH Output High Voltage (VDD = 3.3 V, IOH = 20 mA) 2.5 − − V
IDD Static Supply Current −6.0 −mA
ICC Dynamic Supply Current (3.3 V and 15 pF loading) 6.0 7.0 8.3 mA
VDD Operating Voltage 2.7 3.3 3.8 V
tON Power Up Time (First locked clock cycle after power up) 0.18 ms
ZOUT Clock Output Impedance 50 W
Table 5. AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
fIN Input Frequency 10 27 30 MHz
tLH (Note 1) Output rise time (Measured at 0.8 V to 2.0 V) 0.7 0.9 1.1 ns
tHL (Note 1) Output fall time (Measured at 0.8 V to 2.0 V) 0.6 0.8 1.0 ns
tJC Jitter (cycle−to−cycle) − − 360 ps
tDOutput duty cycle 45 50 55 %
1. tLH and tHL are measured into a capacitive load of 15 pF.
P2027A
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PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
P2027A
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
P2027A
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Table 6. ORDERING CODES
Part Number Marking Package Type Temperature
P2027AF−08ST P2027AF 8−PIN SOIC, TUBE, Pb Free Commercial
P2027AF−08SR P2027AF 8−PIN SOIC, TAPE AND REEL, Pb Free Commercial
P2027AF−08TT P2027AF 8−PIN TSSOP, TUBE, Pb Free Commercial
P2027AF−08TR P2027AF 8−PIN TSSOP, TAPE AND REEL, Pb Free Commercial
P2027AG−08ST P2027AG 8−PIN SOIC, TUBE, Green Commercial
P2027AG−08SR P2027AG 8−PIN SOIC, TAPE AND REEL, Green Commercial
P2027AG−08TT P2027AG 8−PIN TSSOP, TUBE, Green Commercial
P2027AG−08TR P2027AG 8−PIN TSSOP, TAPE AND REEL, Green Commercial
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P2027A/D
PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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