HD74AC175
Quad D-Type Flip-Flop
ADE-205-377 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-
High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when Low.
Features
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA
HD74AC175
2
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MR
Q0
Q0
D0
D1
Q1
Q1
GND
VCC
Q3
Q3
D3
D2
Q2
Q2
CP
(Top view)
Logic Symbol
CP D0
Q0Q0Q1Q1Q2Q2Q3Q3
D1D2D3
MR
Pin Names
D0 to D3Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0 to Q3True Outputs
Q0 to Q 3 Complement Outputs
HD74AC175
3
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs Outputs
@ tn, MR = H @ tn+1
Dn Qn Qn
LL H
HH L
H : High Voltage Level
L : Low Voltage Level
tn: Bit Time before Clock Pulse
tn + 1: Bit Time after Clock Pulse
Logic Diagram
D0
D
CP
CDQ
Q0Q0
Q
D1
D
CP
CDQ
Q1Q1
Q
D2
D
CP
CDQ
Q2Q2
Q
D3CPMR
D
CP
CDQ
Q3Q3
Q
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
HD74AC175
4
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current ICC 80 µAV
IN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current ICC 8.0 µAV
IN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
AC Characteristics
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Maximum clock fmax 3.3 149 — — 139 — MHz
frequency 5.0 187 — — 187 —
Propagation delay tPLH 3.3 1.0 9.5 12.0 1.0 13.5 ns
CP to Qn or Qn5.0 1.0 7.0 9.0 1.0 9.5
Propagation delay tPHL 3.3 1.0 8.5 13.0 1.0 14.5 ns
CP to Qn or Qn5.0 1.0 6.0 9.5 1.0 10.5
Propagation delay tPLH 3.3 1.0 7.5 12.5 1.0 13.5 ns
MR to Qn5.0 1.0 5.5 9.0 1.0 10.0
Propagation delay tPHL 3.3 1.0 8.5 11.0 1.0 12.5 ns
MR to Qn5.0 1.0 6.0 8.5 1.0 9.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
HD74AC175
5
AC Operating Requirements
Ta = +25°C
CL = 50 pF
Ta = –40°C
to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Typ Guaranteed Minimum Unit
Set-up time, HIGH or LOW tsu 3.3 2.0 4.5 4.5 ns
Dn to CP 5.0 1.0 3.0 3.0
Hold time, HIGH or LOW th3.3 0 1.0 1.0 ns
Dn to CP 5.0 0 1.0 1.0
CP pulse width HIGH or LOW tw3.3 2.5 4.5 4.5 ns
5.0 2.0 3.5 3.5
MR pulse width, LOW tw3.3 2.5 4.5 5.0 ns
5.0 2.0 3.5 3.5
Recovery time MR to CP trec 3.3 –2.0 0.0 0.0 ns
5.0 –1.0 0.0 0.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitance CIN 4.5 pF VCC = 5.5 V
Power dissipation capacitance CPD 45.0 pF VCC = 5.0 V
HD74AC175
6
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
6.30
19.20
16 9
81 1.3
20.00 Max
7.40 Max
7.62
0.25
+ 0.13
– 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0° – 15°
1.11 Max
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-16DA
—
Conforms
0.24 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.22 ± 0.05
*0.42 ± 0.08
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0° – 8°
0.10 ± 0.10
1.15
1.27
0.40 ± 0.06
0.20 ± 0.04
HD74AC175
7
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
1.27
16 9
18
0.15
0.25
M
1.75 Max 3.95
*0.22 ± 0.03
9.9
0° – 8°
10.3 Max
+ 0.10
– 0.30
6.10
+ 0.67
– 0.20
0.60
+ 0.11
– 0.04
0.14
*0.42 ± 0.08
0.635 Max
0.40 ± 0.06
0.20 ± 0.03
1.08
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
TTP-16DA
—
—
0.05 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.50 ± 0.10
0° – 8°
*0.17 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
18
16 9
4.40
5.00
5.30 Max
0.07
+0.03
–0.04
0.65 Max
1.0
0.20 ± 0.06
+ 0.08
– 0.07
*0.22
0.15 ± 0.04
HD74AC175
8
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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