Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com JULY '06
DS679F1
Low Power, Stereo CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
98 dB Dynamic Range (A-wtd)
-86 dB THD+N
Headphone Amplifier - GND Centered
– On-Chip Charge Pump Provides -VA_HP
– No DC-Blocking Capacitor Required
– 46 mW Power Into Stereo 16 Ω @ 1.8 V
– 88 mW Power Into Stereo 16 Ω @ 2.5 V
– -75 dB THD+N
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
– PCM + ADC Mix w/Independent Vol Control
– Master Digital Volume Control
– Soft Ramp & Zero Cross Transitions
Beep Generator
– Tone Selections Across Two Octaves
– Separate Volume Control
– Programmable On & Off Time Intervals
– Continuous, Periodic or One-Shot Beep
Selections
Programmable Peak-Detect and Limiter
Pop and Click Suppression
ANALOG to DIGITAL FEATURES
98 dB Dynamic Range (A-wtd)
-88 dB THD+N
Analog Gain Controls
– +32 dB or +16 dB MIC Pre-Amplifiers
– Analog Programmable Gain Amplifier
(PGA)
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold and
Attack/Release Rates
Independent Channel Control
Digital Volume Control
High-Pass Filter Disable for DC Measurements
Stereo 3:1 Analog Input MUX
Dual MIC Inputs
– Programmable, Low Noise MIC Bias Levels
– Differential MIC Mix for Common Mode
Noise Rejection
Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
1.8 V to 3.3 V
Multibit
∆Σ Modulator
Charge
Pump
Left HP O ut
Right HP Out
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Serial Audio
Input
Serial Audio
Output
1.8 V to 2.5 V 1.8 V to 2.5 V
MUX
PGA
PCM Serial Interface
Register
Configuration
Level Translator
Reset
Hardware
Mode or I2C &
SPI So ftw are
Mode
Control D ata
Stereo Input 1
Stereo Input 2
Stereo Input 3 /
Mic Input 1 & 2
PGA
+32 dB
+32 dB
Volume
Controls
Beep
Generator
MUX
MUX
Headphone
Amp - GND
Centered
Headphone
Amp - GND
Centered
ALC
MIC
Bias
1.8 V to 2.5 V
MUX
MUX
Switched
Capacitor DAC
and Filter
Switched
Capacitor DAC
and Filter
High Pass
Filters
ALC
Digital
Signal
Processing
Engine
CS42L51
2DS679F1
CS42L51
SYSTEM FEATURES
24-bit Converters
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Oper ation
– Stereo Playback: 12.93 mW @ 1.8 V
– Stereo Record and Playback: 20.18 mW @
1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– ADC, DAC, CODEC, MIC Pre-Amplifier,
PGA
Software Mode (I²C® & SPI™ Control)
Hardware Mode (Stand-Alone Control)
Digital Routing/Mixes:
– Analog Out = ADC + Digital In
– Digital Out = ADC + Digital In
– Internal Digital Loopback
– Mono Mixes
Flexible Clocking Options
– Master or Slave Operation
– High-Impedance Digital Output Option (for
easy MUXing between CODEC and Other
Data Sources)
– Quarter-Speed Mode - (i.e. Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
APPLICATIONS
HDD & Flash-Based Portable Audio Players
MD Players/Recorders
PDAs
Personal Media Players
Portable Game Consoles
Digital Voice Recorders
Digital Camcorders
Digital Cameras
Smart Phones
GENERAL DESCRIPTION
The CS42L51 is a highly integr ated , 24-b it, 96 kHz, low
power stereo CODEC. Based on multi-bit, delta-sigma
modulation, it allows infinite sample rate adjustment be-
tween 4 kHz and 96 kHz. Both the ADC and DAC offer
many features suitable for low power, portable system
applications.
The ADC input path allows independent channel control
of a number of feat ures. An input multiplexer selects b e-
tween line-level or microphone level inputs for each
channel. The microphone input path includes a select-
able programmable-gain pre-amplifier stage and a low
noise MIC bias voltage supply. A PGA is available for
line or microphone inp uts and provides analog gain with
soft ramp and zero cross transition s. The ADC also fea-
tures a digital volume attenuator with soft ramp
transitions. A progr ammable ALC and Noise Gate mon-
itor the input signals and adjust the volume levels
appropriately.
The DAC output pa th includes a digital signal pr ocess-
ing engine. Tone Control provides bass and treble
adjustment of four selectable corner frequencies. The
Mixer allows independent volume control for both the
ADC mix and the PCM mix, as well as a master digital
volume control for the analog output. All volume level
changes may be configured to occur on soft ramp and
zero cross transitions. The DAC also includes de-em-
phasis, limiting functions and a beep generator
delivering tones selectable across a range of two full
octaves.
The stereo headphon e amplifier is powered from a sep-
arate positive supply and the integrated charge pump
provides a negative supply. This allows a ground-cen-
tered analog output with a wide signal swing and
eliminates external DC-blocking capacitors.
In addition to its many features, the CS42L51 operates
from a low-voltage analog and digital core, making this
CODEC ideal for portable systems that require ex-
tremely low power consumption in a minimal amount of
space.
The CS42L51 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85 ° C). The CDB42L51 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 85 for complete details.
DS679F1 3
CS42L51
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 7
1.1 Digital I/O Pin Characteristics ........................................................................................................... 9
2. TYPICAL CONNECTION DIAGRAMS .................................................................................................10
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 12
SPECIFIED OPERATING CONDITIONS ............................................................................................. 12
ABSOLUTE MAXIMUM RATINGS .......................................................................................................12
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 13
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 14
ADC DIGITAL FILTER CHAR ACTERI S TI CS .... ... ... ... .... ... ................... ... .... ... ................... ... .... ... ... ...... 15
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 16
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ................ ... ... .... ... ... ................... ... 17
LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 18
HEADPHONE OUTP UT POWER CHARA CTERISTI CS ......... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 19
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 20
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT .................................................................. 22
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT ............................................................ 23
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 24
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 24
POWER CONSUMPTION .................................................................................................................... 25
4. APPLICATIONS ................................................................................................................................... 26
4.1 Overview ......................................................................................................................................... 26
4.1.1 Architecture ........................................................................................................................... 26
4.1.2 Line & MIC Inputs .................................................................................................................. 26
4.1.3 Line & Headphone Outputs ................................................................................................... 26
4.1.4 Signal Processing Engine ..................................................................................................... 26
4.1.5 Beep Generator ..................................................................................................................... 26
4.1.6 Device Control (Hardware or Software Mode) ...................................................................... 26
4.1.7 Power Management .............................................................................................................. 26
4.2 Hardware Mode .............................................................................................................................. 27
4.3 Analog Inputs ................................................................................................................................. 28
4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 28
4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 29
4.3.3 Digital Routing ....................................................................................................................... 29
4.3.4 Differential Inputs .................................................................................................................. 29
4.3.4.1 External Passive Components ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ...... 29
4.3.5 Analog Input Multiplexer ........................................................................................................ 31
4.3.6 MIC & PGA Gain ................................................................................................................... 31
4.3.7 Automatic Level Control (ALC) .............................................................................................. 32
4.3.8 Noise Gate ............................................................................................................................ 33
4.4 Analog Outputs ............................................................................................................................... 34
4.4.1 De-Emphasis Filter ................................................................................................................ 34
4.4.2 Volume Controls .................................................................................................................... 35
4.4.3 Mono Channel Mixer ............................................................................................................. 35
4.4.4 Beep Generator ..................................................................................................................... 35
4.4.5 Tone Control .......................................................................................................................... 36
4.4.6 Limiter .................................................................................................................................... 36
4.4.7 Line-Level Outputs and Filtering ........................................................................................... 37
4.4.8 On-Chip Charge Pump .......................................................................................................... 38
4.5 Serial Port Clocking ........................................................................................................................ 38
4.5.1 Slave ..................................................................................................................................... 39
4.5.2 Master ................................................................................................................................... 39
4DS679F1
CS42L51
4.5.3 High-Impedance Digital Output ............................................................................................. 40
4.5.4 Quarter- and Half-Speed Mode .............................................................................................40
4.6 Digital Interface Formats ................................................................................................................ 40
4.7 Initialization ..................................................................................................................................... 41
4.8 Recommended Power-Up Sequence .............................................................................................41
4.9 Recommended Power-Down Sequence ........................................................................................ 42
4.10 Software Mode ............................................................................................................................. 43
4.10.1 SPI Control .......................................................................................................................... 43
4.10.2 I²C Control ........................................................................................................................... 43
4.10.3 Memory Address Pointer (MAP) .......................................................................................... 45
4.10.3.1 Map Increment (INCR) ............................................................................................. 45
5. REGISTER QUICK REFERENCE ........................................................................................................ 46
6. REGISTER DESCRIPTION .................................................................................................................. 49
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 49
6.2 Power Control 1 (Address 02h) ...................................................................................................... 49
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 50
6.4 Interface Control (Address 04h) ..................................................................................................... 52
6.5 MIC Control (Address 05h) ............................................................................................................. 53
6.6 ADC Control (Address 06h) ............................................................................................................ 54
6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 56
6.8 DAC Output Control (Address 08h) ................................................................................................ 57
6.9 DAC Control (Address 09h) ............................................................................................................ 58
6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ............... 59
6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 60
6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 61
6.13 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 62
6.14 Beep Frequency & Timing Configuration (Address 12h) .............................................................. 62
6.15 Beep Off Time & Volume (Address 13h) ................ ... ... ... .... ... ... ................... .... ... ... ... ...................63
6.16 Beep Configuration & Tone Conf iguration (Address 14h) ... ... ...................................................... 64
6.17 Tone Control (Address 15h) ......................................................................................................... 65
6.18 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 66
6.19 PCM Channel Mixer (Address 18h) .............................................................................................. 67
6.20 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 67
6.21 Limiter Release Rate Register (Address 1Ah) .............................................................................. 69
6.22 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 70
6.23 ALC Enable & Attack Rate (Address 1Ch) ...................................................................................70
6.24 ALC Release Rate (Address 1Dh) ............. ............. ......... ............. ............. ............. ............. ......... 71
6.25 ALC Threshold (Address 1Eh) ...................................................................................................... 71
6.26 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 72
6.27 Status (Address 20h) (Read Only) ............................................................................................... 73
6.28 Charge Pump Frequency (Address 21h) ...................................................................................... 74
7. ANALOG PERFORMANCE PLOTS .......... ... .................... ... ... .... ... ... ... ... .... ... ... ................... .... ... ... ... ...75
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 75
7.2 Headphone Amplifier Efficiency ...................................................................................................... 77
7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 78
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 79
8.1 Auto Detect Enabled ....................................................................................................................... 79
8.2 Auto Detect Disabled ...................................................................................................................... 80
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 81
9.1 Power Supply, Grounding ............................................................................................................... 81
9.2 QFN Thermal Pad .......................................................................................................................... 81
10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 82
DS679F1 5
CS42L51
11. PARAMETER DEFINITIONS ....... .... ... ... ... ... .... ... ... ... .... ... ................... ... .... ... ... ... .... ............................ 83
12. PACKAGE DIMENSIONS .......... .... ... ... ... .................... ... ... ... .................... ... ... ... .... ............................ 84
THERMAL CHARACTERISTICS ........................................................................................................84
13. ORDERING INFORMATIO N ............. ... ... ... .... ... ... ... .................... ... ... ... .... ... ................... ... .... ... ......... 85
14. REFERENCES ... .... ... ... ... .... ... ................... ... .... ... ... .................... ... ... ... .................... ... ... ...................... 85
15. REVISION HISTORY ..... .... ... ... ... .... ... ... ... ... .... ................... ... .... ... ................... ... .... ... ... ...................... 86
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ...........................................................................10
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 11
Figure 3.Headphone Output Test Load ..................................................................................................... 19
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 21
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 21
Figure 6.Control Port Timing - I²C ............................................................................................................. 22
Figure 7.Control Port Timing - SPI Format ................................................................................................ 23
Figure 8.Analog Input Architecture ............................................................................................................ 28
Figure 9.MIC Input Mix w/Common Mode Rejection .................................................................................30
Figure 10.Differential Input ........................................................................................................................ 30
Figure 11.ALC ........................................................................................................................................... 32
Figure 12.Noise Gate Attenuation ............................................................................................................. 33
Figure 13.Output Architecture ................................................................................................................... 34
Figure 14.De-Emphasis Curve .................................................................................................................. 35
Figure 15.Beep Configuration Options ...................................................................................................... 36
Figure 16.Peak Detect & Limiter ............................................................................................................... 37
Figure 17.Master Mode Timing ................................................................................................................. 39
Figure 18.Tri-State Serial Port ..... ... ... .... ... ... ... ... .... ... ... .................... ... ... ... ... .... ... ... ... .... ... ......................... 40
Figure 19.I²S Format ................................................................................................................................. 40
Figure 20.Left-Justified Format ................................................................................................................. 41
Figure 21.Right-Justified Format (DAC only) ............................................................................................ 41
Figure 22.Initialization Flowchart ............................................................................................................... 42
Figure 23.Control Port Timing in SPI Mode ........... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ................... ......... 43
Figure 24.Control Port Timing, I²C Write ................................................................................................... 44
Figure 25.Control Port Timing, I²C Read ................................................................................................... 44
Figure 26.AIN & PGA Selection ................................................................................................................ 56
Figure 27.T HD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 75
Figure 28.T HD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 75
Figure 29.T HD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 76
Figure 30.T HD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 76
Figure 31.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................77
Figure 32.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) . ... ... ... .................... ... ... ... ... 77
Figure 33.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 78
Figure 34.ADC Passband Ripple .............................. ... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... ................ 82
Figure 35.ADC Stopband Rejection .......................................................................................................... 82
Figure 36.ADC Transition Band ................................................................................................................ 82
Figure 37.ADC Transition Band Detail ...................................................................................................... 82
Figure 38.DAC Passband Ripple .............. ... ... .................... ... ... ... .... ... ... ... ... .... ... ................... ... ................ 82
Figure 39.DAC Stopband .......................................................................................................................... 82
Figure 40.DAC Transition Band ................................................................................................................ 82
Figure 41.DAC Transition Band (Detail) .................................................................................................... 82
6DS679F1
CS42L51
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 9
Table 2. Hardware Mode Feature Summary ............................................................................................. 27
Table 3. MCLK/LRCK Ratios .................................................................................................................... 39
DS679F1 7
CS42L51
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
Pin Name # Pin Description
LRCK 1Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDA/CDIN
(MCLKDIV2) 2Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
SCL/CCLK
(I²S/LJ)3Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Sele cts between I²S & Left-Justified interface for-
mats for the ADC & DAC.
AD0/CS
(DEM) 4Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filte r.
VA_HP 5Analog Power For Headphone (Input) - Positive pow er for the internal analog headphone section.
FLYP 6Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
GND_HP 7Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.
FLYN 8Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
VSS_HP 9Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-
phone section.
109
8
7
6
5
4
3
2
1
11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
CS42L51
VD
DGND
SDOUT (M/S)
MCLK
SDIN
SCLK
VSS_HP
AOUTB
AOUTA
VA
AGND
DAC_FILT+
ADC_FILT+
VQ
SDA/CDIN (MCLKDIV2)
SCL/CCLK (I²S/LJ)
ADO/CS (DEM)
FLYP
VL
RESET
GND_HP
FLYN
AFILTA
AIN1A
AIN1B
AIN2A
AIN2B/BIAS
MICIN1/AIN3A
MICIN2/BIAS/AIN3B
AFILTB
VA_HP
LRCK
8DS679F1
CS42L51
AOUTB
AOUTA 10
11 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-
tics specification table
VA 12 Analog Power (Input) - Positive power for the internal analog section.
AGND 13 Analog Grou nd (Input) - Ground reference for the internal analog secti on.
DAC_FILT+ 14 Positive Voltage Reference (Output) - Positive reference vol tage for the internal sampling circuits.
VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
ADC_FILT+ 16 Positive Voltage Reference (Output) - Positive reference vol tage for the internal sampling circuits.
MICIN1/
AIN3A 17 Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-
cation table.
MICIN2/
BIAS/AIN3B 18 Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics
specification table. This pin can also be configured as an output to provide a low noise bias supply for an
external microphone. Electrical characteristics are specified in the DC Electrical Cha r acteristics table.
AIN2A 19 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
AIN2B/BIAS 20 Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-
cation table. This pin can also be configured as an output to provide a low noise bias supply for an exter-
nal microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
AFILTA
AFILTB 21
22 Filter Co nnection (Output) - Filter connection for the ADC inputs.
AIN1A
AIN1B 23
24 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
RESET 25 Reset (Input) - The device enters a low power mode when this pin is driven low.
VL 26 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and
host control port. Refer to the Recommended Operating Conditions for appropriate voltages.
VD 27 Digital Power (Input) - Positive power for the internal dig ital section.
DGND 28 Digital Ground (Input) - Ground reference for the internal digital section.
SDOUT
(M/S)29 Serial Audio Data Output (Output) - Output for two’s compleme nt seri al au d io da ta.
Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.
MCLK 30 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 31 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 32 Serial Audio Dat a Input (Input) - Input for two’s complement serial audio data.
Thermal Pad -Thermal relief pad for optimiz e d hea t di ssi pation. Se e “QFN Thermal Pad” on page 81.
DS679F1 9
CS42L51
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply.
Pin Name
SW/(HW) I/O Driver Receiver
RESET Input - 1.8 V - 3.3 V
SCL/CCLK
(I²S/LJ)Input - 1.8 V - 3.3 V, with Hysteresis
SDA/CDIN
(MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis
AD0/CS
(DEM) Input - 1.8 V - 3.3 V
MCLK Input - 1.8 V - 3.3 V
LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
SCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
SDOUT
(M/S)Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
SDIN Input - 1.8 V - 3.3 V
Table 1. I/O Power Rails
10 DS679F1
CS42L51
2. TYPICAL CONNECTION DIAGRAMS
1 µF
+1.8 V or +2.5 V
1 µF
VQ
DAC_FILT+
0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8 V, +2.5 V
or +3.3 V
SCL/CCLK
SDA/CDIN
RESET
2 k Ω
See Note 1
LRCK
AGND
AD0/CS
MCLK
SCLK
0.1 µF
VA_HP
VD
* Capacitors must be C0G o r equivalent
150 pF
AFILTA
AFILTB
MICIN1
AIN3A Microphone Input
150 pF
SDIN
SDOUT
CS42L51
2 k Ω
1 µF
BIAS2
AIN3B/MICIN2
**
+1.8 V or +2.5 V
AOUTB
AOUTA
470 Ω
470 Ω
C
CRext
Rext
See Note 2
AIN1A Left Analog Input 1
1800 pF
1800 pF
100 kΩ
100 Ω
AIN1B Right Analog Input 1
*
*
Note 1:
Resistors are required for I²C
control po r t operation
For best r esponse to Fs/2 :
()
4704470
×
+
=
ext
ext
RFs
R
C
π
This circuitry is intended for applications where the
CS42L51 connec ts directly to an unbal anced output of the
device. For internal routing applications please se e the
DAC Analog Output Characteristics section for loadi ng
limitations.
Note 2 :
RLSee Note 3
Note 3: The value of RL is dicta ted
by the mi crophone cartridge.
Digital Audio
Processor
0.1 µF
VA
Headphone O ut
Left & Right
Line Level Out
Left & Right
Speaker Driver
AIN2A Left Analog Input 2
1800 pF
1800 pF
AIN2B
BIAS1 Right Analog Input 2
*
*
FLYP
FLYN
VSS_HP
GND_HP
1 µF
10 µF
ADC_FILT+
Microphone Bias
1 µF
1 µF
1 µF
1 µF
1 µF
0.1 µF
51.1 Ω
0.022 µF
100 kΩ
100 Ω
100 Ω
100 Ω
100 kΩ
100 kΩ
100 kΩ
1 µF **
**
* *Use low ESR ceramic ca pacitors.
See Note 4
Note 4:
Series resi stance in the path of the power supplies must
be avoided. Any voltage drop on VA_HP will directly
impact the negative charge pump supply (VSS_ HP) and
result in clipping on the audio output.
1.5 µF
1.5 µF
See Note 5
Note 5 :
Larger capacitors , such as 1.5 µF, improves the char ge
pump performance (and su bsequent THD+N) at the full
scale outpu t power achieved with gain (G) settings
greater than default.
**
**
Figure 1. Typical Connection Diagram (Software Mode)
DS679F1 11
CS42L51
+1.8V or +2 .5V
1 µF
VQ
DAC_FILT+
0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8V, 2.5 V
or +3.3V
I²S/LJ
MCLKDIV2
RESET
LRCK
AGND
DEM
MCLK
SCLK
0.1 µF
VA_HP
VD
* Capacitors must be C0G or equivalent
150 pF
AFILTA
AFILTB
150 pF
SDIN
SDOUT/
M/S
CS42L51
1 µF
**
+1.8 V or +2 .5V
AOUTB
AOUTA
470Ω
470Ω
C
CRext
Rext
See Note 2
AIN1A Left Analog Input 1
1800 pF
1800 pF
100 kΩ
100 kΩ
100 Ω
100 Ω
AIN1B Right Analog Input 1
*
*
For best resp ons e to Fs/2 :
()
4704470
×
+
=
ext
ext
RFs
R
C
π
This circuitry is intended for applications where the CS42L51 connects directly to an unbalanced output of the device. For
internal routing applications please see the DAC Analog Output Characteristics section for loading limitations .
Note 2 :
Digital Audio
Processor
0.1 µF
VA
Headphone Out
Left & Right
Line Level Out
Left & Right
Speaker Driver
FLYP
FLYN
VSS_HP
GND_HP
10 µF
ADC_FILT+
1 µF
1 µF
51.1 Ω
0.022 µF
VL or DGND (1)
1 µF See Note 4
Note 4:
Series resistance in the path of the power supplies (typically
used for added filtering) must be avoided. Any voltage drop
on VA_HP will directly impact the negative cha rge pump
supply (VSS_HP) and result in clipping on the audio output.
1 µF
1 µF **
**
* *Use low ESR ceramic capacitors.
(1) Pull-up to VL (47 kΩ for Master Mode.
Pull-down to DGND for Slave Mode.
Figure 2. Typical Conn ection Diagram (Hardware Mode)
12 DS679F1
CS42L51
3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from me asure ments taken at nominal supply voltages and
TA = 25° C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and
serial/control port interface supplies.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
Parameters Symbol Min Nom Max Units
DC Power Supply (Note 1)
Analog Core VA 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Headphone Amplifier VA_HP 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Digital Core VD 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Serial/Control Port Interface VL 1.65
2.37
3.14
1.8
2.5
3.3
1.89
2.63
3.47
V
V
V
Ambient Temperature Commercial - CNZ
Automotive - DNZ TA-10
-40 -
-+70
+85 °C
°C
Parameters Symbol Min Max Units
DC Power Supply Analog
Digital
Serial/Control Port Interface
VA, VA_HP
VD
VL
-0.3
-0.3
-0.3
3.0
3.0
4.0
V
V
V
Input Current (Note 2) Iin -±10mA
Analog Input Voltage VIN AGND-0.7 VA+0.7 V
Digital Input Voltage
(Note 3) VIND -0.3 VL+ 0.4 V
Ambient Operating Temperature (power applied) TA-50 +115 °C
St orage Temperature Tstg -65 +150 °C
DS679F1 13
CS42L51
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specifie d): Input sine wave (relative to digital full scale): 1 kHz through passive
input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 5) Min Typ Max Min Typ Max Unit
Analog In to ADC (PGA bypassed)
Dynamic Range A-weighted
unweighted 93
90 99
96 -
-90
87 96
93 -
-dB
dB
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
-
-
-
-86
-76
-36
-80
-
-
-
-
-
-84
-73
-33
-78
-
-
dB
dB
dB
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted 92
89 98
95 -
-89
86 95
92 -
-dB
dB
PGA Setting: +12 dB A-weighted
unweighted 85
82 91
88 -
-82
79 88
85 -
-dB
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
-60 dBFS -
--88
-35 -81
--
--86
-32 -80
-dB
dB
PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted -
-86
83 -
--
-83
80 -
-dB
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS --76- --74-dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted -
-78
74 -
--
-75
71 -
-dB
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS --74- --71-dB
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch -0.2- -0.2-dB
Gain Drift - ±100 - - ±100 - ppm/°C
Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB
Input
Interchannel Isolation -90--90-dB
DAC Isolation (Note 4) -70--70-dB
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
0.74•VA
0.75•VA 0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA 0.74•VA
0.75•VA 0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA Vpp
Vpp
Vpp
Vpp
Input Impedance (No te 6) ADC
PGA
MIC
-
-
-
20
39
50
-
-
-
-
-
-
20
39
50
-
-
-
kΩ
kΩ
kΩ
14 DS679F1
CS42L51
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input
filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
4. Measured with DAC delivering full-scale output power into 16 Ω.
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 5) Min Typ Max Min Typ Max Unit
Analog In to ADC
Dynamic Range A-weighted
unweighted 91
78 99
96 -
-88
85 96
93 -
-dB
dB
Total Harmonic Distortion + Noise -1 dB FS
-20 dBFS
-60 dBFS
-
-
-
-86
-76
-36
-78
-
-
-
-
-
-84
-73
-33
-76
-
-
dB
dB
dB
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted 90
87 98
95 -
-87
84 95
92 -
-dB
dB
PGA Setting: +12 dB A-weighted
unweighted 83
80 91
88 -
-80
77 88
85 -
-dB
dB
Total Harmonic Distortion + Nois e
PGA Setting: 0 dB -1 dBFS
-60 dBFS -
--88
-35 -80
--
--86
-32 -78
-dB
dB
PGA Setting: +12 dB -1 dBFS - -85 -77 - -83 -75 dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted -
-86
83 -
--
-83
80 -
-dB
dB
Total Harmonic Distortion + Nois e
PGA Setting: 0 dB -1 dBFS --76---74-dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted -
-78
74 -
--
-75
71 -
-dB
dB
Total Harmonic Distortion + Nois e
PGA Setting: 0 dB -1 dBFS --74---71-dB
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Gain Drift - ±100 - - ±100 - ppm/°C
Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB
Input
Interchannel Isolation -90--90-dB
DAC Isolation (Note 4) -70--70-dB
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
0.74•VA
0.75•VA 0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA 0.74•VA
0.75•VA 0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA Vpp
Vpp
Vpp
Vpp
Input Impedance (Note 6) ADC
PGA
MIC
18
40
50
-
-
-
-
-
-
18
40
50
-
-
-
-
-
-
kΩ
kΩ
kΩ
DS679F1 15
CS42L51
5. Referred to the typical full-scale voltage . Applies to all THD+N and Dynamic Range values in the table.
6. Measured between AINxx and AGND.
ADC DIGITAL FILTER CHARACTERISTICS
7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figure 33 to Figure 41)
have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF param-
eters are for Fs = 48 kHz.
Parameter (Note 7) Min Typ Max Unit
Passband (Frequency Response) to -0.1 dB corner 0 - 0.4948 Fs
Passband Ripple -0.09 - 0.17 dB
Stopband 0.6 - - Fs
Stopband Attenuation 33 - - dB
Total Group Delay - 7.6/Fs - s
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB -
-3.7
24.2 -
-Hz
Hz
Phase Devia ti o n @ 20 Hz -10-Deg
Passband Ripple - - 0.17 dB
Filter Settling Time -10
5/Fs 0 s
16 DS679F1
CS42L51
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone o utput. HP_GAIN[2:0] = 011.)
Parameter (Note 8) VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Nois e
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-86
-75
-35
-86
-73
-33
-78
-
-
-
-
-
-
-
-
-
-
-
-88
-72
-32
-88
-70
-30
-82
-
-
-
-
-
dB
dB
dB
dB
dB
dB
RL = 16 Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Nois e
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-75
-75
-35
-75
-73
-33
-69
-
-
-
-
-
-
-
-
-
-
-
-75
-72
-32
-75
-70
-30
-69
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Other Characteristics for RL = 16
Ω
or 10 k
Ω
Output Parameters Modulation Index (MI)
(Note 9) Analog Gain Multiplier (G) -0.6787
0.6047 --
0.6787
0.6047 -
Full-scale Output Voltage (2•G•MI•VA) (Note 9) Refer to Table “Line Output Voltage Characteristics” on
page 18 Vpp
Full-scale Outpu t Power (Note 9) Refer to Table “Headphone Output Power Characteristics”
on page 19 mW
Interchannel Isolation (1 kHz) 16 Ω
10 kΩ
-
-80
95 -
--
-80
93 -
-dB
dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°
C
AC-Load Resistance (RL)(Note 10) 16 - - 16 - - Ω
Load Capacitance (CL)(Note 10) - - 150 - - 150 pF
DS679F1 17
CS42L51
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the
line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output.
HP_GAIN[2:0] = 011.)
Parameter (Note 8) VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
90
87
-
-
98
95
96
93
-
-
-
-
87
84
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-86
-75
-35
-86
-73
-33
-73
-
-
-
-
-
-
-
-
-
-
-
-88
-72
-32
-88
-70
-30
-80
-
-
-
-
-
dB
dB
dB
dB
dB
dB
RL = 16
Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
90
87
-
-
98
95
96
93
-
-
-
-
87
84
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-75
-75
-35
-75
-73
-33
-67
-
-
-
-
-
-
-
-
-
-
-
-75
-72
-32
-75
-70
-30
-67
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Other Characteristics for RL = 16
Ω
or 10 k
Ω
Output Parameters Modulation Index (MI)
(Note 9) Analog Gain Multiplier (G) -0.6787
0.6047 --
0.6787
0.6047 -
Full-scale Output Voltage (2•G•MI•VA) (Note 9) Refer to Table “Line Output Voltage Characteristics” on
page 18 Vpp
Full-scale Output Power (Note 9) Refer to Table “Headphone Output Power Characteristics”
on page 19 mW
Interchannel Isolation (1 kHz) 16 Ω
10 kΩ
-
-80
95 -
--
-80
93 -
-dB
dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°
C
AC-Load Resistance (RL)(Note 10) 16 - - 16 - - Ω
Load Capacitance (CL)(Note 10) - - 150 - - 150 pF
18 DS679F1
CS42L51
LINE OUTPUT VOLTAGE CHARACTERISTICS
Test conditions (unless otherwise specified): Inp ut test signal is a fu ll-scale 997 Hz sine wave; measurement band-
width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3).
Parameter VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
AOUTx Voltage Into RL = 10 k
Ω
HP_GAIN[2:0] Analog
Gain (G) VA_HP
000 0.3959 1.8 V - 1.34 - - 0.97 - Vpp
2.5 V - 1.34 - - 0.97 - Vpp
001 0.4571 1.8 V - 1.55 - - 1.12 - Vpp
2.5 V - 1.55 - - 1.12 - Vpp
010 0.5111 1.8 V - 1.73 - - 1.25 - Vpp
2.5 V - 1.73 - - 1.25 - Vpp
011 (defaul t) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 Vpp
2.5 V 1.95 2.05 2.15 - 1.48 - Vpp
100 0.7099 1.8 V - 2.41 - - 1.73 - Vpp
2.5 V - 2.41 - - 1.73 - Vpp
101 0.8399 1.8 V - 2.85 - 2.05 Vpp
2.5 V - 2.85 - - 2.05 - Vpp
110 1.0000 1.8 V - 3.39 - - 2.44 - V pp
2.5 V - 3.39 - - 2.44 - Vpp
111 1.1430 1.8 V (See (Note 11) 2.79 Vpp
2.5 V - 3.88 - - 2.79 - Vpp
DS679F1 19
CS42L51
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band-
width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3).
8. One-half LSB of tr iangular PDF dither is added to data.
9. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain (HP_GAIN[2:0])” on page 57. High gain settings at certain VA and VA_HP supply levels may
cause clipping when the audio signal approaches full-scale, maximum power output, as shown in
Figures 27 - 30 on page 76.
10. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance re-
quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-
mended 150 pF can cause the internal op-amp to become unstab le.
11. VA_HP settings lower than VA r educes the headroom of the headphone amp lifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power .
Parameter VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
AOUTx Power Into RL = 16
Ω
HP_GAIN[2:0] Analog
Gain (G) VA_HP
000 0.3959 1.8 V - 14 - - 7 - mWrms
2.5 V - 14 - - 7 - mWrms
001 0.4571 1.8 V - 19 - - 10 - mWrms
2.5 V - 19 - - 10 - mWrms
010 0.5111 1.8 V - 23 - - 12 - mWrms
2.5 V - 23 - - 12 - mWrms
011 (default) 0 .6047 1.8 V (Note 11) -17 -mW
rms
2.5 V - 32 - - 17 - mWrms
100 0.7099 1.8 V (Note 11) -23 -mW
rms
2.5 V - 44 - - 23 - mWrms
101 0.8399 1.8 V (Note 9) mWrms
2.5 V -32 -mW
rms
110 1.0000 1.8 V (Note 9, 11)mWrms
2.5 V mWrms
111 1.1430 1.8 V mWrms
2.5 V mWrms
AOUTx
AGND
RL
CL
0.022 µF
51 Ω
Figure 3. Headphone Output Test Load
20 DS679F1
CS42L51
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Notes: 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 38 to Figure 41
on page 82) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
Parameter (Note 12) Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corne r
to -3 dB corner 0
0-
-0.4780
0.4996 Fs
Fs
StopBand 0.5465 - - Fs
St opBand Attenuation (Note 13) 50 - - dB
Group Delay - 10.4/Fs - s
De-emphasis Error Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
Parameters Symbol Min Max Units
RESET pin Low Pulse Width (Note 14) 1-ms
MCLK Frequency 1.024 38.4 MHz
MCLK Duty Cycle (Note 15) 45 55 %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
Fs
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP-64•F
sHz
SCLK Duty Cycle 45 55 %
LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns
LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns
SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns
SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
DS679F1 21
CS42L51
14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies.
16. See
17. “Master” on page 39
18. “MCLK” refers to the external master clock applied.
Master Mode (Note 17)
Output Sample Rate (LRCK) All Speed Modes
(Note 17) Fs-Hz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP- 64•FsHz
SCLK Duty Cycle 45 55 %
LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns
SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns
SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
Parameters Symbol Min Max Units
MCLK
128
-----------------
th(SK-SDO)
//
//
//
//
//
//
//
//
ts(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
td(MSB)
ts(LK-SK) tP
th
ts(SDO-SK)
Figure 4. Serial Audio Interface Slave Mode Timing
th(SK-SDO)
//
//
//
//
//
//
//
//
ts(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
td(MSB)
tP
th
ts(SDO-SK)
Figure 5. Serial Audio Interface Master Mode Timing
22 DS679F1
CS42L51
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RESET Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 19) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc -1µs
Fall T ime SCL and SDA tfc - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Fallin g tack 300 3450 ns
tbuf thdst thdst
tlow tr
tf
thdd
thigh
tsud tsust
tsusp
Stop Start Start Stop
Repeated
SDA
SCL
tirs
RST
Figure 6. Control Port Timing - I²C
DS679F1 23
CS42L51
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT
(Inputs: Logic 0 = DGND , Lo gic 1 = VL)
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For fsck <1 MHz.
Parameter Symbol Min Max Units
CCLK Clock Frequency fsck 06.0MHz
RESET Rising Edge to CS Falling tsrs 20 - ns
CS Falling to CCLK Edge tcss 20 - ns
CS High Time Between Transmissions tcsh 1.0 - µs
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 20) tdh 15 - ns
Rise T ime of CCLK and CDIN (Note 21) tr2 -100ns
Fall Time of CCLK and CDIN (Note 21) tf2 -100ns
CS
CCLK
CDIN
RST tsrs
tscl
tsch
tcss tr2
tf2
tcsh
tdsu tdh
Figure 7. Control Port Timing - SPI Format
24 DS679F1
CS42L51
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
22. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
23. Valid with the recommended ca pacitor va lue s on DAC_FILT +, ADC_FILT+ a nd VQ . Increa sing the ca-
pacitance will also increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
24. See “Digital I/O Pin Characteristics” on page 9 for serial and control port power rails.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 22 )
-
-
-
0.5•VA
23
-
-
-
10
V
kΩ
µA
DAC_FILT+ Nominal Voltage
ADC_FILT+ Nominal Voltage -
-VA
VA -
-V
V
VSS_HP Characteristics
Nominal Voltage
DC Current Source -
--0.8•(VA_HP) -
10 V
µA
MIC BIAS Characteristics
Nominal Vol tage MICBIAS_LVL[1:0] = 00
MICBIAS_LVL[1:0] = 01
MICBIAS_LVL[1:0] = 10
MICBIAS_LVL[1:0] = 11
DC Current Source
Power Supply Rejection Ratio (PSRR) 1 kHz
-
-
-
-
-
-
0.8•VA
0.7•VA
0.6•VA
0.5•VA
-
50
-
-
-
-
1
-
V
V
V
V
mA
dB
Power Supply Rejection Ratio (PSRR) (Note 23) 1 kHz -60-dB
Parameters (Note 24) Symbol Min Max Units
Input Leakage Current Iin -±10µA
Input Capacit ance -10pF
1.8 V - 3.3 V Logic
High-Level Output Vol tage (IOH = -100 µA) VOH VL - 0.2 - V
Low-Level Output Voltage (IOL = 100 µA) VOL -0.2V
High-Level Input Voltage VIH 0.68•VL - V
Low-Level Input Voltage VIL - 0.32•VL V
DS679F1 25
CS42L51
POWER CONSUMPTION
See (Note 25)
25. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
26. RESET pin 25 held LO, all clocks and data lines are held LO.
27. RESET pin 25 held HI, all clocks and data lines are held HI.
28. VL current will slightly increase in master mode.
Power Ctl. Registers Typical Current (mA)
Operation
02h 03h
PDN_DACB
PDN_DACA
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
PDN_MICB
PDN_MICA
PDN_MICBIAS
V
iVA_HP iVA iVD iVL
(Note 28) Total
Power
(mWrms)
1Off (Note 26) xxxxxxxxxx1.8 0 0 0 0 0
2.5 0 0 0 0 0
2 Standby (Note 27) xxxxxx1xxx1.8 0 0.01 0.02 0 0.05
2.5 0 0.01 0.03 0 0.10
3 Mono Record ADC11111001111.8 0 1.85 2.03 0.03 7.05
2.5 0 2.07 3.05 0.05 12.94
PGA to ADC 11101001111.8 0 2.35 2.03 0.03 7.95
2.5 0 2.58 3.08 0.05 14.29
MIC to PGA to ADC
(with Bias) 11101001001.8 0 3.67 2.05 0.03 10.36
2.5 0 3.95 3.09 0.05 17.71
MIC to PGA to ADC
(no Bias) 11101001011.8 0 3.27 2.03 0.03 9.61
2.5 0 3.52 3.08 0.05 16.62
4 Stereo Record ADC11110001111.8 0 2.69 2.12 0.03 8.72
2.5 0 2.93 3.18 0.04 15.40
PGA to ADC 11000001111.8 0 3.65 2.12 0.03 10.45
2.5 0 3.91 3.17 0.04 17.84
MIC to PGA to ADC
(no Bias) 11000000011.8 0 5.48 2.11 0.03 13.73
2.5 0 5.76 3.17 0.04 22.45
5 Mono Playback 10111101111.8 1.66 1.40 2.35 0.01 9.74
2.5 2.03 1.71 3.48 0.02 18.08
6 Stereo Playback 00111101111.8 2.77 2.05 2.35 0.01 12.93
2.5 3.21 2.50 3.49 0.02 23.02
7Mono Record & Playback
PGA in (no MIC) to Mono Out 10101001111.8 1.66 3.63 2.73 0.03 14.49
2.5 2.03 4.16 4.08 0.05 25.79
8Phone Monitor
MIC (w/bias) in to Mono Out 10101001001.8 1.66 4.95 2.75 0.03 16.90
2.5 2.03 5.52 4.08 0.05 29.20
9Stereo Record & Playback
PGA in (no MIC) to Stereo Out 00000001111.8 2.77 5.59 2.82 0.03 20.18
2.5 3.21 6.28 4.19 0.04 34.30
26 DS679F1
CS42L51
4. APPLICATIONS
4.1 Overview
4.1.1 Architecture
The CS42L51 is a highly integrated, lo w power, 24-bit audio CODEC comprised of stereo analog-to-digital
converters (ADC), and stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma
techniques. The DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where
Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining
high performance. The CODEC operates in one of four sample rate speed modes: Quarter, Half, Single
and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input
Master Clock (MCLK).
4.1.2 Line & MIC Inputs
The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and micr ophone (MIC) source s. Six line inputs with configuration for two MIC inputs (or one MIC
input with common mode rejection), two MIC bias outputs and independent channel control (including a
high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Au-
tomatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume
controls, including gain, boost, attenuation and inversion are also available.
4.1.3 Line & Headphone Outputs
The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and
line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale out-
put swing centered around ground. This eliminates th e need for large DC- Blocking capacitors and allows
the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for
the headphone amplifie r are available.
4.1.4 Signal Processing Engine
A signal processing engine is available to process serial input D/A data before output to the DAC. The
D/A data has independen t volume co ntrols and mixing functions such as mono mixes a nd left/rig ht chan-
nel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic
level control provides limiting capabilities at programmable attack and release rates, maximum thresholds
and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz sample rate.
4.1.5 Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales
and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume
may be controlled independently.
4.1.6 Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface . In Hard wa re Mod e , a limited feature set may be controlled via stand-alone control pins.
4.1.7 Power Management
Two Software Mode control registers provide independent power-down control of the ADC, DAC, PGA,
MIC pre-amp and MIC bias, allowing operation in select applications with minimal power consumption.
DS679F1 27
CS42L51
4.2 Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Pow-
er-Up Sequence” on page 41) and may be controlled via stand-alone control pins. Table 2 shows a list of
functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function Default Configuration Stand-Alone Control Note
Power Control CODEC
PGAx
ADCx
DACx
MIC Bias
MICx Pre-amplifier
Powered Up
Powered Up
Powered Up
Powered Up
Powered Down
Powered Down
--
Auto-Detect Enabled - -
Speed Mode Serial Port Slave
Serial Port Master Auto-Detect Speed Mode
Single-Speed Mode --
MCLK Divide (Selectable) “MCLKDIV2” pin 2 see Section
4.5 on page 38
Serial Port Master / Slave Selection (Selectable) “M/S” pin 29 see Section
4.5 on page 38
Interface Control ADC
DAC (Selectable) “I²S/LJ” pin 3 see Section
4.6 on page 40
ADC Volume & Gain Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
--
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze Enabled
Continuous DC Subtraction --
Line/MIC Input Select AIN1A to PGAA
AIN1B to PGAB --
DAC Volume & Ga in HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
G = 0.6047
0 dB
Disabled
Enabled
Disabled
--
DAC De-Emphasis (Selectable) “DEM” pin 4 see Section
on page 34
Signal Processing Engine (SPE) Mix
Beep
Tone Control
Peak Detect and Limiter
Disabled
Disabled
Disabled
Disabled
--
Data Selection Data Input (PCM) to DAC - -
Channel Mix ADC
DAC ADCA = L; ADCB = R
PCMA = L; PCMB = R --
Charge Pump Frequency (64xFs)/7 - -
Table 2. Hardware Mode Feature Summary
28 DS679F1
CS42L51
4.3 Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-
nals, allowing various gain and signal adjustments for each channel.
4.3.1 Digital Code, Offset & DC Measurement
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle betw een ‘1’ and ‘0’, possibly introduc ing noise into the system as the bit swit ches back and fo rth.
To prevent th is phe nom ena , a constan t DC offse t is a dd ed to th e ser ial d ata b ringing th e lo w-level sig nal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to “Analog Input Characteristics (Commercial - CNZ)” on page 13
and/or “Analog Input Ch aracteristics (Automotive - DNZ)” on page 14 for the specified offset level).
The CODEC may be used to measure DC voltages by disabling the high-pass filter for the designated
channel. DC levels are measured relative to VQ and will be decoded as positive two’s complement binary
numbers above VQ an d negative two’s complement binary numbers below VQ.
Software
Controls: “Status (Address 20h) (Read Only)” on page 73, “ADC Control (Address 06h)” on page 54.
Multibit
Oversampling
ADC AIN3A/ MICIN1
MICA_BOOST
Attenuator
ALC
PGAA_VOL[5:0]
ADC_SNGVOL
0/-96dB
1dB steps
ADCA_ATT[7:0]
ADCA_HPF ENABLE
ADCA_HPF FREEZE
PDN_ADCA
ADCA_MUTE
SOFTA
ALC_ENA
ALCB_SRDIS
ALCB_ZCDIS
PDN_MICA
MICBIAS
PDN_MICBIAS
MICBIAS_LVL[1:0]
PCM Serial Interface
MICBIAS_SEL
TO SIGNAL PROCE S SING
ENGINE (SPE)
INV_ADCA
ALC_ARATE[5:0]
ALC_RRATE[5:0]
MAX[2:0]
MIN[2:0]
ALC_ENB
ALCA_SRDIS
ALCA_ZCDIS
MUX
AIN1A
AIN2A
PGA
+16/
32 dB
AINA_MUX[1:0]
PDN_PGAA
+12/-3dB
0.5dB steps
SOFTA
ZCROSSA
Multibit
Oversampling
ADC AIN3B/ MICIN 2 /
MICBIAS
MICB_BOOST
PGAB_VOL[5:0]
ADC_SNGVOL
0/-96dB
1dB steps
ADCB_ATT[7:0]
ADCB_HPF ENABLE
ADCB_HPF FREEZE
PDN_ADCB
ADCB_MUTE
SOFTB
PDN_MICB
INV_ADCB
MUX
AIN1B
AIN2B/MICBIAS
PGA
+16/
32 dB
AINB_MUX[1:0]
PDN_PGAB
+12/-3dB
0.5dB steps
SOFTB
ZCROSSB
Noise Gate NG_ALL
NG_EN
THRESH[3:0]
NGDELAY[1:0]
Attenuator
Σ
MUX
MUX
MICMIX
MUX
MUX
FROM SIGNAL
PROCESSING ENGINE
(SPE)
DIGMIX
+20dB
Digital
Boost
ADCA_DBOOST
+20dB
Digital
Boost
ADCB_DBOOST
Figure 8. Analog Input Architecture
DS679F1 29
CS42L51
4.3.2 High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset fr om th e outp ut of the de cima tion
filter. If the high-pass filter is “frozen” during normal operation, th e current value o f the DC offset for the
corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion
result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CODECwith the high-pass filter enabled and the DC offset not “frozen” until the filter
settles. See the Digital Filter Characteristics for filter settling time.
2. Freezing the DC offset.
The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.
If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using
the ADCx_HPFEN bit.
4.3.3 Digital Routing
The digital output of the ADC may be internall y routed to the signal processing e ngine (SPE) fo r playback
of analog input signals. Volume to the DAC may be controlled using the ADCMIX[6:0] bits. The serial input
data may also be routed to the ADC serial interface using the DIGMIX bit. This is useful for recording a
digital mix along with the analog input.
4.3.4 Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides com-
mon mode rejection of noise in digitally intense PCB’s where the microphone signal traverses long traces,
or across long microphone cables as illustrated in Figure 9.
Since the mixer provides a differential combination of the two signals, the poten tial input mix may exceed
the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically
attenuated 6 dB. Gain may be a pplied using either the analog PGA or MIC Pre-amp or the digital ADCMIX
volume control to re-adjust a small signal to desired levels.
The analog inputs may also be used as a differential input pair as illustrated in Figure 10. The two chan-
nels are differentially combined when the MICMIX bit is enabled.
4.3.4.1 External Passive Components
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capaci-
tors with valu es consiste nt with the d esired hig h-pass filter design. The MICINx input resistance of 50 kΩ
may be combined with an external capacitor of 1 µF to achieve the cutoff frequency defined by the equa-
tion,
An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with
the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
Software
Controls: “ADC Control (Address 06h)” on page 54.
Software
Controls: “ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 61, “Inter-
face Control (Address 04h)” on page 52.
30 DS679F1
CS42L51
The MICBIAS series resistor must be selected based on the requirements of the particular microphone
used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.
Software
Controls: “Interface Control (Address 04h)” on page 52, “MIC Contro l (Address 05h)” on page 53.
fc 1
2π50 k Ω()1 µF()
----------------------------------------------- 3.18 H z==
MICIN1
MICIN2
Σ
+
+
MICBIAS
18
17
20
//
//
Figure 9. MIC Input Mix w/Common Mode Rejection
Full-Scale Differential Input Level (MICMIX=1)
= (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS
AINxA
AINxB
2.15 V
1.25 V
0.35 V
2.5 V
2.15 V
1.25 V
0.35 V
VA
Figure 10. Differential Input
DS679F1 31
CS42L51
4.3.5 Analog Inp ut Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input
source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or by-
passed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select
from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC pre-
amp, however, the PGA must be powered up.
Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_ SEL bit
routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the
two input channels.
The ADC, PGA and MIC pre-amplifier each has an asso ciated input resistance. When selectin g between
these paths, the input resistance to the CODEC will change accordingly. Refer to the input resistance
characteristics in the Characteristic and Specification Tables for the input resistance of each path.
4.3.6 MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,
allowing it to be used fo r micr ophon e level sig nals with out the need for an y ex te rnal gain. The PGA mu st
be powered up when using the MIC pre-amp.
The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software
Controls: “Power Control 1 (Address 02h)” on page 49, “MIC Contro l (Address 05h)” on page 53 “ADCx
Input Select, Invert & Mute (Address 07h)” on page 56.
Software
Controls:
“Power Control 1 (Address 02h)” on page 49, “ADCx Input Select, Invert & Mute (Address 07h)” on
page 56, “ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on
page 59, “MIC Control (Address 05h)” on page 53.
32 DS679F1
CS42L51
4.3.7 Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases
the digital attenuation levels at a programmable attack rate and maintains the resulting level below the
maximum threshold.
When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first
and the PGA gain is then increased at a programmable release rate and maintains the resulting level
above the minimum threshold.
Attack and release rates a re affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set
in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains
the output signal between the MIN and MAX thr esholds . As the input signal leve l changes, the level-con-
trolled output may not always be the same but will always fall within the thresholds.
Software
Controls:
“ALC Enable & Attack Rate (Address 1Ch)” on page 70, “ALC Release Rate (Address 1Dh)” on
page 71, “ALC Threshold (Address 1Eh)” on page 71, “ALCX & PGAX Control: ALCA, PGAA
(Address 0Ah) & ALCB, PGAB (Address 0Bh)” on page 59.
Output
(after ALC)
Input
RRATE[5:0]
PGA Gain and/or
Attenuator
ALC
MAX[2:0]
ARATE[5:0]
below full scale
MIN[2:0]
below full scale
MIN[2:0]
below full scale
MAX[2:0]
below full scale
ADCx_ATT[7:0] and
PGAx_VOL[4:0] volume
controls should NOT be
adjusted manually when
ALCx is enabled.
Figure 11. ALC
DS679F1 33
CS42L51
4.3.8 Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from ap plying gain to noise. A programmable de lay may be used to set the minimum time b efore
the noise gate attacks the signal.
Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-am-
plifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the max-
imum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Ramp-down time to the maximum setting is affected by the SOFTx bit.
Recommended setting s: For best results, enable soft ramp for the digital attenuator. Wh en the analog in-
puts are configured for differential signals (see “Differential Inputs” on page 29), enable the NG_ALL bit
to trigger the noise gate only when both inputs fall below the threshold.
Software
Controls: “Noise Gate Configuration & Misc. (Address 1Fh)” on page 72 , “ADC Control (Address 06h)” on
page 54.
-96 -40
THRESH[2:0]
Maximum Attenuation *
-52 dB
Output
(dB)
Input (dB)
NGEN=1
NGEN=0
-80 dB
-64 dB
Figure 12. Noise Gate Attenuation
34 DS679F1
CS42L51
4.4 Analog Outputs
AOUTA and AOUTB are the ground -centered line or headpho ne outputs. Various signal processing options
are available, including digi tal mixes with the ADC si gnal and an internal Beep Generator. Th e desired path
to the DAC must be selected using the DATA_SEL[1:0] bits.
4.4.1 De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 14. The de-emphasis feature is included to accommodate audio recordings
that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. De-emphasis is only avail-
able in Single-Speed Mode.
Software
Controls: “DAC Control (Address 09h)” on page 58.
Software
Controls: “DAC Control (Address 09h)” on page 58.
Hardware
Control:
Pin Setting Selection
“DEM” pin 4. LO No De-Emphasis
HI De-Emphasis Applied
Charge
Pump
Left/Right
HP Out
Switched
Capac i to r DAC
and Filter
Headphone
Amp - GND
Centered
PDN_DACA
PDN_DACB
DATA_SEL[1:0]
00
CHRG_FREQ[3:0]
01
HP_GAIN[2:0]
Beep
Generator
Bass/
Treble/
Control
ΣVOL
Peak
Detect
Limiter
Chnl Vol.
Settings
Demph VOL
VOL
+12dB/-102dB
0.5dB steps
OUTA_VOL[7:0]
OUTB_VOL[7:0]
+12dB/-51.5dB
0.5dB steps
PCMMIXA_VOL[6:0]
PCMMIXB_VOL[6:0]
0dB/-50dB
2.0dB ste p s
BPVOL[4:0]
MUTE_PCMMIXA
MUTE_PCMMIXB
DEEMPH
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB ste p s
BASS_CF[1:0]
TREB_CF[1:0]
TC_EN
SIGNAL PROCESSING ENGINE (SPE)
DAC_SZC[1:0]
DACA_MUTE
DACB_MUTE
INV_DACA
INV_DACB
DAC_SNGVOL
AMUTE
ARATE[7:0]
RRATE[7:0]
MAX[2:0]
MIN[2:0]
LIM_SRDIS
LIM_ZCDIS
LIMIT_EN
PCMA[1:0]
PCMB[1:0]
PCM Serial Interface
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
REPEAT
BEEP
Channel
Swap
Figure 13. Output Architecture
DS679F1 35
CS42L51
4.4.2 Volume Controls
Three digital volume control functions are implemented, offering independent control over the ADC and
PCM signal paths into the mixer as well as a combined control over the mixed signals. All volume controls
are programmable to ramp in increments of 0.125 dB at a rate controlled by the DAC soft ramp/zero cross
settings.
All signal paths may also be independently muted via mute control bits. When enabled, each bit attenu-
ates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation
level set in the respective volume control register. The attenuation is ramped up and down at the rate
specified by the DAC_SZC[1:0] bits.
4.4.3 Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for either the PCM or ADC
signals. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be
used to implement a left/right channel swap.
4.4.4 Beep Generato r
The Beep Generator gen erates audio frequencies across approximately two octave major scales. It offe rs
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are availa ble .
Note: The Be ep is gen erated b efor e the limiter an d may affe ct desire d limitin g p erforma nce. If the limiter
function is used, it may be require d to set the Beep volume sufficiently below the threshold to prevent th e
peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep vol-
ume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits.
Software
Controls:
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 61, “PCMX
Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)” on page 62, “AOUTx Vol-
ume Control: AOUTA (Address 16h) & AOUTB (Address 17h)” on page 66, “DAC Output Control
(Address 08h)” on page 57.
Software
Controls: “PCM Channel Mixer (Address 18h)” on page 67.
Software
Controls: “Beep Frequency & Timing Con figuration (Address 12h)” on page 62, “Beep Off Time & Volume
(Address 13h)” on page 63, “Beep Configuration & Tone Con figuration (Address 14h)” on page 64
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 14. De-Emphasis Curve
36 DS679F1
CS42L51
4.4.5 Tone Control
Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequen-
cies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings.
4.4.6 Limiter
When enabled, th e limiter monitors the digital inpu t signal before the DAC modulator, detects when le vels
exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate be-
low the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT
volume returns to its original level set in the Volume Control register at a programmable release rate. At-
tack and release rates ar e affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best limiting performance may be realized with the fastest attack and slowest
release settin g with soft ramp enab led in the control re gisters. The “c ushion” bits allow th e user to set a
threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the lim-
iter attacks and releases.
Note:
1. When the Limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted
manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits.
2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the dig ital input
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
Software
Controls: “Tone Control (Address 15h)” on page 65 .
Software
Controls: “Limiter Release Rate Register (Address 1Ah)” on page 69, “Limiter Attack Rate Register (Address
1Bh)” on page 70, “DAC Control (Address 09h)” on page 58
FREQ[3:0]
...
BPVOL[4:0]
ONTIME[3:0] OFFTIME[2:0]
REPEAT = '0'
BEEP = '1'
REPEAT = '1'
BEEP = '0'
REPEAT = '1'
BEEP = '1'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
REPEAT is cleared.
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains
on until REPEAT is cleared.
Figure 15. Beep Configuration Options
DS679F1 37
CS42L51
4.4.7 Lin e-Level Outputs and Filtering
The CODEC contains on-chip buffer amplifiers capable of producing line level s ingle-ended outputs on
AOUTA and AOUTB. These amp lifiers are groun d center ed and do not have any DC o ffset. A load stabi-
lizer circuit, shown in the “Typical Connection Diagram (Software Mode)” on page 10 and the “Typical
Connection Diagram (Hardware Mode)” on page 11, is required on the analog outputs. This allows the
DAC amplifiers to drive line or headphone outputs.
Also shown in the T ypical Connection diagrams is th e recommended passive output filter to suppor t high-
er impedances such as those found on the inputs to operational amplifiers. “Rext”, shown in the typical
connection diag ra m s, is the input imp e da nc e of the re ce ivin g de vice.
The invert and digital gain controls may be used to provide phase an d/or amplitude compensation for an
external filter.
The delta-sigma conve rsion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filter s. The remainin g out-of-band noise can be attenu ated using
an off-chip low pass filter.
Software
Controls: “DAC Output Control (Address 08h)” on page 57, “AOUTx Volume Control: AOUTA (Address 16h)
& AOUTB (Address 17h)” on page 66.
MAX[2:0]
Output
(after Limiter)
Input
RRATE[5:0]ARATE[5:0]
Volume
Limiter
CUSH[2:0]
ATTACK/RELEASE SOUND
CUSHION
MAX[2:0]
AOUTx_VOL[7:0] volume
control should NOT be
adjusted manually when
Limiter is enabled.
Figure 16. Peak Detect & Limiter
38 DS679F1
CS42L51
4.4.8 On-Chip Charge Pump
An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual
rail supplies allowing a full-scale output swing centere d around groun d and eliminates the need for large ,
DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency
(bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage
drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply,
VSS_HP, and may result in clipping.
The FLYN and FLYP pins connect to internal switch es that charges and disch arges the external capacitor
attached, at a default switching frequency. This frequency may be adjusted in the control port registers.
Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor con-
nected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple in-
duced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the
typical connection diagrams in Figure 1 on page 10 or Figure 2 on page 11 for the recommended capacitor
values for the charge pump circuitry.
4.5 Serial Port Clocking
The CODEC serial audio inte rface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multip le of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equa l to Fs, the frequency at which a udio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone cont rol
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.
Software
Controls: “Charge Pump Frequency (Address 21h)” on page 74.
Software
Control: “MIC Power Control & Speed Control (Address 03h)” on page 50, “DAC Control
(Address 09h)” on page 58.
Hardware
Control:
Pin Setting Selection
“SDOUT, M/S” pin 29 47 kΩ Pull-down Slave
47 kΩ Pull-up Master
“MCLKDIV2” pi n 2 LO No Divide
HI MCLK is divided by 2 prior
to all internal circuitry.
DS679F1 39
CS42L51
4.5.1 Slave
LRCK and SCLK are inputs in Slave Mode. Th e spee d of the CODEC is automatica lly determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.5.2 Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the CODEC operates in single-speed only. In Softwa re Mode, the CODEC operates
in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect QSM HSM SSM DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072 256, 384, 512, 768,
1024, 1536 128, 192, 256, 384,
512, 768 128, 192, 256, 384
Enabled 1024, 1536, 2048*,
3072* 512, 768, 1024*, 1536* 2 56, 384, 512*, 768* 128, 192, 25 6*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1 0
1
MCLK
MCLKDIV2
÷ 128 00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2 00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 17. Master Mode Timing
40 DS679F1
CS42L51
4.5.3 High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-
out the need for external buffers. The 3ST_SP bit places the in ternal buffers for these I/O in a hig h-imped-
ance state, allowing another device to transmit serial po rt data without bus contention.
4.5.4 Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
4.6 Digital Interface Formats
The serial port ope rates in sta ndard I²S, Left- Justified or Right-Justified (DAC only) digital interface formats
with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of
SCLK. Figures 19-21 illustrate the general structure of each format. Refer to “Switching Specifications - Se-
rial Port” on page 20 for exact timing relationship between clocks and data.
Software
Control: “Interface Control (Address 04h)” on page 52.
Hardware
Control:
Pin Setting Selection
“I²S/LJ” pin 3 LO Left-Justified Interface
HI I²S Interface
CS42L51
Transmitting Device #1 Transmitting Device #2
Receiving Device
3ST_SP
SDOUT
SCLK/LRCK
Figure 18. Tri-State Serial Port
LRCK
SCLK
MSB LSB MSB LSB
AOUTA / AINxA
Left Channel Right Channel
SDIN
AOUTB / AINxB
MSB
Figure 19. I²S Forma t
DS679F1 41
CS42L51
4.7 Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC en-
ters a Power-Do wn state up on initial powe r-up. The inter polation and decima tion filters, de lta-sigma mo du-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are po we re d down .
The device will remain in the Power-Down state until the RESET pin is brought high. The contr ol port is ac-
cessible once RESET is high and the desi red reg ister se ttings can be loaded per the inter face descriptio ns
in “Software Mode” on page 43. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to de t ermine t he MCLK/LRC K frequency ratio and normal operation begins.
4.8 Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device w ill en te r Ha rd wa re Mode .
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6. Set the PDN bit to ‘0’b.
7. Apply LRCK,SCLK and SDIN for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
LRCK
SCLK
MSB LSB MSB LSB
Left Channel Ri ght Channel
SDIN MSB
AOUTA / AINxA AOUTB / AINxB
Figure 20. Left-J ustified Format
LRCK
SCLK
MSB LSB MSB LSB
Left Channel Right Channel
SDIN
AOUTA AOUTB
Figure 21. Right-Justified Format (DAC only)
42 DS679F1
CS42L51
4.9 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby,
1. Mute the DAC’s and ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary
to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
3. Bring RESET low.
ADC Initialization DAC Initialization
Software Mode
Registers setup to
desired settings.
RESET = Low?
No Power
1. No audio signal
generated.
Off Mode (Power Applie d)
1. No audio signal generated.
2. Control Port Registers reset
to default.
Control Port
Active
Control Port Valid
Write Seq. within
10 ms?
Hardware Mode
Minimal feature
set support.
PDN bit = '1'b?
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Valid
MCLK/LRCK
Ratio?
No
Yes
No
Yes
No
Yes
Yes
No
Normal Operation
Audio signal generated per control port or stand-
alone settings.
Analog Output Freeze
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
ERROR: MCLK removed
PDN bit set to '1'b
(software mode only)
Standby Mode
1. No audio signal generated.
2. Cont rol Port Registers retain
settings.
Reset Transition
1. Pops suppressed.
Power Off Transition
1. Audible pops.
ERROR: Power removed
Valid
MCLK Applied?
No
20 ms delay
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
2048 internal
MCLK cycle delay
Digital/Analog
Output Muted
50 ms delay
Charge Pump
Powered Up
Headphone Amp
Powered Up
20
µ
s delay
Headphone Amp
Powered Down
20
µ
s delay (DAC
only)
Stand-By
Transition
1. Pops suppressed.
ERROR: MCLK/LRCK ratio change
RESET = Low
Figure 22. Initialization Flowchart
DS679F1 43
CS42L51
4.10 Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchr onous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in two modes: SPI and I²C, with the CODEC acting as a slave device. Software
Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought
high. I²C Mode is selected by connecting the AD0/CS pin through a re sistor to VL or DGND, thereby per-
manently selecting the desired AD0 bit address state.
4.10.1 SPI Control
In Software Mod e, CS is the CS42L51 chip-sel ect signal, CCLK i s the co ntrol port bit clock (input into the
CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ig-
nored.
Figure 23 shows the operation of the control port in Software Mode. To write to a register, bring CS low.
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
4.10.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sen sed while the CS42L51 is being
reset.
The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L51
after a Start condition consists of a 7 -bit chip address field an d a R/W bit (high for a read, low for a write).
The upper 6 bits of the 7-bit address fiel d are fixed at 100101. To communicate with a CS42L51, the chip
address field, which is the first byte sent to the CS42L51, should match 100101 followed by the setting of
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or wr itten. If the operat ion is a read,
4 5 6 7
CCLK
CHIP ADDRESS (WRITE) MAP BYTE DATA
1 0 0 1 0 1 0 0
CDIN INCR 6 5 4 3 2 1 0 7 6 1 0
0 1 2 3 8 9 12 16 1710 11 13 14 15
DATA +n
CS
7 6 1 0
Figure 23. Control Port Timing in SPI Mode
44 DS679F1
CS42L51
the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the CS42L51 after each input byte is read and is input to the CS42L51 from
the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 25, the write operation is aborted after the ackno wledge for the MAP byte b y sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4 5 6 7 24 25
SCL
CHIP ADDRES S ( WRITE) MAP BYTE DATA DATA +1
START
ACK STOP
ACKACKACK
1 0 0 1 0 1 AD0 0
SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
26
DATA +n
Figure 24. Control Port Timing, I²C Write
SCL
CHIP ADDRESS (W RIT E) MAP BYTE DATA DATA +1
START ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 1 AD0 0
SDA 1 0 0 1 0 1 AD0 1
CHIP AD DRESS (READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 25. Control Port Timing, I²C Read
DS679F1 45
CS42L51
4.10.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.10.3.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
46 DS679F1
CS42L51
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
AddrFunction76543210
01h ID Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
p49
default 11011001
02h Power Ctl. 1 Reserved PDN_DACB PDN_DACA dPDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
p49
default 000 00000
03h Speed Ctl. &
Power Ctl. 2 AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_
MICBIAS MCLKDIV2
p50
default 10101110
04h Interface Ctl. SDOUT->SDIN M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 ADC_I²S/LJ DIGMIX MICMIX
p52
default 00000000
05h MIC Control
& Misc. ADC_SNGVOL ADCB_
DBOOST ADCA_
DBOOST MICBIAS_
SEL MICBIAS_
LVL1 MICBIAS_
LVL0 MICB_
BOOST MICA_
BOOST
p53
default 00000000
06h ADC Control ADCB_HPF
EN ADCB_HP
FRZ ADCA_HPF
EN ADCA_HP
FRZ SOFTB ZCROSSB SOFTA ZCROSSA
p54
default 10100000
07h ADC Input
Select
, Invert, Mute
AINB_MUX1 AINB_MUX
0AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_
MUTE ADCA_
MUTE
p56
default 00000000
08h DAC Output
Control HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_SNG
VOL INV_PCMB INV_PCMA DACB_
MUTE DACA_
MUTE
p57
default 01100000
09h DAC Control DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0
p58
default 00000110
0Ah ALCA SZC &
PGAA Vol-
ume
ALCA_SR
DIS ALCA_ZC
DIS Reserved PGAA
VOL4 PGAA
VOL3 PGAA
VOL2 PGAA
VOL1 PGAA
VOL0
p59
default 00000000
0Bh ALCB SZC &
PGAB Vol-
ume
ALCB_SR
DIS ALCB_ZC
DIS Reserved PGAB
VOL4 PGAB
VOL3 PGAB
VOL2 PGAB
VOL1 PGAB
VOL0
p59
default 00000000
0Ch ADCA Atten-
uator ADCA_
ATT7 ADCA_
ATT6 ADCA_
ATT5 ADCA_
ATT4 ADCA_
ATT3 ADCA_
ATT2 ADCA_
ATT1 ADCA_
ATT0
p60
default 00000000
0Dh ADCB Atten-
uator ADCB_
ATT7 ADCB_
ATT6 ADCB_
ATT5 ADCB_
ATT4 ADCB_
ATT3 ADCB_
ATT2 ADCB_
ATT1 ADCB_
ATT0
DS679F1 47
CS42L51
p60
default 00000000
0Eh Vol. Control
ADCMIXA MUTE_ADC
MIXA ADCMIXA
VOL6 ADCMIXA
VOL5 ADCMIXA
VOL4 ADCMIXA
VOL3 ADCMIXA
VOL2 ADCMIXA
VOL1 ADCMIXA
VOL0
p61
default 10000000
0Fh Vol. Control
ADCMIXB MUTE_ADC
MIXB ADCMIXB
VOL6 ADCMIXB
VOL5 ADCMIXB
VOL4 ADCMIXB
VOL3 ADCMIXB
VOL2 ADCMIXB
VOL1 ADCMIXB
VOL0
p61
default 10000000
10h Vol. Control
PCMMIXA MUTE_PCM
MIXA PCMMIXA
VOL6 PCMMIXA
VOL5 PCMMIXA
VOL4 PCMMIXA
VOL3 PCMMIXA
VOL2 PCMMIXA
VOL1 PCMMIXA
VOL0
p62
default 10000000
11h Vol. Control
PCMMIXB MUTE_PCM
MIXB PCMMIXB
VOL6 PCMMIXB
VOL5 PCMMIXB
VOL4 PCMMIXB
VOL3 PCMMIXB
VOL2 PCMMIXB
VOL1 PCMMIXB
VOL0
p62
default 10000000
12h BEEP Freq. &
OnTime FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
p62
default 00000000
13h BEEP Off
Time & Vol. OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
p63
default 00000000
14h BEEP Con-
trol & Tone
Config
REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
p64
default 00000000
15h Tone Control TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
p65
default 10001000
16h Vol. Control
AOUTA AOUTA_
VOL7 AOUTA_
VOL6 AOUTA_
VOL5 AOUTA_
VOL4 AOUTA_
VOL3 AOUTA_
VOL2 AOUTA_
VOL1 AOUTA_
VOL0
p66
default 00000000
17h Vol. Control
AOUTB AOUTB_
VOL7 AOUTB_
VOL6 AOUTB_
VOL5 AOUTB_
VOL4 AOUTB_
VOL3 AOUTB_
VOL2 AOUTB_
VOL1 AOUTB_
VOL0
p66
default 00000000
18h PCM & ADC
Channel
Mixer
PCMA1 PCMA0 PCMB1 PCMB0 ADCA1 ADCA0 ADCB1 ADCB0
p67
default 00000000
19h Limiter
Threshold &
SZC Disable
MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS
p67
default 00000000
AddrFunction76543210
48 DS679F1
CS42L51
1Ah Limiter Con-
fig & Release
Rate
LIMIT_EN LIMIT_ALL LIM_RRATE
5LIM_RRATE
4LIM_RRATE
3LIM_RRATE
2LIM_RRATE
1LIM_RRATE
0
p69
default 01111111
1Bh Limiter Attack
Rate Reserved Reserved LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0
p70
default 00000000
1Ch ALC Enable
& Attack Rate ALC_ENB ALC_ENA ALC_ARATE
5AALC_RATE
4ALC_ARATE
3ALC_ARATE
2ALC_ARATE
1ALC_ARATE
0
p70
default 00000000
1Dh ALC Release
Rate Reserved Reserved ALC_RRATE
5ALC_RRATE
4ALC_RRATE
3ALC_RRATE
2ALC_RRATE
1ALC_RRATE
0
p71
default 00111111
1Eh ALC Thresh-
old MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved
p71
default 00000000
1Fh Noise Gate
Config NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
p72
default 00000000
20h Status Reserved SP_CLKER
RSPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL
p73
default 00000000
21h Charge Pump
Frequency CHRG_
FREQ3 CHRG_
FREQ2 CHRG_
FREQ1 CHRG_
FREQ0 Reserved Reserved Reserved Reserved
p74
default 01010000
AddrFunction76543210
DS679F1 49
CS42L51
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Reg ister which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
Note: Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using
the DATA_SEL[1:0] bits, as described in section “DAC Data Selection (DATA_SEL[1:0])” on page 58.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS42L51. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS42L51 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2 Power Control 1 (Address 02h)
Notes: 1. To activate the power-down sequ ence for individual channels ( A or B,) both channels must first be pow-
ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-
abling the power-down bit on an individual channel basis after the CODEC has fully powered up will
mute the selected cha nnel with o ut ac hie vin g an y po we r sav ing s.
Recommen ded channel power-down sequ ence: 1.) Enable the PDN bit, 2.) enable po wer-down for the se-
lect channels, 3.) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0
0 - Disable
1 - Enable
Function:
DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above.
76543210
Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
76543210
Reserved PDN_DACB PDN_DACA PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
50 DS679F1
CS42L51
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control
1 (Address 02h) on page 49 above.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 56 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on pa ge
49.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire CODEC will enter a low-power state when this function is enabled. The contents of the control
port registers are retained in this mode.
6.3 MIC Power Control & Speed Control (Address 03h)
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operat ing as a slav e.
When AUTO is enabled, the MCLK/LRCK r atio must be implemented according to Table 3 on page 39. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
76543210
AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2
DS679F1 51
CS42L51
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (S SM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the CODEC in Master or Slave Mode. QSM is optimized for 8 kHz sam-
ple rate and HSM is o ptimized for 16 kHz sample rate . These bits are ignored when the AUTO b it is enabled
(see Auto-Detect Speed Mode (AUTO) above).
Tri-State Serial Port Interface (3ST_SP)
Default: 0
0 - Disable
1 - Enable
Function:
When enabled and the device is configured as a master, all serial port outputs are place in a high impedance
state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a high-impedance state.
The other signals will remain as inputs.
Power Down MIC X (PDN_MICX)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone pre-amplifier for channel x will be in a power-down state.
Power Down MIC BIAS (PDN_MICBIAS)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone bias circuit will be in a power-down state.
MCLK Divide By 2 (MCLKDIV2)
Default: 0
0 - Disabled
1 - Divide by 2
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
52 DS679F1
CS42L51
6.4 Interface Control (Address 04h)
SDOUT to SDIN Loopback (SDOUT->SDIN)
Default: 0
0 - Disabled; SDOUT internally disconnected from SDIN
1 - Enabled; SDOUT internally connected to SDIN
Function:
Internally loops the signal on the SDOUT pin to SDIN.
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and se rial data is defined by the Digital Interface Format and the options are
detailed in the section “Digital Interface Formats” on page 40.
76543210
SDOUT->SDIN M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 ADC_I²S/LJ DIGMIX MICMIX
DAC_DIF[2:0] Description Figure
000 Left-Justified, up to 24-bit data 20 on page 41
001 I²S, up to 24-bit data 19 on page 40
010 Right-Justified, 24-bit data 21 on page 41
011 Right-Justified, 20-bit data 21 on page 41
100 Right-Justified, 18-bit data 21 on page 41
101 Right-Justified, 16-bit data 21 on page 41
110 Reserved -
100 Reserved -
DS679F1 53
CS42L51
ADC I²S or Left-Justified (ADC_I²S/ L J)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the da ta on SDOUT. The required re lation-
ship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are de ta iled in this se ction .
Digital Mix (DIGMIX)
Default: 0
Function:
Selects betw een the ADC or a digital mi x of the ADC and DAC into the ser ial por t to the SD OUT pin . This
mix function is affected by the data select bits DATA_SEL[1:0].
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
6.5 MIC Control (Address 05h)
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are in dependently controlled by thei r respective control register s when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable contro l for chann el B is controlled by the ALC A enab le when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
DIGMIX DATA_SEL[1:0] Mix Selected
0 xx No Mix: ADC to ADC serial port, SDOUT data.
1
00 No Mix: SDIN data to ADC serial port, SDOUT data.
01 Mix: ADC + SDIN data to ADC serial port, SDOUT data.
10 No Mix: ADC to ADC serial port, SDOUT data.
11 Reserved
76543210
ADC_SNGVOL ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 MICB_BOOST MICA_BOOST
54 DS679F1
CS42L51
ADCx 20 dB Digital Boost (ADCx_DBOOST)
Default: 0
0 - Disabled
1 - Enabled
Function:
Applies a 20 dB digital gain to the input signa l on ADC channel x, regardless of the input path.
MIC Bias Select (MICBIAS_SEL)
Default: 0
0 - MICBIAS on AIN3B/MICIN2 pin
1 - MICBIAS on AIN2B pin
Function:
Determines the output pin for the inte rn ally gener ated MICBIAS signal. If set to ‘0’b, the MICBIAS is output
on the AIN3B/MICIN2 pin. If set to ‘1’b, the MICBIAS is output on the AIN2B pin.
MIC Bias Level (MICBIAS_LVL[1:0])
Default: 00
00 - 0.8 x VA
01 - 0.7 x VA
10 - 0.6 x VA
11 - 0.5 x VA
Function:
Determines the output voltage level of the MICBIAS output.
MIC X Preamplifier Boost (MICX_BOOST)
Default: 0
0 - +16 d B Ga in
1 - +32 d B Ga in
Function:
Determines the amount of gain applied to the microphone preamplifier for channel x.
6.6 ADC Control (Address 06h)
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1
0 - High-pass filter is disabled
1 - High-pass filter is enabled
Function:
When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter
will be disabled. For DC measurements, this bit must be cleared to ‘0’. See “ADC Digital Filter Characteris-
tics” on page 15.
76543210
ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ SOFTB ZCROSSB SOFTA ZCROSSA
DS679F1 55
CS42L51
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0
0 - Continuous DC Subtraction
1 - Frozen DC Subtraction
Function:
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current va lue of the DC
offset is frozen, and this DC offs et will continue to be subtracted from the co nversion result. For DC mea-
surements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 15.
Soft Ramp CHX Control (SOFTX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital atten-
uation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.
PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB
steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible
artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximate-
ly 10.7 ms at 48 kHz sample rate) if the signal does not encoun ter a zero crossing. The zero cross fun ction
is independently monitored and implemented for each channel.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps
and be implemented on a signal zero crossing.
The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
SOFTx ZCROSSx Analog PGA Volume
(PGAx_VOL[4:0]) Digital Attenuator (ADCx_ATT[7:0])
00
Volume cha nges immediately. Volume cha nges immediately.
01
Volume cha nges at next zero cross time . Volume changes immediately.
10
Volume cha nges in 0.5 dB steps. Change volume in 0.125 dB steps.
11
Volume cha nges in 0.5 dB steps at every
signal zero-cross. Change volume in 0.125 dB steps.
56 DS679F1
CS42L51
6.7 ADCx Input Select, Invert & Mute (Address 07h)
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See Figure 26.
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
76543210
AINB_MUX1 AINB_MUX0 AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_MUTE ADCA_MUTE
PDN_PGAx AINx_MUX[1:0] Selected Path to ADC
0 00 AIN1x-->PGAx
0 01 AIN2x-->PGAx
0 10 AIN3x/MICINx-->PGAx
0 11 AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx
100AIN1x
101AIN2x
1 10 AIN3x/MICINx
1 11 Reserved
MUX
AIN1x
AIN2x
AIN3x / MICINx
PGA
+16/
32 dB
MUX
AINx_MUX[1:0]
PDN_PGAx
AIN1x
AIN2x
AIN3x
Decoder
ADC
Figure 26. AIN & PGA Selection
DS679F1 57
CS42L51
6.8 DAC Output Control (Address 08h)
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
Function:
These bits select the gain multiplier for the headphone/lin e outputs. See “Line Ou tput Volta ge Char acter is-
tics” on page 18 and “Headphone Output Power Characteristics” on pag e 19.
DAC Single Volume Control (DAC_SNGVOL)
Default: 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control reg-
isters when this function is disabled. When enabled, the volume on all channels is determined by the AOU-
TA Volume Control register and the AOUTB Volume Control register is ignored.
PCMX Invert Signal Polarity (INV_PCMX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the PCM x channel.
DACX Channel Mute (DACX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and
Zero Cross bits (DACx_SZC[1:0]).
76543210
HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_
SNGVOL INV_PCMB INV_PCMA DACB_MUTE DACA_MUTE
HP_GAIN[2:0] Gain Setting
000 0.3959
001 0.4571
010 0.5111
011 0.6047
100 0.7099
101 0.8399
110 1.0000
111 1.1430
58 DS679F1
CS42L51
6.9 DAC Control (Address 09h)
DAC Data Selection (DATA_SEL[1:0])
Default: 00
00 - PCM Serial Port to DAC
01 - Signal Processing Engine to DAC
10 - ADC Serial Port to DAC
11 - Reserved
Function:
Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal
Processing Engine to DAC” option is selected using these bits.
Freeze Controls (FREEZE)
Default: 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to all control port reg-
isters without the chang es taking ef fect until the FREEZE is disabled. To have multiple ch anges in the con-
trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then
disable the FREEZE bit.
DAC De-Emphasis Control (DEEMPH)
Default: 0
0 - No De-Emphasis
1 - De-Emphasis Enabled
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control.
Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample
rate of 44.1 kHz.
Analog Output Auto MUTE (AMUTE)
Default: 0
0 - Auto Mute Disabled
1 - Auto Mute Enabled
Function:
Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input
channel.
76543210
DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0
DS679F1 59
CS42L51
DAC Soft Ramp and Zero Cross Control (DAC_S ZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and imple-
mented for each channel. Note: The LIM_SRDIS bit is ignored.
Soft Ramp
Soft Ramp allows level changes, eith er by gain changes, attenuation change s or muting, to be implemented
by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4
left/right clock periods.
Soft Ramp on Zero Crossing
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur
after a timeout period between 51 2 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if
the signal does not encou nter a zero cro ssing. T he zero cross function is indepe nde ntly moni tore d an d im-
plemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
ALCX Soft Ramp Disable (ALCX_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be
dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.
76543210
ALCX_SRDIS ALCX_ZCDIS Reserved PGAX_VOL4 PGAX_VOL3 PGAX_VOL2 PGAX_VOL1 PGAX_VOL0
60 DS679F1
CS42L51
ALCX Zero Cross Disable (ALCX_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not
be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step.
PGA X Gain Control (PGAX_VOL[4:0])
Default: 00000
Function:
The PGAx Gain Control register allows independent sett ing of the signal levels in 0.5 dB increments as dic-
tated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are
decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft &
Zero Cross bits (ALCX_SZC). Levels are decoded as descr ibed in the table above.
Note: When the ALC is enabled, th e PGA is automa tically contro lled and shou ld not be adj usted manu -
ally.
6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
ADCX Attenuation Control (ADCX_ATT[7:0])
Default: 00h
Binary Code Volume Setting
11000 +12 dB
··· ···
01010 +5 dB
··· ···
00000 0 dB
11111 -0.5 dB
11110 -1 dB
··· ···
11001 -3 dB
11010 -3 dB
76543210
ADCx_ATT7 ADCx_ATT6 ADCx_ATT5 ADCx_ATT4 ADCx_ATT3 ADCx_ATT2 ADCx_ATT1 ADCx_ATT0
Binary Code Volume Setting
0111 1111 0 dB
··· ···
0000 0000 0 dB
1111 1111 -1 dB
1111 1110 -2 dB
··· ···
1010 0000 -96 dB
··· ···
1000 0000 -96 dB
DS679F1 61
CS42L51
Function:
The level of ADCX can be adjuste d in 1.0 dB in cr eme nts as dictated by the ADCx Soft an d Ze ro Cro ss bits
(SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table
above.
Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
ADCX Mixer Channel Mute (MUTE_ADCMIXX)
Default: 1
0 - Disabled
1 - Enabled
Function:
The ADC chann el X input to the output mixer will mute when enabled. The muting function is affected by
the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
ADCX Mixer Volume Control (ADCMIXX_VOL[6:0])
Default = 000 0000
Function:
The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the
DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in
the table above.
76543210
MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0
Binary Code Volume Setting
001 1000 +12.0 dB
··· ···
000 0000 0 dB
111 1111 -0.5 dB
111 1110 -1.0 dB
··· ···
001 1001 -51.5 dB
62 DS679F1
CS42L51
6.13 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
PCMX Mixer Channel Mute (MUTE_PCMMIXX)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by
the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
PCMX Mixer Volume Control (PCMMIXX_VOL[6:0])
Default: 000 0000
Function:
The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the
DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described
in the table above.
6.14 Beep Frequency & Timing Configuration (Address 12h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Frequency (FREQ[3 :0])
Default: 0000
76543210
MUTE_
PCMMIXx PCMMIXx_
VOL6 PCMMIXx_
VOL5 PCMMIXx_
VOL4 PCMMIXx_
VOL3 PCMMIXx_
VOL2 PCMMIXx_
VOL1 PCMMIXx_
VOL0
Binary Code Volume Setting
001 1000 +12.0 dB
··· ···
000 0000 0 dB
111 1111 -0.5 dB
111 1110 -1.0 dB
··· ···
001 1001 -51.5 dB
76543210
FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
FREQ[3:0] Frequency
Fs = 12, 24, 48 or 96
kHz
Pitch
0000 260.87 Hz C4
0001 521.74 Hz C5
0010 585.37 Hz D5
0011 666.67 Hz E5
0100 705.88 Hz F5
DS679F1 63
CS42L51
Function:
The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale
directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 15 on
page 36 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep On Time Duration (ONTIME[3:0])
Default: 0000
Function:
The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will
scale inversely with sample rate, Fs, but is fixed at the nomina l Fs within each speed mod e. Refer to Figure
15 on page 36 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits.
6.15 Beep Off Time & Volume (Address 13h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
Beep Off Time (OFFTIME[2:0])
Default: 000
0101 774.19 Hz G5
0110 888.89 Hz A5
0111 1000.00 Hz B5
1000 1043.48 Hz C6
1001 1200.00 Hz D6
1010 1333.33 Hz E6
1011 1411.76 Hz F6
1100 1600.00 Hz G6
1101 1714.29 Hz A6
1110 2000.00 Hz B6
1111 2181.82 Hz C7
TIME[3:0] On Time
Fs = 12, 24, 48 or 96 kHz
0000 86 ms
··· ···
1111 5.2 s
76543210
OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
OFFTIME[2:0] Off Time
Fs = 12, 24, 48 or
96 kHz
000 1.23 s
001 2.58 s
010 3.90 s
011 5.20 s
100 6.60 s
101 8.05 s
FREQ[3:0] Frequency
Fs = 12, 24, 48 or 96
kHz
Pitch
64 DS679F1
CS42L51
Function:
The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration
will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to
Figure 15 on page 36 for single-, multiple- and continuous-beep configurations using the REPEAT and
BEEP bits.
Beep Volume (BPVOL[4:0])
Default: 00000
Function:
The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB.
Refer to Figure 15 on page 36 for single -, multiple- and continuous-beep co nfigurations using the REPEAT
and BEEP bits. Levels are decoded as described in the table above.
6.16 Beep Configuration & Tone Configuration (Address 14h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Repeat Beep (REPEAT)
Default: 0
0 - Disabled
1 - Enabled
Function:
This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output.
Refer to Figure 15 on page 36 for a description of each configuration option.
Beep (BEEP)
Default: 0
0 - Disabled
1 - Enabled
Function:
110 9.35 s
111 10.80 s
Binary Code Volume Setting
00110 +12.0 dB
··· ···
00000 0 dB
11111 -2 dB
11110 -4 dB
··· ···
00111 -5 0 dB
76543210
REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
OFFTIME[2:0] Off T i me
Fs = 12, 24, 48 or
96 kHz
DS679F1 65
CS42L51
This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog
output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to
remain ON for the ma ximum ONTIME duration. Refer to Figu re 15 on page 36 for a descr iption of each con-
figuration option.
Treble Corner Frequency (TREB_CF[1:0])
Default: 00
00 - 5 kHz
01 - 7 kHz
10 - 10 kHz
11 - 15 kHz
Function:
The treble corner frequency is user selectable as shown above.
Bass Corner Frequency (BASS_CF[1:0])
Default: 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - 250 Hz
Function:
The bass corner fre qu en cy is user-selectable as shown above.
Tone Control Enable (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass and Treble tone control features are active when this bit is enabled.
6.17 Tone Control (Address 15h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
Treble Gain Level (TREB[3:0])
Default: 1000 dB (No Treble Gain)
76543210
TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
Binary Code Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10. 5 dB
66 DS679F1
CS42L51
Function:
The level of the sh elving treble gain filte r is set by Treble Gain Level. The level can be adjusted in 1.5 dB
increments from +12.0 to -10.5 dB.
Bass Gain Level (BASS[3:0])
Default: 1000 dB (No Bass Gain)
Function:
The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB in-
crements from +10.5 to -10.5 dB.
6.18 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
AOUTX Volume Control (AOUTX_VOL[7 :0])
Default = 00h
Function:
The analog output levels can b e adjusted in 0.5 dB incr ements fr om +12 to -102 dB as dictated by the DAC
Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table
above.
Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be ad-
justed manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits.
Binary Code Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
76543210
AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
Binary Code Volume Setting
0001 1000 +12.0 dB
··· ···
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -102 dB
··· ···
0001 1001 -102 dB
DS679F1 67
CS42L51
6.19 PCM Channel Mixer (Address 18h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
Channel Mixer (PCMx[1:0] & ADCx[1:0])
Default: 00
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
6.20 Limiter Threshold SZC Disable (Address 19h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
Maximum Threshold (MAX[2 :0])
Default: 000
Function:
Sets the maximum level, below full scale, at which to limit an d attenuate the output signal at the atta ck rate.
Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an
attack.
76543210
PCMA1 PCMA0 PCMB1 PCMB0 ADCA1 ADCA0 ADCB1 ADCB0
PCMA[1:0]
and/or
ADCA[1:0]
AOUTA PCMB[1:0] and/or
ADCB[1:0] AOUTB
00 L 00 R
01 01
10 10
11 R 11 L
76543210
MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS
MAX[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
101 -12
101 -18
110 -24
111 -30
LR+
2
------------ LR+
2
------------
68 DS679F1
CS42L51
Cushion Threshold (CUSH[2:0])
Default: 000
Function:
Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0])
threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal
below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter
attacks and releases.
Limiter Soft Ramp Disable (LIM_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when
DAC_SZC[1:0] = ‘01’b or ‘11’b.)
Limiter Zero Cross Disable (LIM_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the zero-cross setting.
CUSH[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
101 -12
101 -18
110 -24
111 -30
DS679F1 69
CS42L51
6.21 Limiter Release Rate Register (Address 1Ah)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro l in this register.
Peak Detect and Limiter Enable (LIMIT_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting
is performe d by digital attenu ation. Note: When the limiter is enabled, the AOUT Volume is automatically
controlled and should not be adjusted manually. Alternative volume control may be realized using the
PCMMIXx_VOL[6:0] bits.
Peak Signal Limit All Channels (LIMIT_ALL)
Default: 1
0 - Individual Channel
1 - Both channel A & B
Function:
When set to 0, the peak signal limiter will limit the ma ximum signal amplitude to prevent clipping on the spe-
cific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both
channels in response to any single channel indicating clipping.
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the limiter releases the digital attenuation from le vels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
76543210
LIMIT_EN LIMIT_ALL RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
Binary Code Release Time
000000 Fastest Release
··· ···
111111 Slowest Release
70 DS679F1
CS42L51
6.22 Limiter Attack Rate Register (Address 1Bh)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Limiter Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the limiter attenu ates the analog output from levels above the maximum setting in the
limiter threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.23 ALC Enable & Attack Rate (Address 1Ch)
ALC Enable (ALC_ENX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables automatic level control for ADC channel x.
Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
ALC Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the
ALC threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, a nd the SOFTx
& ZCROSSx bit settings unless the disable bit for each function is enabled.
76543210
Reserved Reserved ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
Binary Code Attack Time
000000 Fastest Attack
··· ···
111111 Slowest Attack
76543210
ALC_ENB ALC_ENA ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
Binary Code Attack Time
000000 Fastest Attack
··· ···
111111 Slowest Attack
DS679F1 71
CS42L51
6.24 ALC Release Rate (Address 1Dh)
ALC Release Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting
in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting.
The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSS bit settings unless the disable bit for each function is enabled.
6.25 ALC Threshold (Address 1Eh)
Maximum Threshold (MAX[2 :0])
Default: 000
Function:
Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack
rate.
Minimum Threshold (MIN[2:0])
Default: 000
76543210
Reserved Reserved ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
Binary Code Release Time
000000 Fastest Release
··· ···
111111 Slowest Release
76543210
MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved
MAX[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
100 -12
101 -18
110 -24
111 -30
MIN[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
72 DS679F1
CS42L51
Function:
Sets the minimum level at which to disengage the ALC’s a ttenuation or amp lify the input signal at a rate set
in the release rate register until levels again reach this minimum threshold. The ALC uses this mi nimum a s
a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the
minimum setting. This provides a more natural sound as the ALC attacks and releases.
6.26 Noise Gate Configuration & Misc. (Address 1Fh)
Noise Gate Channel Gang (NG_ALL)
Default: 0
0 - Disabled
1 - Enabled
Function:
Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the thresh-
old setting for the noise gate attenuation to take effect.
Noise Gate Enable (NG_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables the noise gate. Maximum attenuation is relative to all gain settings applied.
Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])
Default: 000
011 -9
100 -12
101 -18
110 -24
111 -30
76543210
NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
THRESH[2:0] Minimum Setting
(NG_BOOST = ‘0’b) Minimum Setting
(NG_BOOST = ‘1’b)
000 -64 dB -34 dB
001 -67 dB -37 dB
010 -70 dB -40 dB
011 -73 dB -43 dB
100 -76 dB -46 dB
101 -82 dB -52 dB
110 Reserved -58 dB
111 Reserved -64 dB
MIN[2:0] Threshold
Setting
(dB)
DS679F1 73
CS42L51
Function:
Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96
dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings.
Noise Gate Delay Timing (NGDELAY[1:0])
Default: 00
00 - 50 ms
01 - 100 ms
10 - 150 ms
11 - 200 ms
Function:
Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx &
ZCROSS bit settings unless the disable bit for each function is enabled.
6.27 Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” mean s the associated er ror condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 38 for valid clock ratios.
Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Signal Processing Engine Overflow (SPEX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: 0
Function:
Indicates a digital overflow conditio n within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the
associated ADC’s.
76543210
Reserved SP_CLKERR SPEA_OVFL SPEB_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL
74 DS679F1
CS42L51
6.28 Charge Pump Frequency (Address 21h)
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
Function:
Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs,
should the switching frequency interfere with other system frequencies such as those in the AM radio b and.
Note: Distortion performance may be affected.
76543210
CHRG_FREQ
3CHRG_FREQ
2CHRG_FREQ
1CHRG_FREQ
0Reserved Reserved Reserved Reserved
N CHRG_FREQ[3:0] Frequency
0 0000
... ...
15 1111
64xFs
N2+
-----------------
DS679F1 75
CS42L51
7. ANALOG PERFORMANCE PLOTS
7.1 Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise sp ecified): Input test sign al is a 997 Hz sin e wave; measurement band-
width is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB42L51 using an Audio Precision an-
alyzer.
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 27. THD+N vs. Output Power pe r Chan nel at 1.8 V (16 Ω load)
VA_HP = VA = 1.8 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 23 mW into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 28. THD+N vs. Output Power pe r Chan nel at 2.5 V (16 Ω load)
VA_HP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 44 mW into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = -
75 dB).
76 DS679F1
CS42L51
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
d
B
r
A
060m6m 12m 18m 24m 30m 36m 42m 48m 54m
W
Figure 29. THD+N vs . Output Power per Channe l at 1.8 V (32 Ω load)
VA_HP = VA = 1.8
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 22 mW into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
d
B
r
A
060m5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m
W
Figure 30. THD+N vs. Outpu t Power per Channel at 2.5 V (32 Ω load)
VA_HP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 42 mW into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = -
75 dB).
DS679F1 77
CS42L51
7.2 Headphone Amplifier Efficiency
The architecture of the headphone amplifier is that of typical class AB amplifiers . Test conditions (unles s
otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback
w/16 Ω load. HP_GAIN = 1.1430. Be st efficiency is rea lized wh en the am plifier outp uts m aximum powe r.
Figure 31. Power Dissipation vs. Output Power into Stereo 16 Ω
VA_HP = VA = 1.8 V
Figure 32. Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail)
VA_HP = VA = 1.8 V
78 DS679F1
CS42L51
7.3 ADC_FILT+ Capacitor Effects on THD+N
The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion +
noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N
at low frequencies. Figure 33 shows the THD+N versus freq uency for the ADC analog input. Plots were tak-
en from the CDB42L51 using an Audio Precision analyzer.
-100
-
60
-96
-92
-88
-84
-80
-76
-72
-68
-64
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 33. ADC THD+N vs. Frequency w/Capacitor Effects
1 µF
Legend –
Capacitor Value on ADC_FILT+
10 µF
22 µF
DS679F1 79
CS42L51
8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
*The”MCLKDIV2” pin 4 must be set HI.
Sample Rate
LRCK (kHz) MCLK (MHz)
1024x 1536x 2048x* 3072x*
8 8.1920 12.2880 16.3840 24.5760
11.025 11.2896 16.9344 22.5792 33.8688
12 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x* 1536x*
16 8.1920 12.2880 16.3840 24.5760
22.05 11.2896 16.9344 22.5792 33.8688
24 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x* 768x*
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x* 384x*
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
80 DS679F1
CS42L51
8.2 Auto Detect Disabled
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x 1536x 2048x 3072x
8 - 6.1440 8.1920 12.2880 16.3840 24.5760
11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688
12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x 1024x 1536x
16 - 6.1440 8.1920 12.2880 16.3840 24.5760
22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688
24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x 384x
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
DS679F1 81
CS42L51
9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-resolution converter, the CS42L51 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 on page 10 shows the recommended
power arrangements, with VA and VA_HP connected to clean su pplies. VD, which powers the digital circuit-
ry, may be run from the system logic supply. Al ternatively, VD may be powered from the analog supply via
a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are re commende d. Decoupling capa citors sh ould be as clo se to the pins of the CS42L51 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS42L51 to minimiz e inductance effects. All signals, es pecially clocks, should be
kept away from the DAC_FILT+/ADC_FILT+ and VQ pins in order to avoid unwanted coupling into the mod-
ulators. The DAC_ F IL T+/ADC_FILT+ and VQ de co up lin g capa cit or s, p ar ticul ar ly the 0 .1 µF, must be posi-
tioned to minimize the electrical pa th from DAC_ FILT+/ADC_FILT+ and AGND. The CDB42L5 1 evaluatio n
board demonstrates the optimum layout and power supp ly ar ra ng em e nt s.
9.2 QFN Thermal Pad
The CS42L51 is available in a compact QFN p ackage . The unde r side of the QFN pa ckage reveals a la rge
metal pad that serves as a thermal relief to provide for maximum h eat dissip ation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS42L51 evaluation board demonstrates the optimum thermal pad and via configuration.
82 DS679F1
CS42L51
10.ADC & DAC DIGITAL FILTERS
Figure 34. ADC Passband Ripple Figure 35. ADC Stopband Rejection
Figure 36. ADC Transition Band Figure 37. ADC Transition Band Detail
Figure 38. DAC Passb an d Ri pple Figure 39. DAC Stopban d
Figure 40. DAC Transition Band Figure 41. DAC Transition Band (Detail)
DS679F1 83
CS42L51
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
bandwidth. Dynamic Range is a signal-to-noise ratio mea surement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensu res tha t the distortion co mpone nts are below the noise level and do n ot affect the m easure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-3 07 . Exp resse d in de cib els .
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 k Hz. Units in decibels.
Interchannel Isolation
A measure of crosstalk betwe en the left and right cha nnel pairs. Measu red for each ch annel at the conver t-
er's output with no signal to the inpu t under test and a full- scale signal applied to the oth er channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a fu ll-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
84 DS679F1
CS42L51
12.PACKAGE DIMENSIONS
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A----0.0394----1.001
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.1969 BSC 5.00 BSC 1
D2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
E 0.1969 BSC 5.00 BSC 1
E2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board θJA -
-52
38 -
-°C/Watt
Side View
A1
Bottom View
Top View
A
Pin #1 Corner
D
E
D2
L
be Pi n #1 Corner
E2
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
DS679F1 85
CS42L51
13.ORDERING INFORMATION
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter
Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at th e 103rd Convention of the
Audio Engineering Society, September 1997.
3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Conv erter for Digital Audio, by D.R. Welland, B.P. Del Signo-
re, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention
of the Audio Engineering Society, November 1988.
4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and
on Oversampling Delta Sigma ADC's , by Steven Harris. Paper presented at the 87th Convention of the Au-
dio Engineering Society, October 1989.
5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Conver ter, with 19-Bit Mono Applica-
tion Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society,
October 1989.
6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven
Harris. Presented at the 93rd Conve ntion of the Audio Engineering Society, October 1992.
7. Cirrus Logic, A Fifth-Order Delta-Sigma Modula tor with 110 dB Audio Dynamic Range, by I. Fujimori, K. Ha-
mashita and E.J. Swanson. Paper p resented at the 93rd Convention of the Audio Engineer ing Society, Oc-
tober 1992.
8. Philips Semiconductor, The I²C -Bus Specific ation: Version 2.1 , Ja nu ar y 20 00 .
http://www.semiconductors.philips.com
Product Description Package Pb-Free Grade Temp Range Container Order #
CS42L51 Low-Power Stereo
CODEC w/HP Amp for
Portable Apps 32L-QFN Yes Commercial -10 to +70° C Rail CS42L51-CNZ
Tape & Reel CS42L51-CNZR
Automotive -40 to +85° C Rail CS42L51-DNZ
Tape & Reel CS42L51-DNZR
CDB42L51 CS42L51 Evaluation
Board - No - - - CDB42L51
CRD42L51 CS42L51 Reference
Design - No - - - CRD42L51
86 DS679F1
CS42L51
15.REVISION HISTORY
Revision Changes
A1 Initial Release
A2
Renamed pin 14, FILT1+ , to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+.
Added 1.5 µF capa cit o r reco mme nd a ti o n to figu r e “Typical Connection Diagram (Software Mode)” on page 10.
Removed the 0.1µF capacitors from pins DAC_FILT+, ADC_FILT+ and VQ on the figures “Typical Connection
Diagram (Software Mode)” on page 10 and “Typical Connection Diagram (Hardwa re Mode)” on page 11.
Added DAC Isola tion specif ication to “Analog Input Characteristics (Commercial - CNZ)” on page 13 and “Analog
Input Characteristics (Automotive - DNZ)” on page 14.
Corrected specification table “Headphone Output Power Characteristics” on page 19.
Removed td timing specification from table in section “Switching Specifications - Serial Port” on page 20.
Added ts(SDO-SK) and th(SK-SDO) timing specification to table in section “Switching Specifications - Serial Port” on
page 20.
Adjusted timing specifications ts(SD-SK) from 0 ns to 20 ns and th from 50 ns to 20 ns in table in section “Switching
Specifications - Serial Port” on page 20.
Added MIC Bias PSRR specification to “DC Electrical Characteri stics” on page 24.
Adjusted specification table “Power Consumption” on page 25.
Removed QSM clock ratios 128, 192, 256, 384 and HSM ratios 128, 192 from Table 3 on page 39.
Modified Digital Mix description in section “Digital Mix (DIGMIX)” on page 53.
Corrected DAC Zero Cross timeout period in section “Zero Cross” on pag e 59.
Adjusted BEEP off time settings in section “Beep Off Time (OFFTIME[2:0])” on page 63.
Modified BEEP description in section “Beep (BEEP)” on page 64.
Adjusted the minimum settings for the “Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])” on
page 72.
Swapped bits PCMA_OVFL w/PCMB_OVFL and AD CA_OVFL w/ADCB_OVFL in register “Status (Address 20h)
(Read Only)” on page 73.
Corrected Charge Pump Frequency setting in section “Charge Pump Frequency (CHRG_FREQ[3:0])” on
page 74.
Added sections “Headphone THD+N versus Output Power Plots” on page 75 and “ADC_FILT+ Capacitor Effect s
on THD+N” on page 78.
DS679F1 87
CS42L51
PP1
Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 12.
Adjusted Ambient Operating Temp. specification in “Absolute Maximum Rati ng s” se cti o n on pa ge 12.
Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Input Characteris-
tics (Commercial - CNZ)” on page 13.
Added Offset Error specification to “Analog Input Characteristics (Commercial - CNZ)” on page 13 and “Analog
Input Characteristics (Automotive - DNZ)” on page 14.
Corrected Interchannel Gain Mismatch specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14.
Adjusted ADC full scale input voltage specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14.
Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 15.
Adjusted maximum “RL = 10kΩ” THD+N performance specification in “Analog Output Characteristics (Commer-
cial - CNZ)” on page 16 and “Analog Output Characteristics (Automotive - DNZ)” on page 17 .
Corrected Group Delay characteristic in table in section “Combined DAC Interp olation & on-Chip Analog FIlter
Response” on page 20.
Adjusted timing specificati ons td(MSB) from 40 ns to 52 ns and ts(SDO-SK) from 30 ns to 20 ns in table in section
“Switching Specifications - Serial Port” on page 20 .
Adjusted I²C timing specification tack from 1000 ns to 3450 ns in table in section “” on page 21.
Adjusted High-Level Input Voltage specifications VIH from 0.65VL to 0.68VL and VIL from 0.35VL to 0.32VL in
table in section “Digital Interface Specifications & Characteristics” on page 24.
Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 8 on page 28.
Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 32.
Modified step 2 of the “Recommended Power-Down Sequence” on page 42.
Corrected default values for ALC and Limit er R ele ase Rates shown in “Register Quick Reference” on page 46.
Corrected default value for the DAC_SZC bits and Added AMUTE bit and description in “DAC Control (Address
09h)” on page 58.
Added section “Headphone Amplifier Efficiency” on page 77.
Corrected ADC Filter Response shown in Figures 34, 35, 36, and 37 on page 82.
Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 53.
F1 Final Release
Revision Changes
88 DS679F1
CS42L51
Contacting Cirrus Logic Support
For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the term s a nd co nditio ns of sa le
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by C irrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringemen t of patent s or other r ights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any p atents, mask wo rk righ ts,
copyrights, tradem arks, trade secrets or oth er intellectual prop erty rights. Cirrus ow ns the copyrights a ssociated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERM ITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATI ONS, CUSTO MER AGREES, BY SUCH US E, TO FULL Y INDEMNIF Y CIRRUS, ITS OF FICE RS, DIRE CTORS, EMPLOYEES, DISTRI BUTORS AND
OTHER AGENTS FROM ANY AND ALL LIA BILITY, INCLUDING ATTORNE YS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
