SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V VCC operation.
The SN74AL VCH16601 combines D-type latches
and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low , the A data is latched if CLKAB is held at a high or low logic level.
If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the
high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16601 is characterized for operation from –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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56
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41
40
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38
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32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE†
INPUTS OUTPUT
CLKENAB OEAB LEAB CLKAB A B
X H X X X Z
XLH XL L
XLH XH H
HLL XXB
0‡
HLL XXB
0‡
LLL ↑LL
LLL ↑HH
LLL HXB
0‡
L L L L X B0§
†A-to-B data flow is shown; B-to-A flow is similar but uses
OEBA, LEBA, and CLKBA.
‡Output level before the indicated steady-state input
conditions were established, provided that CLKAB was high
before LEAB went low
§Output level before the indicated steady-state input
conditions were established
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CE
1D
C1
CLK
CE
1D
C1
CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
354
To 17 Other Channels
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
IOH
High level out
p
ut current
VCC = 2.3 V –12
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V –12
mA
VCC = 3 V –24
VCC = 1.65 V 4
IOL
Low level out
p
ut current
VCC = 2.3 V 12
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V 12
mA
VCC = 3 V 24
∆t/∆vInput transition rise or fall rate 10 ns/V
TAOperating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
IOH = –100 µA1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
VOH 2.3 V 1.7 V
IOH = –12 mA 2.7 V 2.2
3 V 2.4
IOH = –24 mA 3 V 2
IOL = 100 µA1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
VOL
IOL = 6 mA 2.3 V 0.4
V
V
OL
IOL =12mA
2.3 V 0.7
V
I
OL =
12
mA
2.7 V 0.4
IOL = 24 mA 3 V 0.55
IIVI = VCC or GND 3.6 V ±5µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
II(hold) VI = 1.7 V 2.3 V –45 µA
()
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V‡3.6 V ±500
IOZ§VO = VCC or GND 3.6 V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 40 µA
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
CiControl inputs VI = VCC or GND 3.3 V 4 pF
Cio A or B ports VO = VCC or GND 3.3 V 8 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§For I/O ports, the parameter IOZ includes the input leakage current.
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency †150 150 150 MHz
t
Pulse LE high †3.3 3.3 3.3
ns
t
wduration CLK high or low †3.3 3.3 3.3
ns
Data before CLK↑†2.3 2.4 2.1
t
Setu
p
time
Data before LE↓
CLK high †2 1.6 1.6
ns
t
su
Set
u
p
time
Data
before
LE↓
CLK low †1.3 1.2 1.1
ns
CLKEN before CLK↑†2 2 1.7
Data after CLK↑†0.7 0.7 0.8
th
Hold time
Data after LE↓
CLK high †1.3 1.6 1.4
ns
t
h
Hold
time
Data
after
LE↓
CLK low †1.7 2 1.7
ns
CLKEN after CLK↑†0.3 0.5 0.6
†This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
(INPUT)
(OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
fmax †150 150 150 MHz
A or B B or A †1 4 4.6 4.1
tpd LEAB or LEBA
AorB
†1 4.6 5.3 4.7 ns
CLKAB or CLKBA
A
or
B
†1.2 5.2 5.8 5
ten OEAB or OEBA A or B †1.1 5.3 6.1 5.2 ns
tdis OEAB or OEBA A or B †1.4 4.9 4.8 4.4 ns
†This information was not available at the time of publication.
operating characteristics, TA = 25°C
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
TEST
CONDITIONS
TYP TYP TYP
UNIT
Cd
Power dissipation Outputs enabled
CL=50
p
F
f=10MHz
†41 52 p
F
C
pd capacitance Outputs disabled
C
L =
50
pF
,
f
=
10
MH
z†6 6
pF
†This information was not available at the time of publication.
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027E – JULY 1995 – REVISED MA Y 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
0 V
1.5 V 2.7 V
0 V
1.5 V 0 V
2.7 V
0 V
1.5 V 1.5 V
tw
Input
2.7 V 2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
1.5 V
Figure 3. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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