Features Advanced-user programmable macro- cell CMOS EPROM technology for repro- grammability @ Up to 20 input terms 10 programmable VO macrocelis PLDC20RA10 Military/Industrial tpp = 20 ns tco = 20 ns tsu = 10 ns Low power Ic max 80 mA (Commercial) Icc max = 85 mA (Military) High reliability Reprogrammable Asynchronous CMOS Logic Device mable logic device employing a flexible ma- crocell structure that allows any individual output to be configured independently asa combinatorial output orasa fully asynchro- nous D-type registered output. The Cypress PLDC20RA10 provides low- er-power operation with superior speed performance than functionally equivalent bipolar devices through the usc of high-per- @ QOutput macrocell programmable as _ 7 combinatorial or asynchronous D- Proven EPROM technology formance ().8-micron CMOS manufactur- type registered output >2001V input protection ing technology. e Product-term control of register ~~ roore programming and functional The PLDC20RA 10 is packaged in a 24 pin clock, reset and set and output enable vesting ; . 300-mil molded DIP, a 300-mil windowed Register preload and power-up reset Windowed DIP, windowed LCC, DIP, cerDIP, and a 28-lead square leadless chip " LCC, PLCC available carrier, providing up to 20 inputs and 10 e Four data product terms per output : cogs , aa ae macrocell Functional Description outputs. When the windowed device is ex- one he Corenee . oy high ne posed to UV light, the 20RA10 is erased e Fast The Cypress PLDC ORA 10 is a high-per- and can then be reprogrammed. Commercial formance, second-generation program- tpp = 1S ns tco = 15 ns tsu = 7 ns Logic Block Diagram Vss Ig la \7 6 \5 la 13 2 h to PL fo OO OO Or 4 4 4 4 4 4 a 4 a ta 4 ts 44 44 e is 44 4 44 [acroce macrocert| [Macrocett||macroceL [macroceni! bwacroce.| Imacrocece||Macrocett| |Macrocett]] macroceL a OE Wig Og WOz VO, Os WOa WOg Wz vO, WOo Vec RA10-1 Selection Guide Generic Part tpp ns tsu ns tco ns Icc ns Number Com Mil/Ind Com Mil/Ind Com! Mil/Ind Com'l Mil/Ind 20RA 10-15 15 7 15 80 20RA10-20 20 20 10 10 20 20 80) &5 20RA 10-25 25 15 25 85 20RA10-35 35 20 35 8sPLDC20RA10 STD PLCC/HLCC Top Vie JEDEC PLCC/HLCC!!! Top View Ww Ne 4 3 2 1 282726 4321 282726 WO nc qs 25 WOo io G5 25D 102 YO3 3 $ 24 5 03 136 24D 1/03 vOa 4 a 4 ! 23 yo VO5 nos PLDC20RA10 256 1105 net]s PLDC20RA10 3D wo Wg pge 0g is CG7C324 31 P yo 07 sq: O07 le 5 We NCO 31344 1516 1718 P NC " D107 ~ oo Qu Ss wD = I9o9e mY ow RA10-2 rose RA10-3 B83 s RAIO-4 Macrocell Architecture Figure / illustrates the architecture of the 20RAIO macrocell. The cell dedicates three product terms for fully asynchronous controlof the register set, reset, and clock functions, as well as, one term for control of the output enable function. The output enable product term output is ANDed with the input from pin {3 to allow cither product term or hardwired external control of the output or a combination of control from both sources. If product-term-only control is selected, it is automati- cally chosen for all outputs since, for this case, the external out- put enable pin must be tied LOW. The active polarity of each output may be programmed independently fer each output cell and is subsequently fixed. Figure 2 illustrates the output enable options available. Whenan /Ocellisconfigured as an output, combinatorial-only ca- pability may be selected by forcing the set and reset product term outputs tobe HIGH under all input conditions. This is achieved by programming all input term programming cells for these two prod- uct terms. Figure 3 illustrates the available output configuration options. An additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-defined logic functions. Programmable 1/O Because any of the ten 1/O pins may be selected as an input, the de- vice input configuration programmed by the user may vary froma total of nine programmable plus ten dedicated inputs (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable I/O cells configured as outputs. Each input pin available ina given configuration is avail- Note: |.) The CG7C324 is the PLDC20RA 10 packaged in the JEDEC-cumpat- ible 28-pin PLCC pinout. Pin fuction and pin order is identical for both PLCC pinouts. The principal differencd is in the location of the no connect (NC) pins. to able as an input to the four control product terms and four uncom- mitted product terms ofeach programmable I/O macrocell that has been configured as an output. An 1/O cell is programmed as an input by tying the output enable pin (pin 13) HIGH or by programming the output enable product term to provide a LOW, thereby disabling the output buffer, for all possible input combinations. When utilizing the [/O macrocell as an output, the input path func- tions as a feedback path allowing the output signal to be fed back as an input to the product term array, When the output cell is config- ured as a registered output, this feedback path may he used to feed back the current output state to the device inputs to provide cur- rent state control of the next output state as required for state ma- chine implementation. Preload and Power-Up Reset Functional testability of programmed devices is enhanced by inclu- sion of register preload capability, which allows the state of each register to be set by loading cach register from an external source prior to exercising the device. Testing of complex state machine de- signs is simplified by the ability to load an arbitrary state without cycling through long test vector sequences to reach the desired state. Recovery from illegal states can be verified by loading illegal states and observing recovery. Preload ofa particular register is ac- complished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a logic LOW level. If the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. To insure predictable system initialization, all registers are preset to a logic LOW state upon power-up, there- by setting the active LOW outputs to a logic HIGH. -36PLDC20RA10 OUTPUT ENABLE PIN 1) (FROM PIN 13) TO 1/0 PIN AAI0-5 Figure 1. PLDC20RA10 Macrocell Output Always Enabled Programmable >o RAIO-6 AAIO-7 Combination of Programmable and Hardwired RAI0-8 ~O RA10-9 Figure 2. Four Possible Output Enable Alternatives for the PLDC20RAI0 External Pin OEPLDC20RA10 CYPRESS Registered/Active LOW Combinatorial/Active LOW i za RA10-10 : Registered/Active HIGH Combinatorial/Active HIGH ap bo i 2 RAI10-12 NY Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10 bo 38 RAI011 RAI0-13PLDC20RA10 CYPRESS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Latch-Up Current ..... 0.0.0 ce eee > 200 mA not tested.) DC Program Voltage 2.00.00. 0 6c cece cece ete tees 13.0V Storage Temperature ........ 0.00.00 0006 65C to + 150C . . : erating Ran: Ambient Temperature with Op ing hange Power Applied ........ 000.0... eee 55C to + 125C Ambient Supply Voltage to Ground Potential Range Temperature Vee (Pin 24 to Pin 12) 2.0.00. -0.5V to +7.0V Commercial OPC 10 75C SV + 10% DC Voltage Applied to Outputs Tn o o in High Z State... 0. secs sec veeecece eee -05V to +7.0V | Industrial ~A0PC to +85C SV + 10% DC Input Voltage .......000. 0.0... c eee ~3.0Vto+7.0V Militaryl?l 55C to +125C 5V + 10% Output Current into Outputs (LOW) ............005 lomA Static Discharge Voltage .....0.. 0... cece eee >2001V (per MIL-STD-883, Method 3015) Electrical Characteristics Over the Operating Rangel*] Parameter Description Test Conditions Min. | Max. | Unit Vou Veco = Min., lou =-3.2mA Com! 2.4 Vv Output HIGH Voltage Vin =Vin or Vy. - lon = ~2mA Mil/ind Von. Output LOW Voltage Voc = Min., lol = 8mA 0.5 Vv VIN = VIn OF VIL Vin Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputsl4] | 2.0 v Vit Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputsl4] 0.8 Vv Iix Input Leakage Current Vss <= Vin < Veco. Voc = Max -10 | +10 pA loz Output Leakage Current Veco = Max. Vss < Vout < Vee -40 | +40 | vA Isc Output Short Circuit Current] | Voc = Max., Vout = 0.SVI8 -30 | -90 | mA lec Standby Power Supply Current | Vcoc= Max., Vin = GND Outputs Open Com] 78 mA Mil/Ind 80 mA Iec2 Power Supply Current at Vcc = Max., Outputs Disabled (In High Z Com! 80 mA Frequency! State) Device Operating af f wens Penge AMAX Mil/ind 85 | mA Capacitancel'| Parameter Description Test Conditions Max. Unit CIN Input Capacitance Vin = 2.0 V @ f = 1 MHz 10 pF Cour Output Capacitance Vour = 2.0 V @ f = 1 MHz 10 pF Notes: 2. Ta is the instant on case temperature. 5. Tested initially and after any design or process changes that may affect 3. See the last page of this specification for Group A subgroup testing in- these parameters. formation. Not more than one output should be tested at a time. Duration of the 4. These are absolute values with respect to devicee ground and all over- short circuit should not be more than one second. Vout = 0.5 V has shoots due to system or tester noise are included. been chosen to avaid test problems caused by tester ground degrada- tion. 2-39PLDC20RA10 CYPRESS AC Test Loads and Waveforms (Commercial) Ri 4572 Ri 4572 ALL INPUT PULSES (47082 MIL) (4702 MIL) 3.0 5V BV OUTPUT R20 OUTPUT t Re GND $ 2702 & 2702 50 rT i (3199 Mil) 5 rT > (3190 Mil) = OMS INCLUDING = = INCLUDING = = JIG AND JIG AND SCOPE SCOPE RatO-14 RAI0-15 (a) (b} Equivalent to: THEVENIN EQUIVALENT (Commercial) Equivalent to: THEVENIN EQUIVALENT (Military/Industrial} 17002 OUTPUT O~ww ss 1.88V= Vine OUTPUT owr0 2.02V=Vine RAI0-16 RA10-17 Parameter | Vin Output Waveform--Measurement Level texz- L5V Vv woe -) Oo sv Vx AA10-18 tpxz(+) 2.6V Vor 0.5V Vx RAI0-19 0.5V Vv { Vin. OH PZX(+) the Vx vp RA10-20 P2X(-) the x 05V VoL RAI0-21 Vv teR(-} 15V OWS Vx RAI0-22 teR(+) 2.6V Vor. O.5. Vx RA10-23 thac+) Vine Vx OSV Vou RA10-24 thac- Vihe Vv qa A) the x "O5V Vol. RAI0-25 {ce}7 CYPRESS PLDC20RA10 Switching Characteristics Over the Operating Rangel? 7 8} Commercial Military/Industrial -15 -20 ~20 -25 -35 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tpp Input or Feedback to 15 20 20 25 35 ns Non-Registered Output tha Input to Output Enable i) 20 20 30 35 ns teR Input to Output 15 20 20 30 a5 ns Disable tpzx Pin 13 to Output 12 15 15 20 25 ns Enable Ipxz Pin 13 to Output 12 15 15 20 25 ns Disable tco Clock to Output 15 20 20) 25 35 ns tsu Input or Feedback 7 10 10 15 20 ns Set-Up Time ty Hold Time 3 5 3 5 5 ns tp Clock Period 22 30 30 40 55 ns (tsu + too) twH Clock Width HIGHE1 10 13 12 18 25 ns tw Clock Width LOwWD| 10 13 12 18 25 ns {MAX Maximum Frequency 45.5 33.3 33.3 25.0 18.1 MHz (I/tp)t ts Input of Asynchronous 15 20 20 25 40 ns Set to Registered Output tr Input of Asynchronous Is 20 20) 25 40 ns Reset to Registered Output taRW Asynchronous Reset 15 20 20 25 25 ns Widthl*] lasw Asynchronous Set i5 20 20 25 25 ns Widthl} tar Asynchronous Set/ 10 12 12 15 20: ns Reset Recovery Time twe Preload Pulse Width {5 IS 15 15 15 ns tsup Preload Set-Up Time 15 15 15 15 15 ns tue Preload Hold Time 15 1S 15 15 15 ns Notes: 7, Part (apof AC Test Loads was used for all parameters except tea, ter, HIGH output or Voy, +0.5 for an enabled LOW output. Please see tpzx and tpxz. which use part (b). part (c) of AC Test Loads and Waveforms for waveforms and measure- 8. The parameters tep and tpxz are measured as the delay from the in- ment reference levels, put disable logic threshold transition to Vou 0.5 V for an enabledSPY Cyeress PLDC20RA10 Switching Waveform - ty INPUTS, REGISTERED / L FEEDBACK _A x _ pe fe tgu tp cP A K t t ASYNCHRONOUS wel RESET tan ASYNCHRONOUS ~ SET Le toy OUTPUTS he too (HIGH ASSERTED) ter tea OUTPUT ENABLE INPUT PIN RA10-26 Preload Switching Waveform PIN 13 OUTPUT t ENABLE ER tea REGISTER \ | OUTPUTS } tgup tHe PIN 1 RAI0-27 TOV PRELOAD CLOCK we Asynchronous Reset ASYNCHRONOUS Taaw RESET / cn OUTPUT T RAI0-28 Asynchronous Set ASYNCHRONOUS 7 SET /._ sw e ts | OUTPUT Vi RAI0-29SF coors PLDC20RA10 =F Functional Logic Diagram 1 RA10-30 O 3 4 F 8 1218 1699 2023 3427 2831 37255 We=p CYPRESS PLDC20RA10 Ordering Information tpp tsu tco Package Operating Tec (ns) (ns) (ns) Ordering Code Name Package Type Range 80 15 7 15 PLDC20RA101SHC H64 28-Pin Windowed Leaded Chip Carrier | Commercial PLDC20RA10 15JC J64 28-Lead Plastic Leaded Chip Carrier PLDC20RAI1015PC P13 24-Lead (300-Mil} Molded DIP PLDC20RA1015WC wid 24-Lead (300-Mil) Windowed CerDIP CG7C324-AISHC H64 28-Pin Windowed Leaded Chip Carrier CG7C324A15SIC J64 28-Lead Plastic Leaded Chip Carrier 80 20 10 20 PLDC20RA1020HC H64 28-Pin Windowed Leaded Chip Carrier | Commercial PLDC20RAIL0205C J64 28-Lead Plastic Leaded Chip Carrier PLDC20RAI020PC P13 24-Lead (300-Mil) Molded DIP PLDC20RAI020WC Wi4 24-Lead (300-Mil) Windowed CerDIP CG7C324-A20HC H64 28-Pin Windowed Leaded Chip Carrier CG7C324-A205C J64 28-Lead Plastic Leaded Chip Carrier 85 20 10 20 PLDC20RA10-20DI D14 24-Lead (300-Mil) CerDIP Industrial PLDC20RA10-20J1 J64 28-Lead Plastic Leaded Chip Carrier PLDC20RA1020PI P13 24-Lead (300-Mil) Molded DIP PLDC20RA1020WI wl4 24-Lead (300-Mil) Windowed CerDIP PLDC20RA1L020DMB D4 24-Lead (300-Mil) CerDIP Military PLDC20RA10-20HMB H64 28-Pin Windowed Leaded Chip Carrier PLDC20RA1020LMB L64 28-Square Leadless Chip Carrier PLDC20RA10-2QMB Q64 28-Pin Windowed Leadless Chip Carrier PLDC20RA1020WMB | W14 24-Lead (300-Mit} Windowed CerDIP 85 25 IS 25 PLDC20RAI0-25DI D14 24-Lead (300-Mil) CerDIP Industrial PLDC20RA1025J1 J64 28-Lead Plastic Leaded Chip Carrier PLDC20RA1025PI P13 24-Lead (300-Mil) Molded DIP PLDC20RAI025WI1 wi4 24-Lead (300-Mil) Windowed CerDIP PLDC20RA1025DMB D4 24-Lead (300-Mil) CerDIP Military PLDC20RA1025HMB H64 28-Pin Windowed Leaded Chip Carrier PLDC20RA10-25LMB L64 28-Square Leadless Chip Carrier PLDC20RA 10-25QMB Q64 28-Pin Windowed Leadless Chip Carrier PLDC20RA10-25WMB | WI14 24-Lead (300-Mil) Windowed CerDIP 85 35 20 35 PLDC20RA10-35DI DI4 24-Lead (300-Mil) CerDIP Industrial PLDC20RA103J1 J64 28-Lead Plastic Leaded Chip Carrier PLDC20RAI035PI Pi3 24-Lead (300-Mil) Molded DIP PLDC20RAL0-35WI wi4 24-Lead (300-Mil) Windowed CerDIP PLDC20RA10-35DMB D14 24-Lead (300-Mil) CerDIP Military PLDC20RA1035HMB HO64 28-Pin Windowed Leaded Chip Carrier PLDC20RA1035LMB L64 28-Square Leadless Chip Carrier PLDC2URA10-35QMB O64 28-Pin Windowed Leadless Chip Carrier PLDC20RAI0-35WMB] W114 24-Lead (300-Mil) Windowed CerDIP=, CYPRESS PLDC20RA10 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou Voi Viet 1, 2,3 Vib 1, 2.3 lix 1,2,3 loz. 12,3 lee 1,2,3 Switching Characteristics Parameter Subgroups tpp 9, 10, I tezx 9, 10, tL Ico 9,10, 11 tsu 9.10, 11 Gt 9.10, 11 Document #: 3800073-E