A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver DESCRIPTION FEATURES AND BENEFITS The A8519 is a multi-output LED driver for small-size LCD backlighting. It integrates a current-mode boost converter with internal power switch and four current sinks. The boost converter can drive up to 44 white LEDs, 11 LED per string, at 100 mA. The LED sinks can be paralleled together to achieve higher LED currents up to 400 mA. The A8519 operates from a single power supply from 4.5 to 40 V, which allows the part to withstand load dump conditions encountered in automotive systems. * Automotive AEC-Q100 qualified * Fully integrated 42 V MOSFET for boost converter * Fully integrated LED current sinks * Withstands surge input up to 40 VIN for load dump * Operates down to 3.9 VIN (max) for idle stop * Drives four strings of LEDs * Maximum output voltage 40 V Up to 11 white LEDs in series * Drive current for each string is 100 mA * Programmable boost switching frequency (200 kHz to 2.15 MHz) * Synchronized boost switching frequency option (320 kHz to 2.3 MHz) * Dithering of boost switching frequency to reduce EMI * Extremely high LED contrast ratio 10,000:1 using PWM dimming alone 100,000:1 when combining PWM and analog dimming The A8519 can control LED brightness through a digital (PWM) signal. An LED brightness contrast ratio of 10,000:1 can be achieved using PWM dimming at 100 Hz; a higher ratio of 100,000:1 is possible when using a combination of PWM and analog dimming. If required, the A8519 can drive an external P-channel MOSFET to disconnect input supply from the system in the event of a fault. The A8519 provides protection against output short, overvoltage, open or shorted diode, open or shorted LED pin, and overtemperature. A cycle-by-cycle current limit protects the internal boost switch against high-current overloads. Continued on the next page... PACKAGES: 20-Pin TSSOP with Exposed Thermal Pad (suffix LP) 28-Pin QFN with Exposed Thermal Pad (suffix ET) Continued on the next page... APPLICATIONS: * Automotive infotainment backlighting * Automotive cluster * Automotive center stack Not to scale Typical Application Diagram VIN Optional L1 Q1 VOUT > VIN D1 RSC ROVP RADJ CIN COUT1 GATE VSENSE SW COUT2 VOUT VIN OVP VDD VC LED1 RPU CVDD A8519 FAULT LED2 LED3 PWM LED4 APWM CLKOUT ISET FSET AGND PGND COMP CP RISET RFSET RZ CZ GND Typical Application Circuit Showing VOUT-to-Ground Short Protection Using Optional P-Channel MOSFET A8519-DS, Rev. 10 MCO-0000554 March 14, 2019 A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver FEATURES AND BENEFITS (CONTINUED) DESCRIPTION (CONTINUED) * Excellent input voltage transient response at lowest PWM duty cycle * Gate driver for optional P-channel MOSFET input disconnect switch * LED current accuracy 0.7% * LED string current-matching accuracy 0.8% * Protection against: Shorted boost switch, inductor or output capacitor Shorted FSET or ISET resistor Open or shorted LED pins and LED strings Open boost diode Overtemperature The A8519 has a synchronization pin that allows boost switching frequencies to be synchronized in the range of 320 kHz to 2.3 MHz. The high switching frequency allows the converter to operate above the AM radio band. The IC contains a clock output pin that allows other converters to be synchronized to theA8519's boost switching frequency. The A8519 employs hysteresis control to help regulate the LED current at extremely short PWM on-time. The A8519-1 is identical to the A8519, except that it uses a smaller hysteresis window to reduce output voltage ripple during PWM dimming. SELECTION GUIDE Part Number Operating Ambient Temperature Range TA (C) Hysteresis Window Package Packaging [1] Leadframe Plating A8519KLPTR-T -40 to 125 350 mV 20-pin TSSOP with exposed thermal pad 4000 pieces per reel 100% matte tin A8519KETTR-R -40 to 125 350 mV 28-pin 5 x 5 mm QFN with exposed thermal pad and sidewall plated 1500 pieces per reel 100% matte tin A8519KLPTR-T-1 -40 to 125 150 mV 20-pin TSSOP with exposed thermal pad 4000 pieces per reel 100% matte tin A8519KETTR-R-1 -40 to 125 150 mV 28-pin 5 x 5 mm QFN with exposed thermal pad and sidewall plated 1500 pieces per reel 100% matte tin [1] Contact Allegro for additional packing options. ABSOLUTE MAXIMUM RATINGS [2] Characteristic Symbol Rating Unit -0.3 to 40 V -0.3 to 40 V VIN, VOUT -0.3 to 40 V VSENSE, VGATE VIN -7.4 to VIN +0.4 V -0.6 to 42 V -1 to 48 V -0.3 to 40 V -0.3 to 5.5 V LEDx Pins VLEDx OVP Pin VOVP VIN, VOUT Pins VSENSE, GATE Pins SW Pin [3] VSW FAULT Pin VFAULT Notes x = 1, 2, 3, or 4 Continuous t < 50 ns APWM, PWM, CLKOUT, COMP, FSET, ISET, VDD Pins Operating Ambient Temperature TA -40 to 125 C Maximum Junction Temperature TJ(max) 150 C Tstg -55 to 150 C Storage Temperature K temperature range [2] Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. [3] SW DMOS is self-protecting and will conduct when V SW exceeds 48 V. 2 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information. Characteristic Symbol Test Conditions [1] Value Unit 40 C/W Contact factory C/W LP Package on 4-layer PCB Based on JEDEC Standards 29 C/W ET Package on 4-layer PCB Based on JEDEC Standards 32 C/W LP Package on 2-layer 3 Package Thermal Resistance [1] Additional RJA in2 PCB ET Package on 2-layer 3 in2 PCB thermal information available on the Allegro website. Table of Contents Features and Benefits............................................................ 1 Description........................................................................... 1 Applications.......................................................................... 1 Packages............................................................................. 1 Typical Application Diagram.................................................... 1 Specifications....................................................................... 2 Selection Guide................................................................. 2 Absolute Maximum Ratings................................................. 2 Thermal Characteristics...................................................... 3 Functional Block Diagram...................................................... 4 Pinout Diagrams and Terminal List.......................................... 5 Electrical Characteristics........................................................ 6 Characteristic Performance.................................................. 10 Functional Description......................................................... 12 Enabling the IC................................................................ 12 Powering Up: LED Pin Check............................................ 12 Powering Up: Boost Output Undervoltage Protection............ 13 Soft-Start Function........................................................... 14 Frequency Selection......................................................... 14 Synchronization............................................................... 14 LED Current Setting and LED Dimming.............................. 18 PWM Dimming................................................................ 19 APWM Pin...................................................................... 20 Extending LED Dimming Ratio.......................................... 21 Analog Dimming.............................................................. 21 LED String Short Detect.................................................... 22 Overvoltage Protection..................................................... 23 Boost Switch Overcurrent Protection.................................. 24 Input Overcurrent Protection and Disconnect Switch............ 25 Setting the Current Sense Resistor.................................... 26 Input UVLO..................................................................... 26 VDD............................................................................... 26 Shutdown....................................................................... 26 Dithering Feature............................................................. 27 Fault Protection During Operation...................................... 28 Application Information........................................................ 31 Design Example.............................................................. 31 Package Outline Drawings................................................... 36 3 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Functional Block Diagram FSET SW Oscillator Frequency Dithering + CLKOUT Error Amplifier - Driver Circuit Diode Open + Sense + COMP - Current Sense - Internal Soft Start Block PGND VIN Regulator UVLO Block VREF 1.235 V Reference OCP2 TSD VOUT Hyst. Control OVP2 AGND VOUT Internal VCC VDD OVP Sense Fault Block Input Current Sense - Amplifier Open/Short LED Detect + VSENSE OVP IADJ LED1 AGND Vin LED Driver Block Gate Off NMOS Driver GATE LED2 LED3 LED4 APWM Internal VCC Enable Block ISET PWM VREF PWM Block ISET Block AGND FAULT AGND AGND PGND AGND 4 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver PINOUT DIAGRAMS 16 AGND NC VOUT OVP 24 23 22 SW NC APWM 6 16 LED4 PWM 7 15 LED3 8 9 11 VDD Name SW 17 Terminal List Table Pin Number 26 5 12 APWM CLKOUT 10 25 COMP VDD 14 FAULT 9 PGND 18 LED2 13 PWM 19 4 12 VIN 8 3 13 14 FSET FAULT CLKOUT NC VSENSE 7 PGND LED1 15 ISET PGND 20 11 PAD 21 2 ISET GATE 6 1 NC FSET SW 5 VIN 10 17 LED1 AGND 18 LED2 AGND OVP 3 VOUT 4 VSENSE 19 LED3 GATE 20 LED4 PGND 2 27 COMP 1 28-Pin QFN with Exposed Thermal Pad (suffix ET) 28 20-Pin TSSOP with Exposed Thermal Pad (suffix LP) Function LP ET 1 18 COMP Output of the error amplifier and compensation node. Connect an Rz-Cz-Cp network from this pin to GND for control loop compensation. 2 19, 20, 21 PGND Power ground for internal N-channel MOSFET switching device. Connect to PCB ground plane. 3 22 OVP 4 23 VOUT 5 25, 26 SW 6 27 GATE 7 28 VSENSE 8 1 VIN 9 3 FAULT 10 4 CLKOUT 11 5 VDD 12 6 APWM 13 7 PWM Enables the IC when this pin is pulled high. Also serves to control the LED intensity by using pulse-width modulation. Typical PWM dimming frequency is in the range of 100 to 400 Hz. 14 8 FSET Frequency/synchronization pin. A resistor RFSET from this pin to GND sets the switching frequency (with dithering superimposed). It can also be used to synchronize two or more converters in the system to an external frequency between 320 kHz and 2.3 MHz (dithering is disabled in this case). 15 9 ISET Connect RISET resistor between this pin and GND to set the desired LED current setting. Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection level. Connect directly to boost output voltage. The drain of the internal N-channel MOSFET switching device of the boost converter. Output gate driver pin for external P-channel MOSFET control. Connect this pin to the negative sense side of the current sense resistor Rsc. The threshold voltage is measured as VIN-VSENSE. There is also fixed current sink to allow for trip threshold adjustment. Input power to the IC as well as the positive input used for current sense resistor. The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 100 kW resistor between this pin and desired logic level voltage. Logic output representing the switching frequency of internal boost oscillator. This allows other converters to be synchronized to the same frequency (with the same frequency dithering, if applicable) Output of internal LDO (bias regulator). Connect a 1 F decoupling capacitor between this pin and GND. Analog trimming option or dimming. Applying a digital PWM signal to this pin adjusts the internal IISET current. 16 10, 11 AGND 17, 18, 19, 20 13, 14, 15, 16 LED current ground. Connect to PCB ground plane. LED 1-4 - 2, 12, 17, 24 NC No connect. Leave open or connect to GND. - - PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad. LED current sinks #1 to 4. Connect the cathode of each LED string to associated pin. Unused LED pin must be terminated to GND through a 3.09 k resistor. 5 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25C; indicates specifications guaranteed over the full operating temperature range with TA = TJ = -40C to 125C; typical specifications are at TA = 25C Characteristic Symbol Test Conditions Min. Typ. Max. Unit 4.5 - 40 V INPUT VOLTAGE Input Voltage Range [3] VIN UVLO Start Threshold VUVLOrise VIN rising - - 4.35 V UVLO Stop Threshold VUVLOfall VIN falling - - 3.9 V UVLO Hysteresis VUVLOHYS 300 450 600 mV INPUT SUPPLY CURRENT Input Quiescent Current Input Sleep Supply Current IQ ISLEEP VPWM = VIH, fSW = 2 MHz - 8 15 mA VIN = 16 V, VPWM = VSYNC = 0 V - 2.0 10 A INPUT LOGIC LEVELS (PWM, APWM) Input Logic Level Low VIL - - 0.4 V Input Logic Level High VIH 1.5 - - V PWM Input Pull-Down Resistor APWM Input Pull-Down Resistor REN VPWM = 5 V 60 100 140 k RAPWM VPWM = VIH 60 100 140 k 40 - 1000 kHz APWM APWM Frequency [2] fAPWM OUTPUT LOGIC LEVELS (CLKOUT) Output Logic Level Low VOL 5 V < VIN < 40 V - - 0.3 V Output Logic Level High VOH 5 V < VIN < 40 V 1.8 - - V A ERROR AMPLIFIER Source Current IEA(source) VCOMP = 1.5 V - -600 - Sink Current IEA(sink) VCOMP = 1.5 V - +600 - A COMP Pin Pull-Down Resistance RCOMP FAULT = 0, VCOMP = 1.5V - 1.4 - k VOVP(th) OVP pin connected to VOUT 7 8.3 9.5 V IOVP(th) Current into OVP pin 190 200 210 A IOVP(LKG) VIN = 16 V, PWM = L - 0.1 1 A - - 5 % - 3 - V - 0.55 0.7 V 42 45 48 V OVERVOLTAGE PROTECTION OVP Pin Voltage Threshold OVP Pin Sense Current Threshold OVP Pin Leakage Current OVP Accuracy Undervoltage Protection Threshold VUVP(th) Secondary Overvoltage Protection VOVP(sec) Measured at VOUT pin when ROVP = 160 kW [2] Measured at VOUT pin when ROVP = 0 Measured at SW pin Continued on the next page... [1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). by design and characterization, not production tested. [3] Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V IN IN [4] LED current is trimmed to cancel variations in both Gain and ISET voltage [2] Ensured 6 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25C; indicates specifications guaranteed over the full operating temperature range with TA = TJ = -40C to 125C; typical specifications are at TA = 25C Characteristic Symbol Test Conditions Min. Typ. Max. Unit BOOST SWITCH Switch On-Resistance RSW ISW = 0.75 A, VIN = 16 V 100 250 500 m Switch Leakage Current ISW(LKG) VSW = 16 V, VPWM = VIL - 0.1 1 A Switch Current Limit ISW(LIM) 3 3.65 4.5 A - 4.9 - A Secondary Switch Current Limit [2] ISW(LIM2) Higher than max ISW(LIM) under all conditions part latches when detected Minimum Switch On-Time tSW(on) 45 65 85 ns Minimum Switch Off-Time tSW(off) - 65 85 ns RFSET = 10 k 1.95 2.15 2.35 MHz RFSET = 21.5 k OSCILLATOR FREQUENCY Oscillator Frequency [5] fSW 0.9 1 1.1 MHz RFSET = 110 k - 200 - kHz Oscillator Frequency Dithering Range fSW_DITH RFSET = 10 k - 5 - % Dithering Modulation Frequency fSW_MOD RFSET = 10 k - 12.5 - kHz A8519, RFSET = 10 k - 1.02 - V A8519-1, RFSET = 10 k - 1.07 - V - - 0.4 V FSET Pin Voltage VFSET SYNCHRONIZATION Sync Input Logic Level VSYNCL FSET pin logic Low VSYNCH FSET pin logic High 2 - - V Synchronized Switching Frequency fSW(sync) 320 - 2300 kHz Synchronization Input Min. Off-Time tSYNC(off) 150 - - ns Synchronization Input Min. On-Time tSYNC(on) 150 - - ns LED CURRENT SINKS LEDx Accuracy [4] ErrLED RISET = 8.33 kW - 0.7 3 % LEDx Matching LEDx IISET = 120 A - 0.8 2 % LEDx Regulation Voltage VLEDx VLED1 = VLED2 = VLED3 = VLED4, IISET = 120 A 750 850 975 mV ISET to ILEDx Current Gain AISET IISET = 120 A ISET Pin Voltage VISET Allowable ISET Current IISET VLEDx Short detect LED Startup Ramp Time [2] VLEDx(SC) tSS While LED sinks are in regulation; sensed from VLEDx to AGND Time duration before all LED channels come into regulation, or OVP is tripped 696 710 727 A/A 0.987 1.017 1.047 V 20 - 144 A 4.7 5.2 5.7 V - 20 - ms Continued on the next page... [1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). by design and characterization, not production tested. [3] Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V IN IN [4] LED current is trimmed to cancel variations in both Gain and ISET voltage [5] f SW measurements were taken with dithering function is disabled. [2] Ensured 7 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25C; indicates specifications guaranteed over the full operating temperature range with TA = TJ = -40C to 125C; typical specifications are at TA = 25C Characteristic Symbol Test Conditions Min. Typ. Max. Unit - 32750 - fSW cycles PWM DIMMING Maximum PWM Dimming Until OffTime [2] tPWML Measured while PWM = low, during dimming control and internal references are powered on (exceeding tPWML results in shutdown) tPWMH(min1) First cycle when powering up IC (VPWM = 0 to 3.3 V) - 0.75 2 s tPWMH(min) Subsequent PWM pulses - 0.5 1 s PWM High to LED On Delay td(PWMon) Time between PWM going high and when LED current reaches 90% of maximum (VPWM = 0 to 3.3 V) - 0.2 0.5 s PWM Low to LED Off Delay td(PWMoff) Time between PWM going low and when LED current reaches 10% of maximum (VPWM = 3.3 to 0 V) - 0.36 0.5 s Minimum PWM On-Time HYSTERESIS CONTROL Hysteresis Window (A8519) VHYST Measured at VOUT pin when PWM = H to L - 0.35 - V Hysteresis Window (A8519-1) VHYST1 Measured at VOUT pin when PWM = H to L - 0.15 - V IG(sink) VGATE = VIN, no input OCP fault - -113 - A VGATE = VIN - 6 V, input OCP fault tripped - 6 - mA GATE PIN Gate Pin Sink Current Gate Pin Source Current IG(source) Gate Shutdown Delay When Overcurrent Fault Is Tripped [2] tFAULT VIN - VSENSE = 200 mV, monitored at FAULT pin - - 3 s Gate Voltage VGATE Measured between GATE and VIN when gate is on - -6.7 - V 17.2 21.5 25.8 A 95 110 125 mV IFAULT = 1 mA - - 0.5 V VFAULT = 5 V - - 1 A 155 170 - C - 20 - C VSENSE PIN VSENSE Pin Sink Current VSENSE Trip Point IVSENSE VSENSE(trip) Measured between VIN and VSENSE, Radj = 0 FAULT PIN FAULT Pull-Down Voltage FAULT Pin Leakage Current VFAULT IFAULT(lkg) THERMAL PROTECTION (TSD) Thermal Shutdown Threshold [2] TSD Thermal Shutdown Hysteresis [2] TSD(hys) Temperature rising [1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). by design and characterization, not production tested. [3] Minimum V = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V = 3.9 V IN IN [4] LED current is trimmed to cancel variations in both Gain and ISET voltage [2] Ensured 8 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver VIN Optional L1 Q1 VOUT > VIN D1 RSC ROVP RADJ CIN COUT1 GATE VSENSE SW COUT2 VOUT VIN OVP VDD VC LED1 RPU CVDD A8519 LED2 FAULT LED3 PWM LED4 APWM CLKOUT ISET FSET AGND PGND COMP CP RFSET RISET RZ CZ GND Typical Application Showing Boost Configuration with Input Disconnect Switch to Protect Against VOUT-to-Ground Short L2 VIN Output: 3 WLED in series (~10 V) D2 L1 R1* CIN CSW ROVP D2* COUT GATE VSENSE SW VIN OVP VDD VC VOUT LED1 RPU CVDD A8519 FAULT LED2 LED3 PWM LED4 APWM CLKOUT ISET RISET FSET AGND PGND RFSET COMP CP RZ CZ *Notes: Input disconnect switch is not necessary in this case to protect against VOUT-to-ground short. R1 and D2 are used to provide a leakage path so the OVP pin is above 100 mV during startup. Otherwise, the IC would assume an VOUT-to-GND short and not proceed with soft start. GND Typical Application Showing SEPIC Configuration for Flexible Input/Output Voltage Ratio 9 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver CHARACTERISTIC PERFORMANCE Startup Waveforms Efficiency Measurement Efficiency at 60 mA/Channel for Various LED Configurations 89.00 88.00 87.00 Eff% 86.00 10 x 4 LED 85.00 9 x 4 LED 84.00 8 x 4 LED 83.00 7 x 4 LED 82.00 81.00 80.00 8 10 12 14 16 VIN (V) A8519 Evaluation Board Efficiency versus Input Voltage while Disconnect Switch and Snubber Circuit are Used Efficiency at VIN = 12 V for Various LED Configurations Start up at 100% PWM Dimming, VIN = 7 V, 4 Channels, 10 LEDs/Channel, 60 mA/Channel; Time base = 10 ms/Div 92.00 90.00 Eff% 88.00 7 x 4 LED 86.00 8 x 4 LED 84.00 9 x 4 LED 82.00 10 x 4 LED 80.00 78.00 0.1 0.2 0.3 0.4 Total LED Current (A) A8519 Evaluation Board Efficiency versus Total LED Current while Disconnect Switch and Snubber Circuit are Used Higher efficiency can be achieved by: * Using an inductor with low DCR. * Using lower forward voltage drop and smaller junction capacitance Schottky diode. * Removing the snubber circuit; however, this might compromise the EMI performance. * Shorting out the disconnect switch and the input current sense resistor; however, this will eliminate the output short-to-GND protection feature. * Lowering switching frequency. This will significantly improve the efficiency; however, to avoid the EMI AM band limits, careful switching frequency selection is required. In addition, a larger inductor will be needed. Start up at 0.02% PWM Dimming, VIN = 7 V, 4 Channels, 10 LEDs/Channel, 60 mA/Channel; Time base = 10 ms/Div 10 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Transient Response to Step Change in PWM Dimming Transient Response to Step Change in VIN Voltage From PWM = 0.1% to PWM = 100% at 4 Channels, 60 mA/Channel, VIN = 12 V; Time base = 50 ms/Div From VIN = 16 V to VIN = 5.5 V, 4 Channels, 60 mA/Channel, PWM = 100%; Time base = 50 ms/Div From PWM = 100% to PWM = 0.1% at 4 Channels, 60 mA/Channel, VIN = 12 V; Time base = 50 ms/Div From VIN = 5.5 V to VIN = 16 V, 4 Channels, 60 mA/Channel, PWM = 100%; Time base = 50 ms/Div 11 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver FUNCTIONAL DESCRIPTION Enabling the IC The IC turns on when a logic high signal is applied on the PWM pin with a minimum duration of tPWMH for the first clock cycle, and the input voltage present on the VIN pin is greater than 4.35 V to clear the UVLO threshold. Before the LEDs are enabled, the A8519 driver goes through a system check to see if there are any possible fault conditions that might prevent the system from functioning correctly. Also if the FSET pin is pulled low the IC will not power up. More information on the FSET pin can be found in the Synchronization section of the datasheet. Figure 2: Power Up Diagram Showing Disconnect VGATE, VLED1, VISET, and VPWM During LED Pins Detect and Regulation Period When the voltage threshold on VLEDx pins exceeds 120 mV, a delay between 3000 and 4000 clock cycles (1.5 to 2 ms) is used to determine the status of the pins. Table 1: LED Detection Duration for Given Switching Frequency Switching Frequency Detection Time 2 MHz 1.5 to 2 ms 1 MHz 3 to 4 ms 800 kHz 3.75 to 5 ms 600 kHz 5 to 6.7 ms Figure 1: Power Up Diagram Showing PWM, ISET, and VDD Voltages and Total LED Current Once the IC is enabled, there are only two ways to shut down the IC into low-power mode: 1. Pull PWM pin to low for at least 32,750 clock cycles (approximately 16 ms at 2 MHz). 2. Cut off the supply and allow VIN to drop below UVLO falling threshold (less than 3.9 V). All unused LED pins should be connected with a 3.09 k resistor to GND. The unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. Powering Up: LED Pin Check Once VIN pin goes above UVLO and a high signal is present on the PWM pin, the IC proceeds to power up. The A8519 then enables the disconnect switch (GATE) and checks to see if the LED pins are shorted to ground and/or are not used. The LED detect phase starts when the GATE voltage of the disconnect switch is equal to VIN - 3.3 V. Figure 2 shows the relation of LEDx pins with respect to the gate voltage of the disconnect switch (if used) during LED detect phase, as well as the duration of the LED detect for a switching frequency of 2 MHz. LED String LED Strings Use LED1 Channel Only Use Four LED Channels LED1 LED1 LED2 LED2 LED3 LED3 LED4 LED4 3.09 k AGND GND 3.09 k 3.09 k AGND GND Figure 3: Channel Select Setup 12 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Table 2: LED Detection Voltage Thresholds LED Pin Voltage Level LED Pin Action Less than 70 mV Indicates a short to PCB GND A8519 will not proceed with power up. 150 mV Not used LED string connected with the unused LED pin is removed from operation 325 mV LED pin in use None If an LED pin is shorted to ground, the A8519 will not proceed with soft-start until the short is removed from the LED pin. This prevents the A8519 from powering up and putting an uncontrolled amount of current through the LEDs. Figure 6: One LED Pin is Shorted to GND. The IC will not proceed with power up until LED pin is released, at which point the LED pin is checked to see if it is used. Figure 4: LED String Detect Occurs when All LED Strings are Selected to be Used Powering Up: Boost Output Undervoltage Protection During startup, after the input disconnect switch has been enabled, the output voltage is checked through the OVP pin. If the sensed voltage does not rise above VUVP(th), the output is assumed to be at fault and the IC will not proceed with soft-start. Undervoltage protection may be caused by one of the following faults: * Output capacitor shorted to GND * Boost inductor or diode open * OVP sense resistor open After an Output UVP fault has been detected, the A8519 immediately shuts down but does not latch off. It will retry as soon as the UVP fault is removed. Figure 5: Detect Voltage is about 150 mV when LED Pin 2 is not Used In case of output capacitor shorted to GND fault, however, the high inrush current will also trip the Input OCP fault. This causes the IC to shut down and latch off. To enable the IC again, the PWM pin must be pulled low for at least 32,750 clock cycles (about 16 ms at 2 MHz), then pulled high again. 13 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver 2.2 Soft-Start Function The soft-start process is completed when any one of the following conditions is met: 1. All LED currents have reached their regulation targets, 2. Output voltage has reached 93% of its OVP threshold, or 3. Soft-start ramp time (tSS) has expired. Frequency Selection 2.0 1.8 1.6 Frequency in MHz During startup, the A8519 ramps up its boost output voltage following a fixed ramp function. This technique limits the input inrush current and ensures the same startup time regardless of the PWM duty cycle. 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 70 80 90 100 110 Resistance in k Figure 8: Switching Frequency versus RFSET Resistor Synchronization The A8519 can also be synchronized using an external clock. At power-up, if the FSET pin is held low, the IC will not power-up. Only when the FSET pin is tri-stated to allow for the pin to rise to about 1 V, or when a sync clock is detected, the A8519 will try to power up. The basic requirement of the sync signal is 150 ns minimum on-time and 150 ns minimum off-time as dictated by the requirements of pulse-width on- and off-times. Pulse Width Sync On Time Figure 7: Startup Diagram Showing the Input Current, Output Voltage, Total LED Current, and Switch Node Voltage 154 ns 150 ns The switching frequency on the boost regulator is set by a single resistor connected to the FSET pin. The switching frequency can be can be anywhere from 200 kHz to 2.15 MHz. Figure 8 shows typical switching frequency in MHz for a given resistor value (in k). The following equation can also be used to determine typical switching frequency from FSET resistance: fSW = 21.4/RFSET + 0.008 where fSW is in MHz, RFSET is in k. If a fault occurs during operation that will increase the switching frequency, the FSET pin is clamped to a maximum switching frequency of no more than 3.5 MHz. If the FSET pin is shorted to GND, the part will shut down. For more details, see the Fault Mode table on page 25. 150 ns Pulse Width Sync Off Time T = 454 ns Figure 9: Sync Pulse On- and Off-Time Requirements Figure 9 shows timing for a synchronization clock into the A8519 at 2.2 MHz. Any pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to synchronize the IC. Table 3 summarizes the duty cycle range at various synchronization frequencies. 14 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Table 3: Sync Pulse Duty Cycle Range for Selected Switching Frequencies. Sync Pulse Frequency Duty Cycle Range 2.2 MHz 33% to 66% 2 MHz 30% to 70% 1 MHz 15% to 85% 600 kHz 9% to 91% 300 kHz 4.5% to 95.5% Suppose the A8519 is started up with a valid external SYNC signal, but the SYNC signal is lost during normal operation. In that case, one of the following happens: * If the external SYNC signal is high impedance (open), the A8519 continues normal operation after approximately 5 s, at the switching frequency set by RFSET. No FAULT flag is generated. * If the external SYNC signal is stuck low (shorted to ground), the A8519 will detect an FSET-shorted-to-GND fault. The FAULT pin is pulled low after approximately 10 s, and switching is disabled. Once the FSET pin is released or SYNC signal is detected again, the A8519 will proceed to soft-start. To prevent generating a fault when the external SYNC signal is stuck at low, the circuit shown in Figure 12 can be used. When the external SYNC signal goes low, the A8519 will continue to operate normally at the switching frequency set by the RFSET. No FAULT flag is generated. A8519 External Synchronization Signal FSET 220 pF Figure 10: Synchronized FSET Pin and Switch Node SW Voltage. Schottky Barrier Diode RFSET 10.2 k Figure 12: Countermeasure to Prevent External Sync Signal Stuck-at-Low Fault. Figure 11: Transition of the Switch Wave Form when the Sync Pulse is Detected. The A8519 is switching at 2 MHz, and the applied sync pulse is 1 MHz. The LED current does not show any variation while the frequency changeover occurs. 15 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver The following timing diagrams (not to scale) illustrate how the switching frequency of A8519 may be programmed. Case 1: Startup with internal oscillator (RFSET connected to FSET pin) Case 3: Operating with External Sync initially, then switches over to internal oscillator EN/ PWM EN/ PWM Ext_Sync / FSET 1 V VDD CLKOUT External Sync FSET Sync lost Internal oscillator 1V Remarks: 0V CLKOUT Switching frequency controlled by internal ocillator Remarks: * After the IC powers up, CLKOUT signal is generated by internal oscillator based on FSET pin current. * Duty cycle of CLKOUT is approximately 50%. * When boost switching is enable, it has the same frequency as CLKOUT but different duty cycle. Case 2: Startup with External Sync clock signal applied to FSET pin 2V Ext_Sync 0V * If the next rising edge of Ext_Sync failed to arrive within approximately 5 s, the IC switches over to internal oscillator mode. * This transition could happen during fault condition when Ext_Sync line is broken. It is not recommended as part of the normal operation. * DC-blocking capacitor is required (see Figure 12) to prevent Stuck-at-Low fault at FSET pin. Case 4: Operating with internal oscillator initially, then switches over to External Sync EN/ PWM Ext_Sync / FSET 1 V EN/ PWM CLKOUT VDD Internal oscillator CLKOUT Switching frequency controlled by external Sync signal Remarks: * Ext_Sync clock signal should be applied before EN/PWM pin goes High. * After the IC powers up, CLKOUT signal is controlled by Ext_Sync. * CLKOUT generates a fixed negative pulse of 200 ns following each rising edge of Ext_Sync. Its duty cycle varies with external frequency. External Sync Remarks: * This transition could happen during fault condition when Ext_Sync line is intermittent. It is not recommended as part of the normal operation. * DC-blocking capacitor is required (see Figure 12) to prevent Stuck-at-Low fault at FSET pin. * Make sure the first Ext_Sync rising edge and the PWM rising edge do not coincide within a 500 ns window. 16 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Case 5: Operating with Ext_Sync1 initially, then switches over to Ext_Sync2 EN/ PWM 500 ns Ext_Sync / FSET 1 V External Sync1 transition External Sync2 External Sync1 transition Remarks: * Irregular clock pulses may occur during transition between two external sync frequencies. * Ensure the transition takes place at least 500 ns after the previous PWM = H rising edge. * Alternatively, execute the switchover during PWM = L only. 17 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver LED Current Setting and LED Dimming The maximum LED current can be up to 100 mA per channel, and is set through the ISET pin. Connect a resistor, RISET, between this pin and GND. To set ILED calculate RISET as follows: ILED = ISET x AISET ISET = RISET = VISET RISET (VISET x AISET ) ILED This sets the maximum current through the LEDs, referred to as the 100% current. Table 4: LED Current Setting Resistors (Values Rounded to the Nearest Standard Resistor Value) Standard Closest RISET Resistor Values LED Current ILED 7.15 k 100 mA per LED 8.87 k 80 mA per LED 11.8 k 60 mA per LED 14.3 k 50 mA per LED 17.8 k 40 mA per LED where ILED current is in A and RISET is in . Figure 13: Typical PWM Diagram Showing VOUT, ILED and COMP Pin, as well as the PWM Signal. (PWM dimming Frequency is 500 Hz 50% duty cyle.) Figure 14: Typical PWM Diagram Showing VOUT, ILED, and COMP Pin, as well as the PWM Signal. (PWM dimming frequency is 500 Hz 1% duty cycle.) 18 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver PWM Dimming The LED current can be reduced from the 100% current level by PWM dimming using the PWM pin. When the PWM pin is pulled high, the A8519 turns on and all enabled LEDs sink 100% current. When PWM is pulled low, the boost converter and LED sinks are turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. The typical PWM dimming frequencies fall between 200 Hz and 1 kHz. The A8519 is designed to deliver a maximum dimming ratio of 10,000:1 at PWM frequency of 100 Hz. That means a minimum PWM duty cycle of 0.01%, or an on-time of just 1 s out of a period of 10 ms. High-PWM dimming ratio is acheived by regulating the output voltage during PWM off-time. The VOUT pin samples the output Figure 15: Rising Edge PWM Signal to Total LED Current ILED(TOTAL) Turn-On Delay; Time base = 100 ns voltage during PWM on-time and regulates it during off-time. A hysteresis control loop brings VOUT higher by approximately 350 mV (150 mV for A8519-1) whenever it drops below the target voltage. In a highly noisy switching environment, it is necessary to insert an RC filter at the VOUT pin. A typical value of R = 10 k and C = 47 pF is recommended. Another important feature of the A8519 is the PWM signal to LED current delay. This delay is typically less than 500 ns, which allows for greater LED current accuracy at low-PWM dimming duty cycles. The error introduced by LED turn-on delay is partially offset by LED turn-off delay. Therefore, a PWM pulse width of under 1 s is still feasible, but the percentage error of LED current will increase with narrower pulse width. Figure 16: Falling Edge PWM Signal to Total LED Current ILED(TOTAL) Turn-Off Delay; Time base = 100 ns 19 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver APWM Pin 100 90 Normalized LED Current (%) The APWM pin is used in conjunction with the ISET pin (see Figure 17). This is a digital signal pin that internally adjusts the IISET current. The typical input signal frequency is between 40 kHz and 1 MHz. The duty cycle of this signal is inversely proportional to the percentage of current that is delivered to the LED (see Figure 18). As an example, a system that delivers ILED(TOTAL) = 240 mA would deliver ILED(TOTAL) = 180 mA when an APWM signal with a duty cycle of 25% is applied. When this pin is not used it should be tied to AGND. 80 70 60 50 40 30 20 10 0 APWM 0 10 20 30 40 50 60 70 80 90 100 APWM Duty Cycle (%) ISET ISET Current Mirror Figure 18: Normalized LED Current vs. APWM Duty Cycle VIN = 9 V, VOUT = ~22 V, RISET = 24 k, APWM = 200 kHz APWM ISET Current Adjust Block RISET PWM LED Driver LED Current Error (% of full scale) 5 4 3 Figure 17: Simplified Block Diagram of APWM ISET Block To use the APWM pin as a trim function, the user should set the maximum output current to a value higher than the desired current by at least 5%. The LED IISET current is then trimmed down to the appropriate desired value. Another consideration is the limitation of the APWM signal's duty cycle. In some cases, it might be more desirable to set the maximum IISET current to be 25% to 50% higher, thus allowing the APWM signal to have duty cycles that are between 25% and 50%. 2 1 0 0 10 20 30 40 50 60 70 80 90 100 APWM Duty Cycle (%) Figure 19: Error in LED Current vs. APWM Duty Cycle VIN = 9 V, VOUT = ~22 V, RISET = 24 k, APWM = 200 kHz 20 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Figure 22: Transition of output current level when a 50% duty cycle APWM signal is applied to the APWM pin, in conjunction with 50% duty cycle applied to the PWM pin. Figure 20: Transition of Total LED Current from 240 mA to 180 mA, when a 25% APWM signal is applied to the APWM pin. (Dimming PWM = 100%) Extending LED Dimming Ratio The dynamic range of LED brightness can be further extended by using a combination of PWM duty cycle, APWM duty cycle, and analog dimming method. For example, the following approach can be used to achieve a 50,000:1 dimming ratio at 200 Hz PWM frequency: Figure 21: Transition of Total LED Current from 180 mA to 240 mA, when a 25% APWM stops being applied to the APWM pin. (Dimming PWM = 100%) Although the APWM dimming function has a wide frequency range, if used strictly as an analog dimming function, it is recommended to use frequency ranges between 50 and 500 kHz for best accuracy. The frequency range needs to be considered only if the user is not using APWM as a closed-loop trim function. It takes about 1 millisecond to change the actual LED current due to propagation delay between the APWM signal and the ILED(TOTAL). * Vary PWM duty cycle from 100% down to 0.02% to give 5,000:1 dimming. * With PWM duty cycle at 0.02%, vary APWM duty from 0% to 90% to reduce LED current down to 10%. This gives a net effect of 50,000:1 dimming. Analog Dimming Besides using APWM signal, the LED current can also be reduced by using an external DAC or another voltage source. Connect RISET between the DAC output and the ISET pin. The limit of this type of dimming is dependant of the range of the ISET pin. In the case of the A8519, the limit is 20 to 144 A. 21 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver The LED current can be adjusted using the following formula: RISET VDAC ISET DAC or Voltage Source A8519 AGND Simplified Diagram of Voltage LED Current Control GND GND Figure 23: Typical Application Circuit Using a DAC to Control the LED Current in the A8519 The ISET current is controlled by the following formula: VISET - VDAC IISET = RISET where VISET is the ISET pin voltage and VDAC is the DAC output voltage. When the DAC voltage is 0 V, the LED current will be at its maximum. To keep the internal gain amplifier stable, do not decrease the current through the RISET resistor to less than 20 A. IISET = VISET V - VISET - DAC R1 RISET where VISET is the ISET pin voltage and VDAC is the DAC output voltage. When VDAC is equal to 1 V, the output is strictly controlled by the RISET resistor. When VDAC is higher than 1 V, the LED current is reduced. When VDAC is lower that 1 V, the LED current is increased. LED String Short Detect All LEDx pins are capable of handling the maximum VOUT that the converter can deliver, thus allowing for LEDx pin to VOUT protection in case of a connector short. In case some of the LEDs in an LED string are shorted, the voltage at the corresponding LEDx pin will increase. Any LEDx pin that has a voltage exceeding VLEDx(SC) will be removed from operation. This will prevent the IC from dissipating too much power by having a large voltage present on an LEDx pin. Below is a typical application circuit using a DAC to control the LED current using a two-resistor configuration. The advantage of this circuit is that the DAC voltage can be higher or lower, thus adjusting the LED current to a higher or lower value of the preset LED current set by the RISET resistor. R1 ISET VDAC A8519 DAC R ISET AGND GND Simplified Diagram of Voltage LED Current Control GND Figure 25: Disabling of LED1 String when the LED1 Pin Voltage is Increased Above 4.6 V Figure 24: Typical Application Circuit Using a DAC and RISET Resistor to Control the LED Current in the A8519 22 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver While the IC is being PWM dimmed, the IC will recheck the disabled LED every time the PWM signal goes high to prevent false tripping of LED short. This also allows for some self-correction if an intermittent LED pin short-to-VOUT is present. At least one LED must be in regulation for the LED string shortdetect protection to activate. In case all of the LED pins are above regulation voltage (this could happen when the input voltage rises too high for the LED strings), they will continue to operate normally. Overvoltage Protection The A8519 has output overvoltage protection (OVP) and open Schottky diode protection (secondary OVP). The OVP pin has a threshold level of 8.3 V typical. A resistor can be used to set the output overvoltage protection threshold up to 40 V approximately. This is sufficient for driving 11 white LED in series. The formula for calculating the OVP resistor is shown below: ROVP = (VOVP - VOVP(th) ) IOVP(th) where VOVP(th) = 8.3 V typical and IOVP(th) = 200 A typical. The OVP function is not a latched fault. If the OVP condition occurs during a load dump, the IC will stop switching but not shut down. Figure 26: Output of A8519 when Disconnected from Load During Normal Operation Figure 27 illustrates a typical OVP condition caused by an open LED string. Once OVP is detected, the boost stops switching, and the open LED string is removed from operation. Afterwards, VOUT is allowed to fall, the boost will resume switching, and the A8519 will resume normal operation. There are several possibilities why an OVP condition is encountered during operation, the two most common being an open LED string and a disconnected output condition. Figure 26 illustrates when the output of the A8519 is disconnected from load during normal operation. The output voltage instantly increases up to OVP voltage level, and then the boost stops switching to prevent damage to the IC. When the output voltage decreases to a low value, the boost converter will begin switching. If the condition that caused the OV event still exists, OVP will be triggered again. Figure 27: Typical OVP Condition Caused by an Open LED String 23 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver The A8519 also has built-in secondary overvoltage protection to protect the internal switch in the event of an open-diode condition. Open Schottky diode detection is implemented by detecting overvoltage on the SW pin of the device. If voltage on the SW pin exceeds the device's safe operating voltage rating, the A8519 disables and remains latched. To clear this fault, the IC must be shut down by either using the PWM signal or by going below the UVLO threshold on the VIN pin. Boost Switch Overcurrent Protection The boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3 A. Figure 29 illustrates the normal operation of the switch node (VSW), inductor current, and output voltage (VOUT) for a 11x4 LED configuration. Figure 28 illustrates open Schottky diode protection while the IC is in normal operation. As soon as the switch node voltage (VSW) exceeds 48 V, the IC will shut down. Due to small delays in the detection circuit, as well as there being no load present, the switch node voltage (VSW) will rise above the trip point voltage. Figure 29: Normal Operation of Switch Node (VSW), Inductor Current, and Output Voltage (VOUT) Figure 30 shows the cycle-by-cycle current limit showing inductor current as a green trace. Note the inductor current is truncated and as a result the output voltage is reduced as compared to normal operation shown for the 11x4 LED configuration. Figure 28: Open Schottky Diode Protection When enabling the A8519 into an open-diode condition, the IC will first go through all of its initial LED detection and will then check the boost output voltage. At that point, the open diode is detected. Figure 30: Cycle-by-Cycle Current Limit 24 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver There is also a secondary current limit (ISW(LIM2)) that is sensed through the boost switch. This current limit, once detected, immediately shuts down the A8519. The level of this current limit is set above the cycle-by-cycle current limit to protect the switch from destructive currents when boost inductor is shorted. Figure 31 shows the secondary boost switch OCP. Once this limit is reached, the A8519 will immediately shut down. Input Overcurrent Protection and Disconnect Switch The primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. If the input current level goes above the preset current limit threshold, the part will be shut down in less than 3 s--this is a latched condition. The fault flag is also set low to indicate a fault. This protection feature prevents catastrophic failure in the system due to a short of the inductor, inductor short to GND, or short at the output GND. Figure 33 illustrates the typical input overcurrent fault condition. As soon as input OCP limit is reached, the part disables the gate of the disconnect switch Q1. Figure 31: Secondary Boost Switch OCP VIN RSC Q1 Radj To L1 CG Iadj VSENSE GND VIN GATE A8519 Figure 33: Startup into Output Shorted to GND fault. Input OCP tripped at 4 A (RSC = 0.024 W, Radj =383 ) During startup when Q1 first turns on, an inrush current flows through Q1 into the output capacitance. If Q1 turns on too fast (due to its low gate capacitance), the inrush current may trip input OCP limit. In this case, an external gate capacitance CG is added to slow down the turn-on transition. Typical value for CG is around 4.7 to 22 nF. Do not make CG too large, since it also slows down the turn-off transient during a real input OCP fault. Figure 32: Typical Circuit Showing Implementation of Input Disconnect Feature 25 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Setting the Current Sense Resistor VDD As shown in Figure 32: The VDD pin provides regulated bias supply for internal circuits. Connect a capacitor with a value of 1 F or greater to this pin. The internal LDO can deliver no more than 2 mA of current with a typical VDD voltage of about 3.5 V, enabling this pin to serve as the pull-up voltage for the fault pin. VIN - VSENSE = VSC + Iadj x Radj or ISC = ((VIN - VSENSE) - Iadj x Radj)/RSC where VSC = the voltage drop across RSC. The typical threshold for the current sense is VIN - VSENSE = 110 mV when Radj is 0 . The A8519 can have this voltage trimmed using the Radj resistor. It is recommended to set trip point to be above 3.65 A to avoid conflicts with the cycle-by-cycle current limit typical threshold. A sample calculation is done below for 4.25 A of input current. Calculated max value of sense resistor RSC = 0.11 V / 4.25 A = 0.0259 . The RSC chosen is 0.024 , a standard value. Therefore, the voltage drop across RSC is: VSC = 4.25 Ax 0.024 = 0.102 V Radj = Radj = Shutdown If PWM pin is pulled low for more than tPWML (32,750 clock cycles), the device enters shutdown mode and clears all internal fault registers. As an example, at 2 MHz clock frequency, it will take approximately 16.3 ms to shut down the IC into the low power mode. When shut down, the IC will disable all current sources and wait until the PWM goes high to re-enable the IC. Figure 35 depicts the shutdown using the PWM enable, showing the 16.3 ms delay between PWM signal and when the VDD and GATE of disconnect switch turn off. VVSENSE(trip) - VSC Iadj 0.11 V - 0.102 V = 372 21.5 A Input UVLO When VIN and VSENSE rise above VUVLOrise threshold, the A8519 is enabled. The A8519 is disabled when VIN falls below VUVLOfall threshold for more than 50 s. This small delay is used to avoid shutting down because of momentary glitches in the input power supply. Figure 34 illustrates a shutdown due to a falling input voltage (VIN). When VIN falls below 3.90 V, the IC will shut down. Figure 35: Shutdown Using the PWM Enable Figure 34: Shutdown with Falling Input Voltage 26 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Dithering Feature To minimize the switching frequency harmonics, a dithering feature is implemented in A8519. This feature simplifies the input filters needed to meet the automotive CISPR 25 conducted and radiated emission limits. The dithering sweep is internally set at 5%. The switching frequency will ramp from 0.95 times the programmed frequency to 1.05 times the programmed frequency. The rate or modulation at which the frequency sweeps is governed by an internal 12.5 kHz triangle pattern. Figure 38: Output Voltage Ripple Frequency Due to Dithering = 12.4 kHz at VIN = 12 V, and PWM Ratio = 100% Figure 36: Minimum Dithering Switching Frequency = 2.02 MHz at VIN = 12 V, and PWM Ratio = 100% Figure 39: Output Voltage Ripple Amplitude Due to Dithering = 100 mV at VIN = 12 V, and PWM Ratio = 100% Figure 37: Maximum Dithering Switching Frequency = 2.23 MHz at VIN = 12 V, and PWM Ratio = 100% 27 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Fault Protection During Operation The A8519 series devices constantly monitor the state of the system to determine if any fault conditions occur during normal operation. The response to a triggered fault condition is summarized in the table below. There are several points at which the A8519 monitors for faults during operation. The locations are input current, switch current, output voltage, switch voltage, and LED pins. (Note: Some protection features might not be active during startup to prevent false triggering of fault conditions.) The detectable fault conditions are: * Open LED pin * Shorted LED pin to GND * Open or shorted inductor * Open or shorted boost diode * Shorted inductor * VOUT short to GND * SW pin shorted to GND * ISET pin shorted to GND * Input disconnect switch source shorted to GND Note: Some faults will not be protected if the input disconnect switch is not used. An example of this is VOUT short to GND. 28 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Table 5: Fault Mode Table Fault Name Type Primary Switch Overcurrent Protection (cycleby-cycle current limit) Autorestart Secondary Switch Current Limit Input Disconnect Current Limit Secondary OVP LEDx Pin Short Protection Latched Latched Latched Autorestart LEDx Pin Open Autorestart ISET Short Protection Autorestart FSET Short Protection Autorestart Overvoltage Protection Autorestart Active Always Always Always Always Startup Normal operation Always Always Always Fault Flag Set Description Boost Disconnect Switch LED Sink Drivers NO This fault condition is triggered when the SW current exceeds the cycle-by-cycle current limit, ISW(LIM).The present SW on-time is truncated immediately to limit the current. Next switching cycle starts normally. Off for a single cycle ON ON YES When current through boost switch exceeds secondary SW current limit (ISW(LIM2)), the device immediately shuts down the disconnect switch, LED drivers, and boost. The Fault flag is set. To re-enable the part, the PWM pin needs to be pulled low for 32,750 clock cycles. OFF OFF OFF YES The device is immediately shut off if the voltage across the input sense resistor is above the VVSENSE(trip) threshold. To re-enable the device, the PWM pin must be pulled low for 32,750 clock cycles. OFF OFF OFF YES Secondary overvoltage protection is used for open-diode detection. When diode D1 opens, the SW pin voltage will increase until VOVP(sec) is reached . This fault latches the IC. The input disconnect switch is disabled as well as the LED drivers. To re-enable the part, the PWM pin needs to be pulled low for 32,750 clock cycles. OFF OFF OFF NO This fault prevents the part from starting up if any of the LED pins are shorted. The part stops soft-start from starting while any of the LED pins are determined to be shorted. Once the short is removed, soft-start is allowed to start. OFF ON OFF NO When an LED pin is open, the device will determine which LED pin is open by increasing the output voltage until OVP is reached. Any LED string not in regulation will be turned OFF. The device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. ON ON OFF for open pins, ON for all others NO Fault occurs when the IISET current goes above 150% of max current. The boost will stop switching and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to regulate to the preset LED current. OFF ON OFF YES Fault occurs when the FSET current goes above 150% of max current. The boost will stop switching, Disconnect switch will turn off, and the IC will disable the LED sinks until the fault is removed. When the fault is removed, the IC will try to restart with soft-start. OFF OFF OFF NO Fault occurs when OVP pin exceeds VOVP(th) threshold. The IC will immediately stop switching to try to reduce the output voltage. If the output voltage decreases, then the IC will restart switching to regulate the output voltage. STOP during OVP event ON ON 29 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Fault Name Type Active Fault Flag Set Boost Disconnect Switch LED Sink Drivers Undervoltage Protection Autorestart Always YES Device immediately shuts off boost and current sinks if the voltage at OVP pin is below VUVP(th). It will autorestart once the fault is removed. OFF ON OFF LED String Short Detection Autorestart Always NO Fault occurs when the LED pin voltage exceeds 5.2 V. Once the LED string short fault is detected, the LED string above the threshold will be removed from operation. ON ON OFF for shorted pins, ON for all others Overtemperature Protection Autorestart Always YES Fault occurs when the die temperature exceeds the overtemperature threshold, typically 170C. OFF OFF OFF VIN UVLO Autorestart Always NO Fault occurs when VIN drops below VUVLOfall, typically below 3.9 V. This fault resets all latched faults. OFF OFF OFF Description 30 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver APPLICATION INFORMATION Design Example This section provides a method for selecting component values when designing an application using the A8519. Assumptions: For the purposes of this example, the following are given as the application requirements: * VIN: 10 to 14 V * Quantity of LED channels, #CHANNELS: 4 * Quantity of series LEDs per channel, #SERIESLEDS: 10 * LED current per channel, ILED: 60 mA * LED Vf at 60 mA: 3.2 V * fSW: 2 MHz * PWM dimming frequency 200 Hz, 1% duty cycle (VOUT(ovp) - VOVP(th) ) IOVP(th) Where both IOVP(th) and VOVP(th) values are from the datasheet's Electrical Characteristics table. 37.85 - 8.3 0.2 ROVP = 147.75 k ROVP = Step 1: Connect LED strings to pins LED1, LED2, LED3, and LED4. Step 2: Determine the LED current set resistor RISET RISET = RISET = (VISET x AISET) ILED (1.017 x 710) = 12 k 0.06 A RISET = 11.8 k An 11.8 k resistor was chosen. Step 3a: Determining the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. The first step is to determine the maximum voltage based on the LED requirements. The regulation voltage for an LED pin (VLEDx) of the A8519 is 850 mV. A 5 V headroom is added to give margin to the design due to noise and output voltage ripple. VOUT(ovp) = #SERIESLEDs x Vf + VLED + 5 V VOUT(ovp) = 10 x 3.2 V + 0.850 V + 5 V VOUT(ovp) = 37.85 V The OVP resistor is: ROVP = Choose a value of resistor that is higher value than the calculated ROVP. In this case, a value of 158 k was selected. Below is the actual value of the minimum OVP trip level with the selected resistor. VOUT(ovp) = 158 k x 0.2 mA + 8.3 V VOUT(ovp) = 39.9 V Step 3b: At this point, a quick check needs to be done to see if the conversion ratio is adequate for the selected frequency. Where VD is the boost diode forward voltage, minimum off-time (tSW(off)) is found in the datasheet: DMAX(boost) = 1 - tSW(off)x fSW(max) DMAX(boost) = 1 - (85 ns x 2.2 MHz) = 0.813 Theoretical Max VOUT = VIN(min) 1 - DMAX(boost) - VD VD is the voltage drop of the boost diode. Theoretical Max VOUT = 10 V 1 - 0.813 - 0.4 = 53.1 V Theoretical Max VOUT value needs to greater than the value VOUT(ovp). If this is not the case, the switching frequency of the boost converter is going to have to be reduced to meet the maximum duty cycle requirements. Step 4: Inductor selection. The inductor needs to be chosen such that it can handle the necessary input current. In most applications, due to stringent EMI requirements, the system needs to operate in continues conduction mode throughout the whole input voltage range. 31 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Step 4a: Determine the Duty Cycle. DMAX = 1 - DMAX = 1 - IL = IIN(max) x K ripple VIN(min) (VOUT(ovp) + VD ) 10 (39.9 + 0.4) = 0.75 Step 4b: Determine the maximum and minimum input current to the system. The minimum input current will dictate the inductor value. The maximum current rating will dictate the current rating of the inductor. IIN(max) = (VIN(min) x DMAX ) IL x fSW ) 10 V L= x 0.75 = 11.79 H 0.318 A x 2 MHz L= Double-check to make sure that 1/2 current ripple is less than IIN(min). IIN(min) > 1/2 DIL VOUT(ovp) x IOUT VIN(min) x IOUT = #Channels x I LED IOUT = 4 x 0.060 A = 0.240 A A good approximation of efficiency can be taken from the efficiency curves located on page 10. A value of 90% is a good starting approximation. 39.9 V x 240 mA IIN(max) = = 1.06 A 10 V x 0.90 V x IOUT IIN(max) = OUT VIN(max) x VOUT = 10 x 3.2 V + 0.85 V = 32.85 V IIN(min) = IL = 1.06 A x 0.3 = 0.318 A 32.85 V x 240 mA = 0.625 A 14 V x 0.90 Step 4c: Determining the inductor value. To ensure that the inductor operates in continuous conduction mode, the value of the inductor needs to be set such that the 1/2 inductor ripple current is not greater than the average minimum input current. A first pass calculation for Kripple should be 30% of the maximum inductor current. 0.625 A > 0.159 A A good inductor value to use would be 10 H. Step 4d: This step is used to verify that there is sufficient slope compensation for the inductor chosen. 6 A/s slope compensation value is applied inside the IC at 2 MHz switching frequency. The slope compensation at any switching frequency can be determined by the following formula: Slope Comp = 6 A/s x fSW 2 x 10 6 Next, insert the inductor value used in the design: IL(used) = IL(used) = VIN(min) x DMAX L(used) x fSW 10 V x 0.75 = 0.375 A 10 H x 2 MHz Required Min Slope = IL(used) x S x 10 -6 1 x (1 - DMAX ) fSW where S is taken from the following formula: S = 1 - 0.18 DMAX S = 0.76 Required Min Slope = 0.375 x 0.76 x 10 = 2.28 A/s 1 x (1 - 0.75) 2 MHz -6 32 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver If the required minimum slope is larger than the calculated slope compensation, the inductor value needs to be increased. Note that the slope compensation value is in A/s the 1 x 10-6 is constant multiplier. 200 Hz; the minimum duty cycle is 0.02%. Typically, the voltage variation on the output during PWM dimming needs to be less than 250 mV (VCOUT) so there is no audible hum. COUT = ILK x Step 4e: Determining the inductor current rating. IL(min) = IIN(max) + (1/2) x IL IL(min) = 1.06 A + 0.375 A = 1.25 A 2 (1 - minimum dimming duty cycles) PWM dimming frequency x VCOUT The selected diode leakage current at a 150C junction temperature and 30 V output is 100 A, and the maximum leakage current through OVP pin is 1 A. The total leakage current can be calculated as follows: Step 5: To determine the resistor value for a switching frequency refer to the graph in Figure 8. A 10 k resistor will result in a 2 MHz switching frequency. ILK = ILKG(diode) + ILKG(ovp) Step 6: Choosing the proper output Schottky diode. The diode needs to be chosen for three characteristics when it is used in LED lighting circuitry. The most obvious two are the current rating of the diode and the reverse voltage rating. The reverse voltage rating should be larger than the maximum output VOVP . The peak current through the diode is: = 101 A ID(pk) = IIN(max) + ID(pk) = 1.06 + IL(used) 2 0.375 A = 1.25 A 2 The other major factor in deciding the switching diode is the reverse current characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time, the boost converter is not switching. This results in a slow bleeding off of the output voltage due to leakage currents. IR or reverse current can be a large contributor especially at high temperatures. The reverse current of the selected diode varies between 1 and 100 A. For higher efficiency, use a small forward voltage drop diode. For lower high-frequency noise, choose a small junction capacitor diode. Step 7: Choosing the output capacitors. The output capacitors need to be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factor that contributes to the size of the output capacitor is PWM dimming frequency and the PWM duty cycle. Another major contributor is leakage current (ILK). This current is the combination of the OVP current sense as well as the reverse current of the boost diode. In this design, the PWM dimming frequency is = 100 A + 1 A COUT = 101 A x (1 - 0.02) = 2 F 200 Hz x 0.250 V A capacitor larger than 2 F should be selected. Due to degradation of capacitance at dc voltages, a 4.7 F / 50 V capacitor is a good choice. Vendor Value Part Number Murata 4.7 F / 50 V GRM21BC18H475KE11K It is also necessary to note that if a high dimming ratio of 5000:1 must be maintained at lower input voltages, then larger output capacitors will be needed. 4 x 4.7 F / 50 V / X6S / 0805 capacitors are chosen; 0805 size is selected to minimize possible audible noise. The RMS current through the capacitor is given by: COUT(rms) = IOUT x COUT(rms) = 0.240 x IL(used) IIN(max) x 12 1 - DMAX DMAX + 0.375 1.06 x 12 = 0.424 A 1 - 0.75 0.75 + The output capacitor needs to have a current rating of at least 0.424 A. The capacitors selected in this design, 4 x 4.7 F / 50 V / X6S / 0805, have a combined current rating of more than 3 A current rating. 33 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Step 8: Selection of input capacitor. The input capacitor needs to be selected such that it provides good filtering of the input voltage waveform. A good rule of thumb is to set the input voltage ripple VIN to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: IL(used) CIN = 8 x f SW x VIN CIN = CIN(rms) = (1 - D MAX )x 12 Step 9: Choosing the input disconnect switch components. Set the input disconnect current limit to 4.25 A. RSC = 0.375 A = 0.234 F 8 x 2 MHz x 0.1 V IL(used) IOUT x I IN(max) larger input capacitor. A larger input capacitor is also required to have stable input voltage during line transients. Combinations of aluminum electrolytic and ceramic capacitors can be used. 0.11 V = 0.0259 4.25 A The RSC chosen is 0.024 ohms. Therefore, the voltage drop across RSC is: VSC = 4.25 Ax 0.024 = 0.102 V = 0.1 A 0.375 A 0.240 A x 1.06 A CIN(rms) = = 0.1 A (1 - 0.75) x 12 A good ceramic input capacitor with ratings of 50 V / 2.2 F or 50 V / 4.7 F will suffice for this application. Vendor Value Part Number Murata 4.7 F / 50 V GRM32ER71H475KA88L Murata 2.2 F / 50 V GRM31CR71H225KA88L If long wires are used for the input, it is necessary to use a much Radj = Radj = VVSENSE(trip) - VSC Iadj 0.11 V - 0.102 V = 372 21.5 A A value of 383 was chosen for this design. The disconnect switch Q1 works as on or off. Therefore, the Radj value is not really critical. For the input disconnect switch, an AO4421 6.2 A / 60 V P-channel MOSFET is selected. To achieve proper operation at low dimming ratios, connect an RC filter to the VOUT pin. Use R = 10 k and C = 47 pF. 34 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver *optional VIN = (4.5 to 40) V 10 H VOUT > VIN 0.024 47 F Electrolytic 383 Q1 10 k 158 k 2.2 F 47 pF GATE VSENSE 10 F 10 F SW VOUT VIN 1 F VDD OVP VDD LED1 A8519 10 k FAULT LED2 LED3 PWM LED4 APWM CLKOUT ISET FSET AGND PGND COMP 100 pF 11.8 k 10 k 280 68 nF GND Figure 40: Schematic Showing Calculated Values from the Design Example Above 35 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver PACKAGE OUTLINE DRAWINGS For Reference Only - Not for Tooling Use (Reference MO-153 ACT) Dimensions in millimeters - NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 6.50 0.10 0.45 4.20 8 0 0.65 20 20 0.20 0.09 1.70 C 3.00 4.40 0.10 6.40 0.20 3.00 6.10 0.60 0.15 A 1.00 REF 1 2 1 2 0.25 BSC 20X C 0.10 1.20 MAX C 4.20 SEATING PLANE GAUGE PLANE B SEATING PLANE 0.30 0.19 PCB Layout Reference View 0.65 BSC 0.15 0.00 A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C Exposed thermal pad (bottom surface) D Branding scale and appearance at supplier discretion NNNNNNN YYWW LLLLLLL 1 D Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Lot number Figure 41: Package LP: 20-Pin, 0.65 mm Pin Pitch TSSOP with Exposed Thermal Pad 36 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver For Reference Only - Not for Tooling Use (Reference JEDEC MO-220VHHD-1) Dimensions in millimeters - NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 5.00 0.10 0.50 0.28 28 28 1.35 1 2 1 A 3.17 5.00 0.10 5.05 3.17 29X C D 0.08 5.05 0.90 0.10 C C SEATING PLANE 0.25 +0.05 -0.07 PCB Layout Reference View 0.50 3.15 0.55 +0.20 -0.10 B 3.15 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 2 1 28 Figure 42: Package ET: 28-Pin QFN with Exposed Thermal Pad 37 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A8519 and A8519-1 Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver Revision History Number Date Description - September 10, 2014 1 October 24, 2014 2 March 18, 2015 3 May 19, 2015 Added A8519-1 variant. 4 June 10, 2015 Fixed typo on page 2; revised FSET pin voltage typical spec. 5 November 4, 2015 6 January 8, 2016 Amended "Powering Up: Boost Output Undervoltage Protection" (page 13) 7 October 24, 2016 Updated Input Overcurrent Protection and Disconnect Switch section (page 22) 8 December 21, 2018 9 January 23, 2019 10 March 14, 2019 Initial Release Lowered minimum fSW (when using RFSET) to 200 kHz and SYNC down to 260 kHz. Revised OVP Thresholds and Oscillator Frequencies. Amended "Enabling the IC" (page 12) and "Synchronization" (page 15) of Functional Description; inserted Figures 18 and 19; updated Selection Guide table (page 2); corrected 2nd Typical Application Drawing (page 9) Increased minimum external SYNC frequency to 320 kHz Added timing diagrams to illustrate all possible cases to program the switching frequency (page 16); Corrected Fault table for FAULT flag behavior during Overtemperature Protection (page 29) Added Case 5 to Synchronization section (page 17) Copyright 2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com 38 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com