DESCRIPTION
The A8519 is a multi-output LED driver for small-size LCD
backlighting. It integrates a current-mode boost converter
with internal power switch and four current sinks. The boost
converter can drive up to 44 white LEDs, 11 LED per string, at
100 mA. The LED sinks can be paralleled together to achieve
higher LED currents up to 400 mA. The A8519 operates from
a single power supply from 4.5 to 40 V, which allows the part
to withstand load dump conditions encountered in automotive
systems.
The A8519 can control LED brightness through a digital
(PWM) signal. An LED brightness contrast ratio of 10,000:1
can be achieved using PWM dimming at 100 Hz; a higher ratio
of 100,000:1 is possible when using a combination of PWM
and analog dimming.
If required, the A8519 can drive an external P-channel
MOSFET to disconnect input supply from the system in the
event of a fault. The A8519 provides protection against output
short, overvoltage, open or shorted diode, open or shorted
LED pin, and overtemperature. A cycle-by-cycle current limit
protects the internal boost switch against high-current overloads.
A8519-DS, Rev. 10
MCO-0000554
FEATURES AND BENEFITS
• Automotive AEC-Q100 qualified
• Fully integrated 42 V MOSFET for boost converter
• Fully integrated LED current sinks
• Withstands surge input up to 40 VIN for load dump
• Operates down to 3.9 VIN (max) for idle stop
• Drives four strings of LEDs
• Maximum output voltage 40 V
Up to 11 white LEDs in series
• Drive current for each string is 100 mA
• Programmable boost switching frequency (200 kHz to
2.15 MHz)
• Synchronized boost switching frequency option (320 kHz
to 2.3 MHz)
• Dithering of boost switching frequency to reduce EMI
• Extremely high LED contrast ratio
10,000:1 using PWM dimming alone
100,000:1 when combining PWM and analog dimming
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
PACKAGES:
Typical Application Diagram
Not to scale
A8519 and A8519-1
Continued on the next page…
Continued on the next page…
V> V
OUT IN
C
IN
C
OUT1
C
OUT2
C
VDD
R
PU
C
P
L1
Q1 D1
R
ADJ
R
SC
Optional
C
Z
R
Z
R
ISET
V
IN
APWM
AGND
GND
PGND
VDD
R
OVP
V
C
PWM
LED4
LED1
OVP
VIN
GATE SW VOUT
FAULT
VSENSE
R
FSET
CLKOUT
ISET FSET
A8519
LED2
LED3
COMP
Typical Application Circuit Showing VOUT-to-Ground Short Protection Using Optional P-Channel MOSFET
APPLICATIONS:
• Automotive infotainment backlighting
• Automotive cluster
• Automotive center stack
28-Pin QFN with Exposed
Thermal Pad (suffix ET)
20-Pin TSSOP with Exposed
Thermal Pad (suffix LP)
March 14, 2019
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS [2]
Characteristic Symbol Notes Rating Unit
LEDx Pins VLEDx x = 1, 2, 3, or 4 –0.3 to 40 V
OVP Pin VOVP –0.3 to 40 V
VIN, VOUT Pins VIN, VOUT –0.3 to 40 V
VSENSE, GATE Pins VSENSE, VGATE VIN –7.4 to VIN +0.4 V
SW Pin [3] VSW
Continuous –0.6 to 42 V
t < 50 ns –1 to 48 V
FAULT Pin VFAULT –0.3 to 40 V
APWM, PWM, CLKOUT, COMP,
FSET, ISET, VDD Pins –0.3 to 5.5 V
Operating Ambient Temperature TAK temperature range –40 to 125 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
[2] Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is
not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
[3] SW DMOS is self-protecting and will conduct when VSW exceeds 48 V.
The A8519 has a synchronization pin that allows boost switching
frequencies to be synchronized in the range of 320 kHz to 2.3 MHz.
The high switching frequency allows the converter to operate above the
AM radio band. The IC contains a clock output pin that allows other
converters to be synchronized to the A8519’s boost switching frequency.
The A8519 employs hysteresis control to help regulate the LED
current at extremely short PWM on-time. The A8519-1 is identical
to the A8519, except that it uses a smaller hysteresis window to
reduce output voltage ripple during PWM dimming.
• Excellent input voltage transient response at lowest PWM duty cycle
• Gate driver for optional P-channel MOSFET input disconnect switch
• LED current accuracy 0.7%
• LED string current-matching accuracy 0.8%
• Protection against:
Shorted boost switch, inductor or output capacitor
Shorted FSET or ISET resistor
Open or shorted LED pins and LED strings
Open boost diode
Overtemperature
FEATURES AND BENEFITS (CONTINUED) DESCRIPTION (CONTINUED)
SELECTION GUIDE
Part Number
Operating Ambient
Temperature Range
TA (°C)
Hysteresis
Window Package Packaging [1] Leadframe
Plating
A8519KLPTR-T –40 to 125 350 mV 20-pin TSSOP with exposed thermal pad 4000 pieces per reel 100% matte tin
A8519KETTR-R –40 to 125 350 mV 28-pin 5 × 5 mm QFN with exposed ther-
mal pad and sidewall plated 1500 pieces per reel 100% matte tin
A8519KLPTR-T-1 –40 to 125 150 mV 20-pin TSSOP with exposed thermal pad 4000 pieces per reel 100% matte tin
A8519KETTR-R-1 –40 to 125 150 mV 28-pin 5 × 5 mm QFN with exposed ther-
mal pad and sidewall plated 1500 pieces per reel 100% matte tin
[1] Contact Allegro for additional packing options.
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information.
Characteristic Symbol Test Conditions [1] Value Unit
Package Thermal Resistance RθJA
LP Package on 2-layer 3 in2 PCB 40 °C/W
ET Package on 2-layer 3 in2 PCB Contact factory °C/W
LP Package on 4-layer PCB Based on JEDEC Standards 29 °C/W
ET Package on 4-layer PCB Based on JEDEC Standards 32 °C/W
[1] Additional thermal information available on the Allegro website.
Table of Contents
Features and Benefits ........................................................... 1
Description .......................................................................... 1
Applications ......................................................................... 1
Packages ............................................................................ 1
Typical Application Diagram ................................................... 1
Specifications ...................................................................... 2
Selection Guide ................................................................ 2
Absolute Maximum Ratings ................................................ 2
Thermal Characteristics ..................................................... 3
Functional Block Diagram ..................................................... 4
Pinout Diagrams and Terminal List ......................................... 5
Electrical Characteristics ....................................................... 6
Characteristic Performance ................................................. 10
Functional Description ........................................................ 12
Enabling the IC ............................................................... 12
Powering Up: LED Pin Check ........................................... 12
Powering Up: Boost Output Undervoltage Protection ........... 13
Soft-Start Function .......................................................... 14
Frequency Selection ........................................................ 14
Synchronization .............................................................. 14
LED Current Setting and LED Dimming ............................. 18
PWM Dimming ............................................................... 19
APWM Pin ..................................................................... 20
Extending LED Dimming Ratio.......................................... 21
Analog Dimming ............................................................. 21
LED String Short Detect ................................................... 22
Overvoltage Protection .................................................... 23
Boost Switch Overcurrent Protection ................................. 24
Input Overcurrent Protection and Disconnect Switch ........... 25
Setting the Current Sense Resistor ................................... 26
Input UVLO .................................................................... 26
VDD .............................................................................. 26
Shutdown....................................................................... 26
Dithering Feature ............................................................ 27
Fault Protection During Operation ..................................... 28
Application Information ....................................................... 31
Design Example ............................................................. 31
Package Outline Drawings .................................................. 36
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram
Fault
Block
ISET
Block
Gate
Off
LED
Driver
Block
Diode Open
Sense
TSD
OVP2 VOUT
OVP
Enable
Block
PWM
Block
Regulator
UVLO Block
Input Current
Sense
Amplifier
GATE
PWM
VSENSE
VIN
Vin
AGND
AGND
AGND
SWFSET
AGND
1.235 V
Reference
NMOS
Driver
Driver
Circuit
Internal Soft
Start Block
VOUT Hyst.
Control
OVP
Sense
Open/Short
LED Detect
Oscillator
Internal
V
CC
Internal V
CC
Frequency
Dithering
LED1
LED2
LED3
LED4
APWM
ISET
AGND
V
REF
V
REF
VDD
I
ADJ
AGND
FAULT
PGND
PGND
COMP
CLKOUT
+
–
+
–
+
–
+
–
OCP2
Current
Sense
Error
Amplifier
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PINOUT DIAGRAMS
Terminal List Table
Pin Number Name Function
LP ET
1 18 COMP Output of the error amplifier and compensation node. Connect an Rz-Cz-Cp network from this pin to GND
for control loop compensation.
2 19, 20, 21 PGND Power ground for internal N-channel MOSFET switching device. Connect to PCB ground plane.
3 22 OVP Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection level.
4 23 VOUT Connect directly to boost output voltage.
5 25, 26 SW The drain of the internal N-channel MOSFET switching device of the boost converter.
6 27 GATE Output gate driver pin for external P-channel MOSFET control.
7 28 VSENSE Connect this pin to the negative sense side of the current sense resistor Rsc. The threshold voltage is
measured as VIN-VSENSE. There is also fixed current sink to allow for trip threshold adjustment.
8 1 VIN Input power to the IC as well as the positive input used for current sense resistor.
9 3 FAULT The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 100 kW
resistor between this pin and desired logic level voltage.
10 4 CLKOUT Logic output representing the switching frequency of internal boost oscillator. This allows other converters to
be synchronized to the same frequency (with the same frequency dithering, if applicable)
11 5 VDD Output of internal LDO (bias regulator). Connect a 1 μF decoupling capacitor between this pin and GND.
12 6 APWM Analog trimming option or dimming. Applying a digital PWM signal to this pin adjusts the internal IISET current.
13 7 PWM Enables the IC when this pin is pulled high. Also serves to control the LED intensity by using pulse-width
modulation. Typical PWM dimming frequency is in the range of 100 to 400 Hz.
14 8 FSET
Frequency/synchronization pin. A resistor RFSET from this pin to GND sets the switching frequency (with
dithering superimposed). It can also be used to synchronize two or more converters in the system to an
external frequency between 320 kHz and 2.3 MHz (dithering is disabled in this case).
15 9 ISET Connect RISET resistor between this pin and GND to set the desired LED current setting.
16 10, 11 AGND LED current ground. Connect to PCB ground plane.
17, 18,
19, 20
13, 14,
15, 16 LED 1-4 LED current sinks #1 to 4. Connect the cathode of each LED string to associated pin. Unused LED pin must
be terminated to GND through a 3.09 kΩ resistor.
–2, 12,
17, 24 NC No connect. Leave open or connect to GND.
– – PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the
ground plane(s) of the PCB with at least 8 vias, directly in the pad.
1
COMP LED4
2
PGND LED3
3
OVP LED2
4
VOUT LED1
5
SW AGND
6
GATE ISET
7
VSENSE FSET
8
VIN PWM
9
FAULT APWM
10
CLKOUT VDD
PAD
11
12
13
14
15
16
17
18
19
20
2
VIN
3
FAULT
4
CLKOUT
5
VDD
6
APWM
7
PWM
8FSET
9ISET
10
AGND
11
AGND
12NC
13LED1
14LED2
15 LED3
16 LED4
17 NC
NC
18 COMP
19 PGND
20 PGND
21 PGND
22 OVP
23 VOUT
24 NC
25 SW
26 SW
27
28
GATE
1
VSENSE
28-Pin QFN with Exposed Thermal Pad (suffix ET)
20-Pin TSSOP with Exposed Thermal Pad (suffix LP)
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25°C; ● indicates
specifications guaranteed over the full operating temperature range with TA = TJ = -40°C to 125°C; typical specifications are at TA = 25°C
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
INPUT VOLTAGE
Input Voltage Range [3] VIN ●4.5 – 40 V
UVLO Start Threshold VUVLOrise VIN rising ●– – 4.35 V
UVLO Stop Threshold VUVLOfall VIN falling ●– – 3.9 V
UVLO Hysteresis VUVLOHYS 300 450 600 mV
INPUT SUPPLY CURRENT
Input Quiescent Current IQVPWM = VIH, fSW = 2 MHz ●– 8 15 mA
Input Sleep Supply Current ISLEEP VIN = 16 V, VPWM = VSYNC = 0 V ●– 2.0 10 µA
INPUT LOGIC LEVELS (PWM, APWM)
Input Logic Level Low VIL ●– – 0.4 V
Input Logic Level High VIH ●1.5 – – V
PWM Input Pull-Down Resistor REN VPWM = 5 V 60 100 140 kΩ
APWM Input Pull-Down Resistor RAPWM VPWM = VIH 60 100 140 kΩ
APWM
APWM Frequency [2] fAPWM ●40 – 1000 kHz
OUTPUT LOGIC LEVELS (CLKOUT)
Output Logic Level Low VOL 5 V < VIN < 40 V ●– – 0.3 V
Output Logic Level High VOH 5 V < VIN < 40 V ●1.8 – – V
ERROR AMPLIFIER
Source Current IEA(source) VCOMP = 1.5 V – –600 – μA
Sink Current IEA(sink) VCOMP = 1.5 V – +600 – μA
COMP Pin Pull-Down Resistance RCOMP FAULT = 0, VCOMP = 1.5V – 1.4 – kΩ
OVERVOLTAGE PROTECTION
OVP Pin Voltage Threshold VOVP(th) OVP pin connected to VOUT ●7 8.3 9.5 V
OVP Pin Sense Current Threshold IOVP(th) Current into OVP pin ●190 200 210 μA
OVP Pin Leakage Current IOVP(LKG) VIN = 16 V, PWM = L ●– 0.1 1 μA
OVP Accuracy – – 5 %
Undervoltage Protection Threshold VUVP(th)
Measured at VOUT pin when ROVP = 160 kW [2] – 3 – V
Measured at VOUT pin when ROVP = 0 – 0.55 0.7 V
Secondary Overvoltage Protection VOVP(sec) Measured at SW pin ●42 45 48 V
Continued on the next page…
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking).
[2] Ensured by design and characterization, not production tested.
[3] Minimum VIN = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to VIN = 3.9 V
[4] LED current is trimmed to cancel variations in both Gain and ISET voltage
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
BOOST SWITCH
Switch On-Resistance RSW ISW = 0.75 A, VIN = 16 V ●100 250 500 mΩ
Switch Leakage Current ISW(LKG) VSW = 16 V, VPWM = VIL ●– 0.1 1 μA
Switch Current Limit ISW(LIM) ●3 3.65 4.5 A
Secondary Switch Current Limit [2] ISW(LIM2)
Higher than max ISW(LIM) under all conditions
part latches when detected – 4.9 – A
Minimum Switch On-Time tSW(on) ●45 65 85 ns
Minimum Switch Off-Time tSW(off) ●– 65 85 ns
OSCILLATOR FREQUENCY
Oscillator Frequency [5] fSW
RFSET = 10 kΩ ● 1.95 2.15 2.35 MHz
RFSET = 21.5 kΩ ● 0.9 1 1.1 MHz
RFSET = 110 kΩ – 200 – kHz
Oscillator Frequency Dithering Range fSW_DITH RFSET = 10 kΩ – ±5 – %
Dithering Modulation Frequency fSW_MOD RFSET = 10 kΩ – 12.5 – kHz
FSET Pin Voltage VFSET
A8519, RFSET = 10 kΩ – 1.02 – V
A8519-1, RFSET = 10 kΩ – 1.07 – V
SYNCHRONIZATION
Sync Input Logic Level VSYNCL FSET pin logic Low ●– – 0.4 V
VSYNCH FSET pin logic High ●2 – – V
Synchronized Switching Frequency fSW(sync) ●320 – 2300 kHz
Synchronization Input Min. Off-Time tSYNC(off) ●150 – – ns
Synchronization Input Min. On-Time tSYNC(on) ●150 – – ns
LED CURRENT SINKS
LEDx Accuracy [4] ErrLED RISET = 8.33 kW●– 0.7 3 %
LEDx Matching ΔLEDx IISET = 120 µA ●– 0.8 2 %
LEDx Regulation Voltage VLEDx
VLED1 = VLED2 = VLED3 = VLED4,
IISET = 120 µA ●750 850 975 mV
ISET to ILEDx Current Gain AISET IISET = 120 µA ●696 710 727 A/A
ISET Pin Voltage VISET 0.987 1.017 1.047 V
Allowable ISET Current IISET ●20 – 144 µA
VLEDx Short detect VLEDx(SC)
While LED sinks are in regulation; sensed from
VLEDx to AGND ●4.7 5.2 5.7 V
LED Startup Ramp Time [2] tSS
Time duration before all LED channels come
into regulation, or OVP is tripped – 20 – ms
ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25°C; ● indicates
specifications guaranteed over the full operating temperature range with TA = TJ = -40°C to 125°C; typical specifications are at TA = 25°C
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking).
[2] Ensured by design and characterization, not production tested.
[3] Minimum VIN = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to VIN = 3.9 V
[4] LED current is trimmed to cancel variations in both Gain and ISET voltage
[5] fSW measurements were taken with dithering function is disabled.
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PWM DIMMING
Maximum PWM Dimming Until Off-
Time [2] tPWML
Measured while PWM = low, during dimming
control and internal references are powered on
(exceeding tPWML results in shutdown)
– 32750 – fSW
cycles
Minimum PWM On-Time tPWMH(min1)
First cycle when powering up IC (VPWM = 0 to
3.3 V) ●– 0.75 2 µs
tPWMH(min) Subsequent PWM pulses ●– 0.5 1 µs
PWM High to LED On Delay td(PWMon)
Time between PWM going high and when LED
current reaches 90% of maximum (VPWM = 0 to
3.3 V)
●– 0.2 0.5 µs
PWM Low to LED Off Delay td(PWMoff)
Time between PWM going low and when LED
current reaches 10% of maximum (VPWM = 3.3
to 0 V)
●– 0.36 0.5 µs
HYSTERESIS CONTROL
Hysteresis Window (A8519) VHYST Measured at VOUT pin when PWM = H to L – 0.35 – V
Hysteresis Window (A8519-1) VHYST1 Measured at VOUT pin when PWM = H to L – 0.15 – V
GATE PIN
Gate Pin Sink Current IG(sink) VGATE = VIN, no input OCP fault – –113 – μA
Gate Pin Source Current IG(source) VGATE = VIN – 6 V, input OCP fault tripped – 6 – mA
Gate Shutdown Delay When
Overcurrent Fault Is Tripped [2] tFAULT VIN – VSENSE = 200 mV, monitored at FAULT pin – – 3 µs
Gate Voltage VGATE
Measured between GATE and VIN when gate
is on – –6.7 – V
VSENSE PIN
VSENSE Pin Sink Current IVSENSE ●17.2 21.5 25.8 µA
VSENSE Trip Point VSENSE(trip) Measured between VIN and VSENSE, Radj = 0 ●95 110 125 mV
FAULT PIN
FAULT Pull-Down Voltage VFAULT IFAULT = 1 mA – – 0.5 V
FAULT Pin Leakage Current IFAULT(lkg) VFAULT = 5 V – – 1 µA
THERMAL PROTECTION (TSD)
Thermal Shutdown Threshold [2] TSD Temperature rising 155 170 – °C
Thermal Shutdown Hysteresis [2] TSD(hys) – 20 – °C
ELECTRICAL CHARACTERISTICS [1]: Unless otherwise specified, specifications are valid at VIN = 16 V, TA = 25°C; ● indicates
specifications guaranteed over the full operating temperature range with TA = TJ = -40°C to 125°C; typical specifications are at TA = 25°C
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking).
[2] Ensured by design and characterization, not production tested.
[3] Minimum VIN = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to VIN = 3.9 V
[4] LED current is trimmed to cancel variations in both Gain and ISET voltage
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
V> V
OUT IN
CIN
COUT1 COUT2
CVDD
RPU
CP
L1
Q1 D1
RADJ
RSC
Optional
CZ
RZ
RISET
VIN
APWM
AGND
GND
PGND
VDD
ROVP
VC
PWM
LED4
LED1
OVP
VIN
GATE SW VOUT
FAULT
VSENSE
RFSET
CLKOUT
ISET FSET
A8519 LED2
LED3
COMP
C
IN
C
OUT
C
VDD
R
PU
C
P
L1
R1*
C
SW
L2
D2
D2*
C
Z
R
Z
R
ISET
V
IN
APWM
*Notes:
Input disconnect switch is not necessary in this
case to protect against VOUT-to-ground short.
R1 and D2 are used to provide a leakage path
so the OVPpin is above 100 mV during startup.
Otherwise, the IC would assume an VOUT-to-GN
D
short and not proceed with soft start.
AGND
GND
PGND
VDD
R
OVP
V
C
PWM
LED4
LED1
OVP
VIN
GATE SW VOUT
FAULT
VSENSE
Output: 3 WLED in series
(~10 V)
R
FSET
CLKOUT
ISET FSET
LED2
LED3
COMP
A8519
Typical Application Showing Boost Configuration with Input Disconnect Switch to Protect Against VOUT-to-Ground Short
Typical Application Showing SEPIC Configuration for Flexible Input/Output Voltage Ratio
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE
8
80.00
81.00
82.00
83.00
84.00
85.00
86.00
87.00
88.00
89.00
10 12 14 16
10 × 4 LE
D
9 × 4 LED
8 × 4 LED
7 × 4 LED
Eff
%
Efficiency at 60 mA/Channel for Various LED Configurations
V(V)
IN
Efficiency Measurement
A8519 Evaluation Board Efficiency versus Input Voltage while
Disconnect Switch and Snubber Circuit are Used
0.1
78.00
80.00
82.00
84.00
86.00
88.00
90.00
92.00
0.2 0.3 0.4
10 × 4 LE
D
9 × 4 LED
8 × 4 LED
7 × 4 LED
Eff
%
Efficiency at V= 12 V for Various LED Configurations
IN
Total LED Current (A)
A8519 Evaluation Board Efficiency versus Total LED Current while
Disconnect Switch and Snubber Circuit are Used
Startup Waveforms
Start up at 100% PWM Dimming, VIN = 7 V, 4 Channels,
10 LEDs/Channel, 60 mA/Channel; Time base = 10 ms/Div
Start up at 0.02% PWM Dimming, VIN = 7 V, 4 Channels,
10 LEDs/Channel, 60 mA/Channel; Time base = 10 ms/Div
Higher efficiency can be achieved by:
• Using an inductor with low DCR.
• Using lower forward voltage drop and smaller junction
capacitance Schottky diode.
• Removing the snubber circuit; however, this might
compromise the EMI performance.
• Shorting out the disconnect switch and the input current sense
resistor; however, this will eliminate the output short-to-GND
protection feature.
• Lowering switching frequency. This will significantly improve
the efficiency; however, to avoid the EMI AM band limits,
careful switching frequency selection is required. In addition,
a larger inductor will be needed.
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Transient Response to Step Change in PWM Dimming
From PWM = 0.1% to PWM = 100% at 4 Channels,
60 mA/Channel, VIN = 12 V; Time base = 50 ms/Div
From PWM = 100% to PWM = 0.1% at 4 Channels,
60 mA/Channel, VIN = 12 V; Time base = 50 ms/Div
Transient Response to Step Change in VIN Voltage
From VIN = 16 V to VIN = 5.5 V, 4 Channels, 60 mA/Channel,
PWM = 100%; Time base = 50 ms/Div
From VIN = 5.5 V to VIN = 16 V, 4 Channels, 60 mA/Channel,
PWM = 100%; Time base = 50 ms/Div
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A8519 and
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Enabling the IC
The IC turns on when a logic high signal is applied on the
PWM pin with a minimum duration of tPWMH for the first clock
cycle, and the input voltage present on the VIN pin is greater
than 4.35 V to clear the UVLO threshold. Before the LEDs are
enabled, the A8519 driver goes through a system check to see
if there are any possible fault conditions that might prevent the
system from functioning correctly. Also if the FSET pin is pulled
low the IC will not power up. More information on the FSET pin
can be found in the Synchronization section of the datasheet.
FUNCTIONAL DESCRIPTION
Figure 1: Power Up Diagram Showing PWM, ISET, and VDD
Voltages and Total LED Current
Figure 2: Power Up Diagram Showing Disconnect VGATE, VLED1,
VISET, and VPWM During LED Pins Detect and Regulation Period
3.09 k3.09 k3.09 k
Use LED1 Channel Only Use Four LED Channels
AGND
GND
AGND
GND
LED2 LED2
LED3 LED3
LED4 LED4
LED1 LED1
LED Strings
LED String
Figure 3: Channel Select Setup
When the voltage threshold on VLEDx pins exceeds 120 mV, a
delay between 3000 and 4000 clock cycles (1.5 to 2 ms) is used
to determine the status of the pins.
Table 1: LED Detection Duration for Given Switching Frequency
Switching Frequency Detection Time
2 MHz 1.5 to 2 ms
1 MHz 3 to 4 ms
800 kHz 3.75 to 5 ms
600 kHz 5 to 6.7 ms
All unused LED pins should be connected with a 3.09 kΩ resis-
tor to GND. The unused pin, with the pull-down resistor, will be
taken out of regulation at this point and will not contribute to the
boost regulation loop.
Once the IC is enabled, there are only two ways to shut down the
IC into low-power mode:
1. Pull PWM pin to low for at least 32,750 clock cycles
(approximately 16 ms at 2 MHz).
2. Cut off the supply and allow VIN to drop below UVLO fall-
ing threshold (less than 3.9 V).
Powering Up: LED Pin Check
Once VIN pin goes above UVLO and a high signal is present
on the PWM pin, the IC proceeds to power up. The A8519 then
enables the disconnect switch (GATE) and checks to see if the
LED pins are shorted to ground and/or are not used. The LED
detect phase starts when the GATE voltage of the disconnect
switch is equal to VIN – 3.3 V.
Figure 2 shows the relation of LEDx pins with respect to the
gate voltage of the disconnect switch (if used) during LED detect
phase, as well as the duration of the LED detect for a switching
frequency of 2 MHz.
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Table 2: LED Detection Voltage Thresholds
LED Pin Voltage
Level LED Pin Action
Less than 70 mV Indicates a short to
PCB GND
A8519 will not
proceed with power
up.
150 mV Not used
LED string connected
with the unused LED
pin is removed from
operation
325 mV LED pin in use None
Figure 4: LED String Detect Occurs when All LED Strings are
Selected to be Used
Figure 5: Detect Voltage is about 150 mV when LED Pin 2 is not
Used
If an LED pin is shorted to ground, the A8519 will not proceed
with soft-start until the short is removed from the LED pin. This
prevents the A8519 from powering up and putting an uncon-
trolled amount of current through the LEDs.
Figure 6: One LED Pin is Shorted to GND.
The IC will not proceed with power up until LED pin is released, at
which point the LED pin is checked to see if it is used.
Powering Up: Boost Output Undervoltage Protection
During startup, after the input disconnect switch has been
enabled, the output voltage is checked through the OVP pin. If
the sensed voltage does not rise above VUVP(th), the output is
assumed to be at fault and the IC will not proceed with soft-start.
Undervoltage protection may be caused by one of the following
faults:
• Output capacitor shorted to GND
• Boost inductor or diode open
• OVP sense resistor open
After an Output UVP fault has been detected, the A8519 immedi-
ately shuts down but does not latch off. It will retry as soon as the
UVP fault is removed.
In case of output capacitor shorted to GND fault, however, the
high inrush current will also trip the Input OCP fault. This causes
the IC to shut down and latch off. To enable the IC again, the
PWM pin must be pulled low for at least 32,750 clock cycles
(about 16 ms at 2 MHz), then pulled high again.
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Soft-Start Function
During startup, the A8519 ramps up its boost output voltage
following a fixed ramp function. This technique limits the input
inrush current and ensures the same startup time regardless of the
PWM duty cycle.
The soft-start process is completed when any one of the follow-
ing conditions is met:
1. All LED currents have reached their regulation targets,
2. Output voltage has reached 93% of its OVP threshold, or
3. Soft-start ramp time (tSS) has expired.
Frequency Selection
Figure 7: Startup Diagram Showing the Input Current, Output
Voltage, Total LED Current, and Switch Node Voltage
Synchronization
The A8519 can also be synchronized using an external clock. At
power-up, if the FSET pin is held low, the IC will not power-up.
Only when the FSET pin is tri-stated to allow for the pin to rise
to about 1 V, or when a sync clock is detected, the A8519 will try
to power up. The basic requirement of the sync signal is 150 ns
minimum on-time and 150 ns minimum off-time as dictated by
the requirements of pulse-width on- and off-times.
Figure 9 shows timing for a synchronization clock into the A8519
at 2.2 MHz.
Any pulse with a duty cycle of 33% to 66% at 2.2 MHz can be
used to synchronize the IC. Table 3 summarizes the duty cycle
range at various synchronization frequencies.
Figure 8: Switching Frequency versus RFSET Resistor
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
01020 30 40 50 60 70 80 90 100 110
Resistance in kΩ
Frequency in MHz
Figure 9: Sync Pulse On- and Off-Time Requirements
Pulse Width
Sync On Time
Pulse Width
Sync OffTime
150 ns
150 ns
154 ns
T= 454 ns
The switching frequency on the boost regulator is set by a single
resistor connected to the FSET pin. The switching frequency can
be can be anywhere from 200 kHz to 2.15 MHz. Figure 8 shows
typical switching frequency in MHz for a given resistor value (in
kΩ). The following equation can also be used to determine typi-
cal switching frequency from FSET resistance:
fSW = 21.4/RFSET + 0.008
where fSW is in MHz, RFSET is in kΩ.
If a fault occurs during operation that will increase the switch-
ing frequency, the FSET pin is clamped to a maximum switching
frequency of no more than 3.5 MHz. If the FSET pin is shorted
to GND, the part will shut down. For more details, see the Fault
Mode table on page 25.
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Table 3: Sync Pulse Duty Cycle Range for Selected Switch-
ing Frequencies.
Sync Pulse Frequency Duty Cycle Range
2.2 MHz 33% to 66%
2 MHz 30% to 70%
1 MHz 15% to 85%
600 kHz 9% to 91%
300 kHz 4.5% to 95.5%
Figure 10: Synchronized FSET Pin and Switch Node SW Voltage.
Figure 11: Transition of the Switch Wave Form when the Sync
Pulse is Detected. The A8519 is switching at 2 MHz, and the
applied sync pulse is 1 MHz. The LED current does not show any
variation while the frequency changeover occurs.
Suppose the A8519 is started up with a valid external SYNC sig-
nal, but the SYNC signal is lost during normal operation. In that
case, one of the following happens:
• If the external SYNC signal is high impedance (open), the
A8519 continues normal operation after approximately 5 µs,
at the switching frequency set by RFSET. No FAULT flag is
generated.
• If the external SYNC signal is stuck low (shorted to ground),
the A8519 will detect an FSET-shorted-to-GND fault. The
FAULT pin is pulled low after approximately 10 µs, and
switching is disabled. Once the FSET pin is released or
SYNC signal is detected again, the A8519 will proceed to
soft-start.
To prevent generating a fault when the external SYNC signal is
stuck at low, the circuit shown in Figure 12 can be used. When
the external SYNC signal goes low, the A8519 will continue to
operate normally at the switching frequency set by the RFSET. No
FAULT flag is generated.
A8519
Schottky
Barrier
Diode
FSET
RFSET
10.2 kΩ
220 pF
External
Synchronization
Signal
Figure 12: Countermeasure to Prevent External Sync Signal
Stuck-at-Low Fault.
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The following timing diagrams (not to scale) illustrate how the
switching frequency of A8519 may be programmed.
Case 1: Startup with internal oscillator (RFSET con-
nected to FSET pin)
EN/
PWM
VDD
FSET
CLKOUT
1 V
0 V
Switching frequency controlled by internal ocillator
Remarks:
• After the IC powers up, CLKOUT signal is generated by
internal oscillator based on FSET pin current.
• Duty cycle of CLKOUT is approximately 50%.
• When boost switching is enable, it has the same frequency as
CLKOUT but different duty cycle.
Case 2: Startup with External Sync clock signal applied
to FSET pin
EN/
PWM
VDD
Ext_Sync
CLKOUT
2 V
0 V
Switching frequency controlled by external Sync signal
Remarks:
• Ext_Sync clock signal should be applied before EN/PWM pin
goes High.
• After the IC powers up, CLKOUT signal is controlled by
Ext_Sync.
• CLKOUT generates a fixed negative pulse of 200 ns following
each rising edge of Ext_Sync. Its duty cycle varies with
external frequency.
Case 3: Operating with External Sync initially, then
switches over to internal oscillator
EN/
PWM
Ext_Sync
/ FSET
CLKOUT
1 V
Internal oscillatorExternal Sync Sync lost
Remarks:
• If the next rising edge of Ext_Sync failed to arrive within
approximately 5 µs, the IC switches over to internal oscillator
mode.
• This transition could happen during fault condition when
Ext_Sync line is broken. It is not recommended as part of the
normal operation.
• DC-blocking capacitor is required (see Figure 12) to prevent
Stuck-at-Low fault at FSET pin.
Case 4: Operating with internal oscillator initially, then
switches over to External Sync
EN/
PWM
Ext_Sync
/ FSET
CLKOUT
1 V
Internal oscillator External Sync
Remarks:
• This transition could happen during fault condition when
Ext_Sync line is intermittent. It is not recommended as part of
the normal operation.
• DC-blocking capacitor is required (see Figure 12) to prevent
Stuck-at-Low fault at FSET pin.
• Make sure the first Ext_Sync rising edge and the PWM rising
edge do not coincide within a 500 ns window.
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Case 5: Operating with Ext_Sync1 initially, then
switches over to Ext_Sync2
EN/
PWM
Ext_Sync
/ FSET 1 V
External Sync1 External Sync2
500 ns
External Sync1
transition transition
Remarks:
• Irregular clock pulses may occur during transition between
two external sync frequencies.
• Ensure the transition takes place at least 500 ns after the
previous PWM = H rising edge.
• Alternatively, execute the switchover during PWM = L only.
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This sets the maximum current through the LEDs, referred to as
the 100% current.
Table 4: LED Current Setting Resistors (Values Rounded to the
Nearest Standard Resistor Value)
Standard Closest RISET Resistor
Values
LED Current
ILED
7.15 kΩ 100 mA per LED
8.87 kΩ 80 mA per LED
11.8 kΩ 60 mA per LED
14.3 kΩ 50 mA per LED
17.8 kΩ 40 mA per LED
Figure 13: Typical PWM Diagram Showing VOUT, ILED and COMP
Pin, as well as the PWM Signal. (PWM dimming Frequency is
500 Hz 50% duty cyle.)
Figure 14: Typical PWM Diagram Showing VOUT, ILED, and COMP
Pin, as well as the PWM Signal. (PWM dimming frequency is
500 Hz 1% duty cycle.)
LED Current Setting and LED Dimming
The maximum LED current can be up to 100 mA per chan-
nel, and is set through the ISET pin. Connect a resistor, RISET,
between this pin and GND. To set ILED calculate RISET as fol-
lows:
I = I × A
LED SET ISET
I =
SET RISET
VISET
R =
ISET
(V × A )
ISET ISET
ILED
where ILED current is in A and RISET is in Ω.
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PWM Dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the PWM pin. When the PWM pin is
pulled high, the A8519 turns on and all enabled LEDs sink 100%
current. When PWM is pulled low, the boost converter and LED
sinks are turned off. The compensation (COMP) pin is floated,
and critical internal circuits are kept active. The typical PWM
dimming frequencies fall between 200 Hz and 1 kHz.
The A8519 is designed to deliver a maximum dimming ratio of
10,000:1 at PWM frequency of 100 Hz. That means a minimum
PWM duty cycle of 0.01%, or an on-time of just 1 µs out of a
period of 10 ms.
High-PWM dimming ratio is acheived by regulating the output
voltage during PWM off-time. The VOUT pin samples the output
voltage during PWM on-time and regulates it during off-time. A
hysteresis control loop brings VOUT higher by approximately
350 mV (150 mV for A8519-1) whenever it drops below the
target voltage. In a highly noisy switching environment, it is
necessary to insert an RC filter at the VOUT pin. A typical value
of R = 10 kΩ and C = 47 pF is recommended.
Another important feature of the A8519 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows for greater LED current accuracy at low-PWM dimming
duty cycles.
The error introduced by LED turn-on delay is partially offset by
LED turn-off delay. Therefore, a PWM pulse width of under 1
μs is still feasible, but the percentage error of LED current will
increase with narrower pulse width.
Figure 15: Rising Edge PWM Signal to Total LED Current
ILED(TOTAL) Turn-On Delay; Time base = 100 ns
Figure 16: Falling Edge PWM Signal to Total LED Current
ILED(TOTAL) Turn-Off Delay; Time base = 100 ns
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The APWM pin is used in conjunction with the ISET pin (see
Figure 17). This is a digital signal pin that internally adjusts the
IISET current. The typical input signal frequency is between
40 kHz and 1 MHz. The duty cycle of this signal is inversely
proportional to the percentage of current that is delivered to
the LED (see Figure 18). As an example, a system that delivers
ILED(TOTAL) = 240 mA would deliver ILED(TOTAL) = 180 mA when
an APWM signal with a duty cycle of 25% is applied. When this
pin is not used it should be tied to AGND.
Figure 17: Simplified Block Diagram of APWM ISET Block
ISET
Current
Mirror
APWM ISET
Current
Adjust Block
PWM
APWM
ISET
RISET
LED Driver
APWM Pin
0
10
20
30
40
50
60
70
80
90
100
010203040506070809
01
00
Normalized LED Current (%)
APWM Duty Cycle (%)
Figure 18: Normalized LED Current vs. APWM Duty Cycle
VIN = 9 V, VOUT = ~22 V, RISET = 24 kΩ, APWM = 200 kHz
0
1
2
3
4
5
010203040506070809
01
00
LED Current Error (% of full scale)
APWM Duty Cycle (%)
Figure 19: Error in LED Current vs. APWM Duty Cycle
VIN = 9 V, VOUT = ~22 V, RISET = 24 kΩ, APWM = 200 kHz
To use the APWM pin as a trim function, the user should set
the maximum output current to a value higher than the desired
current by at least 5%. The LED IISET current is then trimmed
down to the appropriate desired value. Another consideration is
the limitation of the APWM signal’s duty cycle. In some cases, it
might be more desirable to set the maximum IISET current to be
25% to 50% higher, thus allowing the APWM signal to have duty
cycles that are between 25% and 50%.
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Figure 22: Transition of output current level when a 50% duty
cycle APWM signal is applied to the APWM pin, in conjunction
with 50% duty cycle applied to the PWM pin.
Extending LED Dimming Ratio
The dynamic range of LED brightness can be further extended by
using a combination of PWM duty cycle, APWM duty cycle, and
analog dimming method.
For example, the following approach can be used to achieve a
50,000:1 dimming ratio at 200 Hz PWM frequency:
• Vary PWM duty cycle from 100% down to 0.02% to give
5,000:1 dimming.
• With PWM duty cycle at 0.02%, vary APWM duty from 0%
to 90% to reduce LED current down to 10%. This gives a net
effect of 50,000:1 dimming.
Analog Dimming
Besides using APWM signal, the LED current can also be
reduced by using an external DAC or another voltage source.
Connect RISET between the DAC output and the ISET pin. The
limit of this type of dimming is dependant of the range of the
ISET pin. In the case of the A8519, the limit is 20 to 144 µA.
Figure 20: Transition of Total LED Current from 240 mA to
180 mA, when a 25% APWM signal is applied to the APWM pin.
(Dimming PWM = 100%)
Figure 21: Transition of Total LED Current from 180 mA to
240 mA, when a 25% APWM stops being applied to the APWM
pin. (Dimming PWM = 100%)
Although the APWM dimming function has a wide frequency
range, if used strictly as an analog dimming function, it is recom-
mended to use frequency ranges between 50 and 500 kHz for
best accuracy. The frequency range needs to be considered only
if the user is not using APWM as a closed-loop trim function.
It takes about 1 millisecond to change the actual LED current
due to propagation delay between the APWM signal and the
ILED(TOTAL).
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The LED current can be adjusted using the following formula:
where VISET is the ISET pin voltage and VDAC is the DAC output
voltage.
When VDAC is equal to 1 V, the output is strictly controlled by
the RISET resistor. When VDAC is higher than 1 V, the LED cur-
rent is reduced. When VDAC is lower that 1 V, the LED current is
increased.
LED String Short Detect
All LEDx pins are capable of handling the maximum VOUT that
the converter can deliver, thus allowing for LEDx pin to VOUT
protection in case of a connector short.
In case some of the LEDs in an LED string are shorted, the volt-
age at the corresponding LEDx pin will increase. Any LEDx pin
that has a voltage exceeding VLEDx(SC) will be removed from
operation. This will prevent the IC from dissipating too much
power by having a large voltage present on an LEDx pin.
I =
ISET
V
ISET
R
ISET
R1
–V – V
ISETDAC
Figure 25: Disabling of LED1 String when the LED1 Pin Voltage is
Increased Above 4.6 V
VDAC
R
ISET
ISET
A8519
DAC
or
Voltage Source
AGND
GND
GND
Simplified Diagram of
Voltage LED Current
Control
Figure 23: Typical Application Circuit Using a DAC to Control the
LED Current in the A8519
The ISET current is controlled by the following formula:
where VISET is the ISET pin voltage and VDAC is the DAC output
voltage.
When the DAC voltage is 0 V, the LED current will be at its max-
imum. To keep the internal gain amplifier stable, do not decrease
the current through the RISET resistor to less than 20 µA.
Below is a typical application circuit using a DAC to control the
LED current using a two-resistor configuration. The advantage of
this circuit is that the DAC voltage can be higher or lower, thus
adjusting the LED current to a higher or lower value of the preset
LED current set by the RISET resistor.
I =
ISET
R
ISET
V – V
ISET DAC
VDAC
R1
R
ISET
ISET
A8519
DAC
AGND
GNDGND Simplified Diagram of
Voltage LED Current
Control
Figure 24: Typical Application Circuit Using a DAC and RISET
Resistor to Control the LED Current in the A8519
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Figure 26: Output of A8519 when Disconnected from Load During
Normal Operation
Figure 27: Typical OVP Condition Caused by an Open LED String
Figure 27 illustrates a typical OVP condition caused by an open
LED string. Once OVP is detected, the boost stops switching,
and the open LED string is removed from operation. Afterwards,
VOUT is allowed to fall, the boost will resume switching, and the
A8519 will resume normal operation.
While the IC is being PWM dimmed, the IC will recheck the dis-
abled LED every time the PWM signal goes high to prevent false
tripping of LED short. This also allows for some self-correction if
an intermittent LED pin short-to-VOUT is present.
At least one LED must be in regulation for the LED string short-
detect protection to activate. In case all of the LED pins are above
regulation voltage (this could happen when the input voltage
rises too high for the LED strings), they will continue to operate
normally.
Overvoltage Protection
The A8519 has output overvoltage protection (OVP) and open
Schottky diode protection (secondary OVP). The OVP pin has
a threshold level of 8.3 V typical. A resistor can be used to set
the output overvoltage protection threshold up to 40 V approxi-
mately. This is sufficient for driving 11 white LED in series.
The formula for calculating the OVP resistor is shown below:
where VOVP(th) = 8.3 V typical and IOVP(th) = 200 µA typical.
The OVP function is not a latched fault. If the OVP condition
occurs during a load dump, the IC will stop switching but not
shut down.
There are several possibilities why an OVP condition is encoun-
tered during operation, the two most common being an open LED
string and a disconnected output condition.
Figure 26 illustrates when the output of the A8519 is discon-
nected from load during normal operation. The output voltage
instantly increases up to OVP voltage level, and then the boost
stops switching to prevent damage to the IC. When the output
voltage decreases to a low value, the boost converter will begin
switching. If the condition that caused the OV event still exists,
OVP will be triggered again.
R=
OVP
(V – V )
OVP OVP(th)
IOVP(th)
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Figure 30 shows the cycle-by-cycle current limit showing induc-
tor current as a green trace. Note the inductor current is truncated
and as a result the output voltage is reduced as compared to
normal operation shown for the 11×4 LED configuration.
Boost Switch Overcurrent Protection
The boost switch is protected with cycle-by-cycle current limit-
ing set at a minimum of 3 A. Figure 29 illustrates the normal
operation of the switch node (VSW), inductor current, and output
voltage (VOUT) for a 11×4 LED configuration.
Figure 29: Normal Operation of Switch Node (VSW), Inductor
Current, and Output Voltage (VOUT)
Figure 30: Cycle-by-Cycle Current Limit
The A8519 also has built-in secondary overvoltage protection to
protect the internal switch in the event of an open-diode condi-
tion. Open Schottky diode detection is implemented by detecting
overvoltage on the SW pin of the device. If voltage on the SW
pin exceeds the device’s safe operating voltage rating, the A8519
disables and remains latched. To clear this fault, the IC must be
shut down by either using the PWM signal or by going below the
UVLO threshold on the VIN pin.
Figure 28 illustrates open Schottky diode protection while the
IC is in normal operation. As soon as the switch node voltage
(VSW) exceeds 48 V, the IC will shut down. Due to small delays
in the detection circuit, as well as there being no load present, the
switch node voltage (VSW) will rise above the trip point voltage.
Figure 28: Open Schottky Diode Protection
When enabling the A8519 into an open-diode condition, the IC
will first go through all of its initial LED detection and will then
check the boost output voltage. At that point, the open diode is
detected.
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Input Overcurrent Protection and Disconnect Switch
The primary function of the input disconnect switch is to protect
the system and the device from catastrophic input currents during
a fault condition.
If the input current level goes above the preset current limit
threshold, the part will be shut down in less than 3 µs—this is a
latched condition. The fault flag is also set low to indicate a fault.
This protection feature prevents catastrophic failure in the system
due to a short of the inductor, inductor short to GND, or short at
the output GND. Figure 33 illustrates the typical input overcur-
rent fault condition. As soon as input OCP limit is reached, the
part disables the gate of the disconnect switch Q1.
During startup when Q1 first turns on, an inrush current flows
through Q1 into the output capacitance. If Q1 turns on too fast
(due to its low gate capacitance), the inrush current may trip
input OCP limit. In this case, an external gate capacitance CG is
added to slow down the turn-on transition. Typical value for CG
is around 4.7 to 22 nF. Do not make CG too large, since it also
slows down the turn-off transient during a real input OCP fault.
R
SC
C
G
Q1
V
IN
VIN
GND
VSENSE
R
adj
I
adj
To L1
A8519
GATE
Figure 32: Typical Circuit Showing Implementation of Input
Disconnect Feature
Figure 33: Startup into Output Shorted to GND fault. Input OCP
tripped at 4 A (RSC = 0.024 W, Radj =383 Ω)
Figure 31: Secondary Boost Switch OCP
There is also a secondary current limit (ISW(LIM2)) that is sensed
through the boost switch. This current limit, once detected,
immediately shuts down the A8519. The level of this current
limit is set above the cycle-by-cycle current limit to protect the
switch from destructive currents when boost inductor is shorted.
Figure 31 shows the secondary boost switch OCP. Once this limit
is reached, the A8519 will immediately shut down.
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VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect a capacitor with a value of 1 μF or greater to this pin.
The internal LDO can deliver no more than 2 mA of current with
a typical VDD voltage of about 3.5 V, enabling this pin to serve
as the pull-up voltage for the fault pin.
Shutdown
If PWM pin is pulled low for more than tPWML (32,750 clock
cycles), the device enters shutdown mode and clears all internal
fault registers. As an example, at 2 MHz clock frequency, it will
take approximately 16.3 ms to shut down the IC into the low
power mode. When shut down, the IC will disable all current
sources and wait until the PWM goes high to re-enable the IC.
Figure 35 depicts the shutdown using the PWM enable, showing
the 16.3 ms delay between PWM signal and when the VDD and
GATE of disconnect switch turn off.
Figure 35: Shutdown Using the PWM Enable
Setting the Current Sense Resistor
As shown in Figure 32:
VIN – VSENSE = VSC + Iadj × Radj
or
ISC = ((VIN – VSENSE) – Iadj × Radj)/RSC
where VSC = the voltage drop across RSC. The typical threshold
for the current sense is VIN – VSENSE = 110 mV when Radj is 0 W.
The A8519 can have this voltage trimmed using the Radj resistor.
It is recommended to set trip point to be above 3.65 A to avoid
conflicts with the cycle-by-cycle current limit typical threshold.
A sample calculation is done below for 4.25 A of input current.
Calculated max value of sense resistor RSC = 0.11 V / 4.25 A =
0.0259 Ω.
The RSC chosen is 0.024 Ω, a standard value. Therefore, the volt-
age drop across RSC is:
R=
adj
V= 4.25 A×0.024 Ω= 0.102 V
SC
V–V
VSENSE(trip) SC
Iadj
= 372ΩR=
adj
0.11 V – 0.102 V
21.5 µA
Input UVLO
When VIN and VSENSE rise above VUVLOrise threshold, the A8519
is enabled. The A8519 is disabled when VIN falls below VUVLOfall
threshold for more than 50 μs. This small delay is used to avoid
shutting down because of momentary glitches in the input power
supply.
Figure 34 illustrates a shutdown due to a falling input voltage
(VIN). When VIN falls below 3.90 V, the IC will shut down.
Figure 34: Shutdown with Falling Input Voltage
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Figure 38: Output Voltage Ripple Frequency Due to Dithering =
12.4 kHz at VIN = 12 V, and PWM Ratio = 100%
Figure 39: Output Voltage Ripple Amplitude Due to Dithering =
100 mV at VIN = 12 V, and PWM Ratio = 100%
Dithering Feature
To minimize the switching frequency harmonics, a dithering
feature is implemented in A8519. This feature simplifies the input
filters needed to meet the automotive CISPR 25 conducted and
radiated emission limits. The dithering sweep is internally set
at ±5%. The switching frequency will ramp from 0.95 times the
programmed frequency to 1.05 times the programmed frequency.
The rate or modulation at which the frequency sweeps is gov-
erned by an internal 12.5 kHz triangle pattern.
Figure 36: Minimum Dithering Switching Frequency = 2.02 MHz at
VIN = 12 V, and PWM Ratio = 100%
Figure 37: Maximum Dithering Switching Frequency = 2.23 MHz
at VIN = 12 V, and PWM Ratio = 100%
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Fault Protection During Operation
The A8519 series devices constantly monitor the state of the
system to determine if any fault conditions occur during normal
operation. The response to a triggered fault condition is sum-
marized in the table below. There are several points at which the
A8519 monitors for faults during operation. The locations are
input current, switch current, output voltage, switch voltage, and
LED pins. (Note: Some protection features might not be active
during startup to prevent false triggering of fault conditions.)
The detectable fault conditions are:
• Open LED pin
• Shorted LED pin to GND
• Open or shorted inductor
• Open or shorted boost diode
• Shorted inductor
• VOUT short to GND
• SW pin shorted to GND
• ISET pin shorted to GND
• Input disconnect switch source shorted to GND
Note: Some faults will not be protected if the input disconnect
switch is not used. An example of this is VOUT short to GND.
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Table 5: Fault Mode Table
Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
Switch
LED
Sink
Drivers
Primary Switch
Overcurrent
Protection (cycle-
by-cycle current
limit)
Auto-
restart Always NO
This fault condition is triggered when the SW current
exceeds the cycle-by-cycle current limit, ISW(LIM).The
present SW on-time is truncated immediately to limit the
current. Next switching cycle starts normally.
Off for
a single
cycle
ON ON
Secondary Switch
Current Limit Latched Always YES
When current through boost switch exceeds secondary
SW current limit (ISW(LIM2)), the device immediately shuts
down the disconnect switch, LED drivers, and boost.
The Fault flag is set. To re-enable the part, the PWM pin
needs to be pulled low for 32,750 clock cycles.
OFF OFF OFF
Input Disconnect
Current Limit Latched Always YES
The device is immediately shut off if the voltage
across the input sense resistor is above the
VVSENSE(trip) threshold. To re-enable the device, the
PWM pin must be pulled low for 32,750 clock cycles.
OFF OFF OFF
Secondary OVP Latched Always YES
Secondary overvoltage protection is used for open-diode
detection. When diode D1 opens, the SW pin voltage
will increase until VOVP(sec) is reached . This fault latches
the IC. The input disconnect switch is disabled as well
as the LED drivers. To re-enable the part, the PWM pin
needs to be pulled low for 32,750 clock cycles.
OFF OFF OFF
LEDx Pin Short
Protection
Auto-
restart Startup NO
This fault prevents the part from starting up if any of
the LED pins are shorted. The part stops soft-start from
starting while any of the LED pins are determined to be
shorted. Once the short is removed, soft-start is allowed
to start.
OFF ON OFF
LEDx Pin Open Auto-
restart
Normal
operation NO
When an LED pin is open, the device will determine
which LED pin is open by increasing the output voltage
until OVP is reached. Any LED string not in regulation
will be turned OFF. The device will then go back to
normal operation by reducing the output voltage to the
appropriate voltage level.
ON ON
OFF for
open
pins,
ON
for all
others
ISET Short
Protection
Auto-
restart Always NO
Fault occurs when the IISET current goes above 150% of
max current. The boost will stop switching and the IC will
disable the LED sinks until the fault is removed. When
the fault is removed, the IC will try to regulate to the
preset LED current.
OFF ON OFF
FSET Short
Protection
Auto-
restart Always YES
Fault occurs when the FSET current goes above 150%
of max current. The boost will stop switching, Disconnect
switch will turn off, and the IC will disable the LED sinks
until the fault is removed. When the fault is removed, the
IC will try to restart with soft-start.
OFF OFF OFF
Overvoltage
Protection
Auto-
restart Always NO
Fault occurs when OVP pin exceeds VOVP(th) threshold.
The IC will immediately stop switching to try to reduce
the output voltage. If the output voltage decreases,
then the IC will restart switching to regulate the output
voltage.
STOP
during
OVP event
ON ON
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Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
Switch
LED
Sink
Drivers
Undervoltage
Protection
Auto-
restart Always YES
Device immediately shuts off boost and current sinks if
the voltage at OVP pin is below VUVP(th). It will auto-
restart once the fault is removed.
OFF ON OFF
LED String Short
Detection
Auto-
restart Always NO
Fault occurs when the LED pin voltage exceeds
5.2 V. Once the LED string short fault is detected, the
LED string above the threshold will be removed from
operation.
ON ON
OFF for
shorted
pins, ON
for all
others
Overtemperature
Protection
Auto-
restart Always YES Fault occurs when the die temperature exceeds the
overtemperature threshold, typically 170°C. OFF OFF OFF
VIN UVLO Auto-
restart Always NO Fault occurs when VIN drops below VUVLOfall, typically
below 3.9 V. This fault resets all latched faults. OFF OFF OFF
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Design Example
This section provides a method for selecting component values
when designing an application using the A8519.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VIN: 10 to 14 V
• Quantity of LED channels, #CHANNELS: 4
• Quantity of series LEDs per channel, #SERIESLEDS: 10
• LED current per channel, ILED: 60 mA
• LED Vf at 60 mA: 3.2 V
• fSW: 2 MHz
• PWM dimming frequency 200 Hz, 1% duty cycle
Step 1: Connect LED strings to pins LED1, LED2, LED3, and
LED4.
Step 2: Determine the LED current set resistor RISET
R =
ISET
R =
ISET
R = 11.8 k
ISET
= 12 k
(V ×A )
ISET ISET
(1.017 × 710)
I
LED
0.06 A
An 11.8 kΩ resistor was chosen.
Step 3a: Determining the OVP resistor.
The OVP resistor is connected between the OVP pin and the
output voltage of the converter. The first step is to determine the
maximum voltage based on the LED requirements. The regula-
tion voltage for an LED pin (VLEDx) of the A8519 is 850 mV. A
5 V headroom is added to give margin to the design due to noise
and output voltage ripple.
VOUT(ovp) = #SERIESLEDs × Vf + VLED + 5 V
VOUT(ovp) = 10 × 3.2 V + 0.850 V + 5 V
VOUT(ovp) = 37.85 V
The OVP resistor is:
R=
OVP
(V – V )
OUT(ovp) OVP(th)
IOVP(th)
Where both IOVP(th) and VOVP(th) values are from the datasheet’s
Electrical Characteristics table.
R=
OVP
R = 147.75 k
OVP
37.85 – 8.3
0.2
Choose a value of resistor that is higher value than the calculated
ROVP. In this case, a value of 158 kΩ was selected. Below is the
actual value of the minimum OVP trip level with the selected
resistor.
VOUT(ovp) = 158 kΩ × 0.2 mA + 8.3 V
VOUT(ovp) = 39.9 V
Step 3b: At this point, a quick check needs to be done to see
if the conversion ratio is adequate for the selected frequency.
Where VD is the boost diode forward voltage, minimum off-time
(tSW(off)) is found in the datasheet:
Theoretical Max VOUT = 1 – D
MAX(boost)
D = 1–(85 ns × 2.2 MHz) = 0.813
MAX(boost)
D = 1–t × f
MAX(boost) SW(off) SW(max)
– VD
V
IN(min)
VD is the voltage drop of the boost diode.
10 V
Theoretical Max V
OUT
= 1 – 0.813 – 0.4 = 53.1 V
Theoretical Max VOUT value needs to greater than the value
VOUT(ovp). If this is not the case, the switching frequency of the
boost converter is going to have to be reduced to meet the maxi-
mum duty cycle requirements.
Step 4: Inductor selection.
The inductor needs to be chosen such that it can handle the neces-
sary input current. In most applications, due to stringent EMI
requirements, the system needs to operate in continues conduc-
tion mode throughout the whole input voltage range.
APPLICATION INFORMATION
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Step 4a: Determine the Duty Cycle.
D = 1 –
MAX (V + V )
OUT(ovp)
VIN(min)
D = 1 –
MAX (39.9 + 0.4)
10 = 0.75
D
Step 4b: Determine the maximum and minimum input current to
the system. The minimum input current will dictate the inductor
value. The maximum current rating will dictate the current rating
of the inductor.
I =
IN(max)
V × I
OUT(ovp) OUT
V ×
IN(min)
I = #Channels × I
I = 4 × 0.060A= 0.240 A
OUT
OUT LED
A good approximation of efficiency η can be taken from the
efficiency curves located on page 10. A value of 90% is a good
starting approximation.
I =
IN(max)
I =
IN(max)
10 V × 0.90
39.9 V × 240 mA = 1.06 A
I =
IN(min) 14 V × 0.90
32.85 V × 240 mA = 0.625 A
V = 10 × 3.2 V + 0.85 V = 32.85 V
OUT
V × I
OUT OUT
V ×
IN(max)
Step 4c: Determining the inductor value. To ensure that the
inductor operates in continuous conduction mode, the value of
the inductor needs to be set such that the ½ inductor ripple cur-
rent is not greater than the average minimum input current. A
first pass calculation for Kripple should be 30% of the maximum
inductor current.
I = I × K
L IN(max) ripple
I = 1.06A× 0.3 = 0.318 A
L
L = 0.318 A × 2 MHz
10 V × 0.75 = 11.79 µH
L = I × f )
L SW
(V × D )
IN(min) MAX
Double-check to make sure that ½ current ripple is less than
IIN(min).
IIN(min) > ½ DIL
0.625 A > 0.159 A
A good inductor value to use would be 10 µH.
Step 4d: This step is used to verify that there is sufficient slope
compensation for the inductor chosen. 6 A/µs slope compensation
value is applied inside the IC at 2 MHz switching frequency. The
slope compensation at any switching frequency can be deter-
mined by the following formula:
Slope Comp = 6 A/µs × fSW
2 × 10 6
Next, insert the inductor value used in the design:
ΔI =
L(used)
V × D
IN(min) MAX
L(used) × fSW
ΔI =
L(used) = 0.375 A
10 V × 0.75
10 µH × 2 MHz
Required Min Slope = ΔI × ΔS × 10
L(used)
-6
1
fSW
× (1 – D )
MAX
where ΔS is taken from the following formula:
ΔS = 1 – 0.18
D
MAX
ΔS = 0.76
= 2.28 A/µsRequired Min Slope = 0.375 × 0.76×10
-6
1
2 MHz × (1–0.75)
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If the required minimum slope is larger than the calculated slope
compensation, the inductor value needs to be increased. Note that
the slope compensation value is in A/μs the 1 × 10-6 is constant
multiplier.
Step 4e: Determining the inductor current rating.
I = I + (1/2) × ΔI
L(min) IN(max)
= 1.25 AI = 1.06A+
L(min)
0.375 A
2
L
Step 5: To determine the resistor value for a switching frequency
refer to the graph in Figure 8. A 10 kW resistor will result in a
2 MHz switching frequency.
Step 6: Choosing the proper output Schottky diode. The diode
needs to be chosen for three characteristics when it is used in
LED lighting circuitry. The most obvious two are the current
rating of the diode and the reverse voltage rating. The reverse
voltage rating should be larger than the maximum output VOVP .
The peak current through the diode is:
= 1.25 AI = 1.06 +
D(pk)
0.375 A
2
I = I +
D(pk) IN(max)
I
L(used)
2
The other major factor in deciding the switching diode is the
reverse current characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time, the boost converter is not switching. This
results in a slow bleeding off of the output voltage due to leakage
currents. IR or reverse current can be a large contributor espe-
cially at high temperatures. The reverse current of the selected
diode varies between 1 and 100 µA. For higher efficiency, use
a small forward voltage drop diode. For lower high-frequency
noise, choose a small junction capacitor diode.
Step 7: Choosing the output capacitors. The output capacitors
need to be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The biggest
factor that contributes to the size of the output capacitor is PWM
dimming frequency and the PWM duty cycle. Another major
contributor is leakage current (ILK). This current is the combina-
tion of the OVP current sense as well as the reverse current of
the boost diode. In this design, the PWM dimming frequency is
200 Hz; the minimum duty cycle is 0.02%. Typically, the voltage
variation on the output during PWM dimming needs to be less
than 250 mV (VCOUT) so there is no audible hum.
C = I ×
OUT LK
(1–minimum dimming duty cycles)
PWM dimming frequency × V
COUT
The selected diode leakage current at a 150°C junction tem-
perature and 30 V output is 100 μA, and the maximum leakage
current through OVP pin is 1 μA. The total leakage current can be
calculated as follows:
ILK = ILKG(diode) + ILKG(ovp)
= 100 μA + 1 μA
= 101 μA
C = 101 µA ×
OUT
= 2 µF
(1 – 0.02)
200 Hz × 0.250 V
A capacitor larger than 2 µF should be selected. Due to degrada-
tion of capacitance at dc voltages, a 4.7 µF / 50 V capacitor is a
good choice.
Vendor Value Part Number
Murata 4.7 µF / 50 V GRM21BC18H475KE11K
It is also necessary to note that if a high dimming ratio of 5000:1
must be maintained at lower input voltages, then larger out-
put capacitors will be needed. 4 × 4.7 µF / 50 V / X6S / 0805
capacitors are chosen; 0805 size is selected to minimize possible
audible noise.
The RMS current through the capacitor is given by:
C = I ×
OUT(rms) OUT
D +
MAX
IL(used)
1 – DMAX
I × 12
IN(max)
C = 0.240 ×
OUT(rms) = 0.424 A
0.75 + 0.375
1 – 0.75
1.06 × 12
The output capacitor needs to have a current rating of at least
0.424 A. The capacitors selected in this design, 4 × 4.7 µF / 50 V
/ X6S / 0805, have a combined current rating of more than 3 A
current rating.
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Step 8: Selection of input capacitor. The input capacitor needs to
be selected such that it provides good filtering of the input volt-
age waveform. A good rule of thumb is to set the input voltage
ripple ΔVIN to be 1% of the minimum input voltage. The mini-
mum input capacitor requirements are as follows:
C =
IN
ΔIL(used)
8 × f × ΔV
SW IN
C =
IN = 0.234 µF
0.375 A
8 × 2 MHz × 0.1 V
C =
IN(rms)
C =
IN(rms)
= 0.1 A
I ×
OUT
ΔIL(used)
(1 – D )× 12
MAX
IIN(max)
= 0.1 A
0.240 A × 0.375 A
(1 – 0.75) × 12
1.06 A
A good ceramic input capacitor with ratings of 50 V / 2.2 µF or
50 V / 4.7 µF will suffice for this application.
Vendor Value Part Number
Murata 4.7 µF / 50 V GRM32ER71H475KA88L
Murata 2.2 µF / 50 V GRM31CR71H225KA88L
If long wires are used for the input, it is necessary to use a much
larger input capacitor. A larger input capacitor is also required to
have stable input voltage during line transients. Combinations of
aluminum electrolytic and ceramic capacitors can be used.
Step 9: Choosing the input disconnect switch components.
Set the input disconnect current limit to 4.25 A.
R=
SC = 0.0259 Ω
0.11 V
4.25 A
The RSC chosen is 0.024 ohms. Therefore, the voltage drop across
RSC is:
R=
adj
V= 4.25 A×0.024 Ω= 0.102 V
SC
V–V
VSENSE(trip) SC
Iadj
= 372ΩR=
adj
0.11 V – 0.102 V
21.5 µA
A value of 383 W was chosen for this design. The disconnect
switch Q1 works as on or off. Therefore, the Radj value is not
really critical.
For the input disconnect switch, an AO4421 6.2 A / 60 V P-chan-
nel MOSFET is selected.
To achieve proper operation at low dimming ratios, connect an
RC filter to the VOUT pin. Use R = 10 kW and C = 47 pF.
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47 µF
Electrolytic 2.2 µF
10 µF47 pF 10 µF
1 µF
100 pF
10 µH
68 nF
0.024
383
280
158 k
10 k
10 k
11.8 k10 k
V= (4.5 to 40) V
IN
*optional
APWM
CLKOUT COMP
ISET FSET AGND
GND
PGND
VDD
VDD
PWM
LED4
LED1
LED2
LED3
OVP
VIN
GATE SW
VOUT
FAULT
VSENSE
Q1
V> V
OUT IN
A8519
Figure 40: Schematic Showing Calculated Values from the Design Example Above
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PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference MO-153 ACT)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
D
A
1.20 MAX
0.15
0.00
0.30
0.19
0.20
0.09
8º
0º
0.60 ±0.15
1.00 REF
C
SEATING
PLANE
C0.10
20X
0.65 BSC
0.25 BSC
21
1
20
6.50 ±0.10
4.40 ±0.103.00 3.00
4.20
4.20
6.40 ±0.20
GAUGE PLANE
SEATING PLANE
A
B
0.45
1.70
20
21
B
6.10
0.65
C
D
Exposed thermal pad (bottom surface)
C
PCB Layout Reference View
NNNNNNN
YYWW
LLLLLLL
Standard Branding Reference View
= Device part number
= Supplier emblem
= Last two digits of year of manufacture
= Week of manufacture
= Lot number
N
Y
W
L
Terminal #1 mark area
Reference land pattern layout (reference IPC7351 SOP65P640X110-21M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Branding scale and appearance at supplier discretion
Figure 41: Package LP: 20-Pin, 0.65 mm Pin Pitch TSSOP with Exposed Thermal Pad
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Figure 42: Package ET: 28-Pin QFN with Exposed Thermal Pad
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-220VHHD-1)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.25+0.05
–0.07
0.55 +0.20
–0.10
0.50
0.90 ±0.10
C
0.08
29X
SEATING
PLANE
C
A
B
C
28
2
1
A
28
1
2
B
3.15
3.17
3.17
3.15
0.28
1
28
0.50
1.35
5.05
5.05
C
5.00 ±0.10
5.00 ±0.10
D
D
PCB Layout Reference View
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Coplanarity includes exposed thermal pad and terminals
Wide Input Voltage Range, High-Efficiency, Fault-Tolerant LED Driver
A8519 and
A8519-1
38
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– September 10, 2014 Initial Release
1 October 24, 2014 Lowered minimum fSW (when using RFSET) to 200 kHz and SYNC down to 260 kHz.
2 March 18, 2015 Revised OVP Thresholds and Oscillator Frequencies.
3 May 19, 2015 Added A8519-1 variant.
4 June 10, 2015 Fixed typo on page 2; revised FSET pin voltage typical spec.
5 November 4, 2015
Amended “Enabling the IC” (page 12) and “Synchronization” (page 15) of Functional Description;
inserted Figures 18 and 19; updated Selection Guide table (page 2); corrected 2nd Typical Application
Drawing (page 9)
6 January 8, 2016 Amended “Powering Up: Boost Output Undervoltage Protection” (page 13)
7 October 24, 2016 Updated Input Overcurrent Protection and Disconnect Switch section (page 22)
8 December 21, 2018 Increased minimum external SYNC frequency to 320 kHz
9 January 23, 2019 Added timing diagrams to illustrate all possible cases to program the switching frequency (page 16);
Corrected Fault table for FAULT flag behavior during Overtemperature Protection (page 29)
10 March 14, 2019 Added Case 5 to Synchronization section (page 17)
Copyright 2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
