8K x 8 Power-Switched and Reprogrammable PROM
CY7C261
CY7C263/CY7C264
Cypress Semiconductor Corporation • 3901 North F irs t Street • San Jos e • CA 95134 • 408-943-2 600
Document #: 38-04010 Rev. *B Revised December 28, 2002
1
Features
• CMOS for optimum speed/power
• Window ed for reprogramm abi lity
• High speed
—20 ns (Commercial)
—25 ns (Military)
• Low power
—660 mW (Commercial)
—770 mW (Military)
• Super low standby power (7C261)
—Less than 220 mW when deselected
—Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-m il or st andard 600-mil packaging availabl e
•5V ± 10% VCC, commercial and military
• Capable of withstanding greater than 2001V static
discharge
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 81 92-word by 8-bit CMO S PROM s. When desele cted,
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600- mil-wid e packages respec tively, and do no t power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technol ogy a nd byt e-wid e inte lligen t pr ogrammin g algo rithms .
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requ ires only 12.5V for the su pervol tag e and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each lo cation is wri tten into , erase d, and rep eatedl y
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
Read is accomplished by placing an active LOW signa l on CS.
The contents of the memory location addressed by the
address line (A0−A12) will become available on the output lines
(O0−O7).
For an 8K x 8 Registered PROM, see theCY7C265.
Logic Block Diagram Pin Configurations
O7
O6
O5
O4
O3
O2
O1
O0
ADDRESS
DECODER
PROGRAM-
MABLE
ARRAY
COLUMN
MULTI-
PLEXER
POWER DOWN
(7C261)
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A11
A12
CS
GND
1
2
3
4
5
6
7
8
9
10
11 14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/Flatpack
A6
A5
A4
A3
A2
A1
A0
O0
A7
O3
VCC
A8
A9
A10
O7
O6
O5
O4
CS
O212 13
O1
A12
A11
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
O3
O1
O0
Top View
18
O4
O5
NC
A0
A4
A3
A10
NC
A8
A9
NC
NC
CS
A11
O7
O6
7C261
7C263
7C264
7C261
7C263
A7A2
A1A12
O2
COLUMN
ADDRESS
ROW
ADDRESS LCC/PLCC (Opaque Only)
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 2 of 14
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperatures .................................–65°C to+150°C
Ambient Temperature with
Power Applied..............................................–55°C to+125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)............................................–0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to+7.0V
DC Input Voltage...........................................–3.0V to + 7.0V
DC Pr ogram Voltage
(Pin 19 DIP, Pin 23 LCC) ..............................................13.0V
Static Discha rge Voltage..... ................. ...... ................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
UV Exposure ................................................7258 Wsec/cm2
Selection Guide
7C261-20
7C263-20
7C264-20
7C261-25
7C263-25
7C264-25
7C261-35
7C263-35
7C264-35
7C261-45
7C263-45
7C264-45
7C261-55
7C263-55
7C264-55 Unit
Maxi mu m A cc es s Time 20 25 35 45 55 ns
Maxi mu m Op er at ing
Current Commercial 120 120 100 100 100 mA
Military 140 120 120 120 mA
Maxi mu m Standby
Current (7C261 only) Commercial 40 40 30 30 30 mA
Military 40 30 30 30 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to + 70°C 5V ± 10%
Military[2] –55°C to + 125°C 5V ± 10%
Notes:
1. The volatge on any input or I/O pin cannot exceed the power pin during
power-up.
2. TA is the “instant on” case temperature.
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 3 of 14
Electrical Characteristi cs Ov er the Operating Ran ge [3,4]
7C261-20, 25
7C263-20, 25
7C264-20, 25
7C261-35, 45, 55
7C263-35, 45, 55
7C264-35, 45, 55
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8 mA
(6 mA Mil) 0.4 V
VOL Output LOW Voltage VCC = Min., IOL = 16 mA 0.4 V
VIH Input HIGH Level 2.0 2.0 V
VIL Input LOW Level 0.8 0.8 V
IIX Input Current GND < VIN < VCC –10 +10 –10 +10 µA
VCD Input Diode Clamp Voltage Note 4 Note 4
IOZ Output Leakage Current GND < VOUT < VCC
Output Disabled Com’l –10 +10 –10 +10 µA
Mil –40 +40 –40 +40 µA
IOS Output Short Circuit Current[5] VCC = Max. , VOUT = G ND –20 –90 –20 –90 mA
ICC Power Supply Current VCC = Max., f = Max.
IOUT = 0 mA Com’l 120 100 mA
Mil 140 120
ISB Standby Supply Current (7C261) VCC = Max. ,
CS > V IH Com’l 40 30 mA
Mil 40 30
VPP Programming Supply Voltage 12 13 12 13 V
IPP Programming Supply Current 50 50 mA
VIHP Input HIGH Programming Voltage 4.75 4.75 V
VILP Input LOW Programming Voltage 0.4 0.4 V
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.]
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 4 of 14
AC Test Loads and Waveforms[4]
Switching Characteris tics Over th e Opera ting Ra nge [1,3,4]
7C261-20
7C263-20
7C264-20
7C261-25
7C263-25
7C264-25
7C261-35
7C263-35
7C264-35
7C261-45
7C263-45
7C264-45
7C261-55
7C263-55
7C264-55
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tAA Address to Output Va lid 20 25 35 4 5 55 ns
tHZCS1 Chip Select Inactive to High Z
(7C263 and 7C264) 12 12 20 30 35 ns
tHZCS2 Chip Select Inactive to High Z
(7C261) 20 25 35 45 55 ns
tACS1 Chip Select Active to Output Valid
(7C263 and 7C264) 12 12 20 30 35 ns
tACS2 Chip Select Active to Output Valid
(7C261) 20 25 35 45 55 ns
tPU Chip Select Active to Power-Up
(7C261) 00000ns
tPD Chip Select Inactive to
Power-Down (7C261) 20 25 35 45 55 ns
R2333Ω
(403ΩMIL)
3.0V
5V
OUTPUT
R1500
(658ΩMIL)
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤5ns ≤5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a) Normal Load (b) HighZ Load
OUTPUT RTH 200Ω(250ΩMIL)
5V
OUTPUT 5V
OUTPUT
R1250Ω
30pF
INCLUDING
JIG AND
SCOPE
5pF
INCLUDING
JIG AND
SCOPE
(c)Normal Load (d) HighZ Load
OUTPUT 2.0V
RTH 100Ω
R1250Ω
R1500Ω
(658ΩMIL)
R2333Ω
(403ΩMIL)
R2167ΩR2167Ω
2.0V(1.9VMIL)
Test Load for -20 through -30 speeds
Test Load for -35 through -55 speeds
Equivalent to: THÉ VENIN EQUIVALEN T
Equivalent to: THÉ VENINEQUIVALENT
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 5 of 14
Erasure Characteri stics
W ave lengths of lig ht less than 400 0 angstroms begi n to erase
the devices in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviole t lamp with a 12 mW/cm 2 power rating, the ex posure ti me
would be approximately 35 minutes. The 7C261 or 7C263
needs to be within 1 inch of the lamp during erasure.
Permanent damage may result if the PROM is exposed to
high-intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.
Operating Modes
Read
Read is the normal operating mode fo r programmed device. In
this mode, all signals are normal TTL levels. The PROM is
addressed with a 13-bit field, a chip select, (active LOW), is
applied to the CS pin, and the contents of the addressed location
appear on the data out pins.
Program, Program Inhibit, Program Verify
These m odes are en tered b y pla cing a high volt age VPP on pin
19, with pin s 18 and 20 set t o V ILP. In this state, pin 21 becomes a
latch signal, allo wi ng the upp er 5 addr ess bits to b e latc hed into an
onboard r egister, pin 22 be comes an act ive LOW progr am (PGM)
signal and pin 23 becomes an active LOW verify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The
PROGRAM mode exists when PGM is LOW, and VFY is HIGH. The
verify mode exists wh en the reverse is tru e, PGM HIGH and VFY
LOW and the prog ram inhib it mode is ente red wi th both PGM and
VFY HIGH. Program inhibit is specifically provided to allow data to be
placed on and removed from the data pins without conflict
Swit c h in g Waveform s[4]
tAA
VCC
SUPPLY
CURRENT
A0-A
12
ADDRESS
CS
tPU
O0-O
7
tHZCS tACS
50% 50%
tPD
Table 1. Mode Selection
Pin Function[6, 7]
Read or Output Disable A12 A11 A10 A9A8CS O7–O0
Mode Program NA VPP LATCH PGM VFY CS D7–D0
Read A12 A11 A10 A9A8VIL O7–O0
Output Disable A12 A11 A10 A9A8VIH High Z
Program VILP VPP VILP VILP VIHP VILP D7–D0
Pro gram Inhibit VILP VPP VILP VIHP VIHP VILP High Z
Program Verify VILP VPP VILP VIHP VILP VILP O7–O0
Blank Check VILP VPP VILP VIHP VILP VILP O7–O0
Notes:
6. X = “don’t care” but not to exceed VCC ±5%.
7. Addresses A8-A12 must be latched throug h lines A0-A4 in programmin g modes.
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 6 of 14
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Figure 1. Programming Pinouts
DIP/Flatpack LCC/PLCC
Top View Top View
GND
1
2
3
4
5
6
7
8
9
10
11 14
15
16
20
19
18
17
21
24
23
22
A6
A5
A4/A
12
A3/A
11
A2/A10
A1/A9
A0/A8
D0
A7
D3
VCC
VFY
PGM
LATCH
D7
D6
D5
D4
CS
D212 13
D1
NA
VPP
28
4
5
6
7
8
9
10
321 27
13 14 1516 17
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0/A8
A4/A12
A3/A11
LATCH
NC
NC
CS
VPP
D7
D6
7C261
7C263
7C264
7C261
7C263
A2/A10
A1/A9NA
D2
PGM
VFY
NC
(Opaque only)
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 7 of 14
Typical DC and AC Characteristics
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 –55 25 125
1.2
1.1
1.2
1.0
0.8
0.6
4.0 4.5 5.0 5.5 6.0
NORMALIZED ACCESS TIME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C) SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.6
1.2
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORM ALIZED I
CC
NORMALIZED I
CC
VCC = 5.0V
TA= 25°C
TA= 25°C
0.6
0.4
60
50
40
30
20
10
01.0 2.03.0
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
30
25
20
15
10
5
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
4.0 1000
VCC = 4.5V
TA= 25°C
TA= 25°C
f= fMAX
25 0
OUTPUT SOURCE CURRENT
vs. VOLTAGE
4.0
1.00
1.05
0.95
0.85
0.80
0.75
025 5075
100
0.70
0.90
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
CYCLE PERIOD (ns)
NORMALIZED I
CC
VCC = 5.5V
TA= 25°C
0
35
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 8 of 14
]
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
20 CY7C261-20PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C261-20WC W14 24-Lead (300-Mil) Windowed CerDIP
25 CY7C261-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C261-25PC P13 24-Lead (300-Mil) Molded DIP
CY7C261-25WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
35 CY7C261-35PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C261-35WC W14 24-Lead (300-Mil) Windowed CerDIP
CY7C261-35WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
45 CY7C261-45PC P13 224-Lead (300-Mil) Molded DIP Commercial
CY7C261-45WC W14 24-Lead (300-Mil) Windowed CerDIP
CY7C261-45WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
55 CY7C261-55WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial
20 CY7C263-20JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C263-20PC P13 24-Lead (300-Mil) Molded DIP
CY7C263-20WC W14 24-Lead (300-Mil) Windowed CerDIP
25 CY7C263-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C263-25PC P13 24-Lead (300-Mil) Molded DIP
CY7C263-25WC W14 24-Lead (300-Mil) Windowed CerDIP
CY7C263-25DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C263-25QMB Q64 28 -Pin Win dowe d Lead les s Chip Carrier
CY7C263-25WMB W14 24-Lead (300-Mil) Windowed CerDIP
35 CY7C263-35PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C263-35WC W14 24-Lead (300-Mil) Windowed CerDIP
CY7C263-35WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
45 CY7C263-45WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
55 CY7C263-55JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
CY7C263-55PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C263-55WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
35 CY7C264-35PC P11 24-Lead (600-Mil) Molded DIP Commercial
45 CY7C264-45WC W12 24-Lead (600-Mil) Windowed CerDIP Commercial
CY7C264-45WMB W12 24-Lead (600-Mil) Windowed CerDIP Military
55 CY7C264-55WC W12 24-Lead (600-Mil) Windowed CerDIP Commercial
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 9 of 14
MILITARY SPECIFICATION
Group A Subgroup Testing
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
ISB[8] 1, 2, 3
Switching Characteristics
Parameter Subgroups
tAA 7, 8, 9, 10, 11
tACS1[9] 7, 8, 9, 10, 11
tACS2[8] 7, 8, 9, 10, 11
Notes:
8. 7C261 only.
9. 7C263 and 7C264 only.
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 10 of 14
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031
28-Lead Plastic Leaded Chip Carrier J64
51-85001-A
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 11 of 14
Package Diagrams (continued)
51-85016-A
24-Lead (600-Mil) Molded DIP P11
51-85013-A
24-Lead (300-Mil) Molded DIP P13/P13A
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 12 of 14
Package Diagrams (continued)
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 13 of 14
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other ri ghts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
24-Lead (600-Mil) Windowed CerDIP W12
MIL-STD-1835 D-3 Config. A
51-80089-**
51-80086
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
CY7C261
CY7C263/CY7C264
Document #: 38-04010 Rev. *B Page 14 of 14
Document History Page
)
Document Title: CY7C261 CY7C263/CY7C264 8K x 8 Power Switched and Reprogrammable PROM
Document Number: 38-04010
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113866 3/6/02 DSG Change from Spec number: 38-00005 to 38-04010
*A 11889 5 10 /09 /02 GBI Update Ord erin g Inform at ion
*B 122251 12/28/02 RBI Add power up requirements to Maximum Ratings information
