FN3182 Rev 10.00 Page 1 of 15
August 10, 2015
FN3182
Rev 10.00
August 10, 2015
ICL7665S
CMOS Micropower Over/Under Voltage Detector
DATASHEET
The ICL7665S super CMOS micropower Over/Under
voltage detector contains two low power, individually
programmable voltage detectors on a single CMOS chip.
Requiring typically 3A for operation, the device is intended
for battery-operated systems and instruments which require
high or low voltage warnings, settable trip points, or fault
monitoring and correction. The trip points and hysteresis of
the two voltage detectors are individually programmed via
external resistors. An internal bandgap type reference
provides an accurate threshold voltage while operating from
any supply in the 1.6V to 16V range.
The ICL7665S, super programmable Over/Under voltage
detector is a direct replacement for the industry standard.
The ICL7665B offering wider operating voltage and
temperature ranges, improved threshold accuracy
(ICL7665SA), and temperature coefficient, and guaranteed
maximum supply current. All improvements are highlighted
in the electrical characteristics section. All critical
parameters are gu aranteed over the entire commercial
and industrial temperature ranges.
Pinout
ICL7665S
(SOIC, PDIP)
TOP VIEW
Features
• Guaranteed 10µA maximum quiescent current
over-temperature
• Guaranteed wider operating voltage range over entire
operating temperature range
• 2% threshold accuracy (ICL7665SA)
• Dual comparator with precision internal reference
• 100ppm/°C temperature coefficient of threshold voltage
• 100% tested at 2V
• Output current sinking ability . . . . . . . . . . . . . Up to 20mA
• Individually programmable upper and lower trip voltages
and hysteresis levels
• Pb-Free available (RoHS Compliant)
Applications
• Pocket pagers
• Portable instrumentation
• Charging systems
• Memory power back-up
• Battery operated systems
• Portable computers
• Level detectors
OUT 1
HYST 1
SET 1
GND
1
2
3
4
8
7
6
5
V+
OUT 2
SET 2
HYST 2
ICL7665S
FN3182 Rev 10.00 Page 2 of 15
August 10, 2015
Ordering Information
PART NUMBER PART MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
ICL7665SACBAZ (Notes 1, 3) 7665S ACBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ICL7665SACBAZA (Notes 1, 3) 7665S ACBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ICL7665SACPAZ (Note 2) 7665S ACPAZ 0 to +70 8 Ld PDIP (Pb-free) E8.3
ICL7665SAIBAZA (Notes 1, 3) 7665 SAIBAZ -40 to +85 8 Ld SOIC (Pb-free) M8.15
ICL7665SAIPAZ (Note 2) 7665S AIPAZ -40 to +85 8 Ld PDIP (Pb-free) E8.3
ICL7665SCBAZ (Notes 1, 3) 7665 SCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ICL7665SCBAZA (Notes 1, 3) 7665 SCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ICL7665SCPAZ (Note 2) 7665S CPAZ 0 to +70 8 Ld PDIP (Pb-free) E8.3
ICL7665SIBAZ (Notes 1, 3) 7665 SIBAZ -40 to +85 8 Ld SOIC (Pb-free) M8.15
ICL7665SIBAZA (Notes 1, 3) 7665 SIBAZ -40 to +85 8 Ld SOIC(Pb-free) M8.15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ICL7665S
FN3182 Rev 10.00 Page 3 of 15
August 10, 2015
Absolute Maximum Ratings Thermal Information
Supply Voltage (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V
Output Voltages OUT1 and OUT2 . . . . . . . . . . . . . . . . -0.3V to +18V
(with respect to GND) (Note 5)
Output Voltages HYST1 and HYST2 . . . . . . . . . . . . . . -0.3V to +18V
(with respect to V+) (Note 5)
Input Voltages SET1 and SET2 . . . . . (GND -0.3V) to (V+ V- +0.3V)
(Note 5)
Maximum Sink Output OUT1 and OUT2 . . . . . . . . . . . . . . . . . 25mA
Maximum Source Output Current
HYST1 and HYST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA
Operating Conditions
Temperature Range
ICL7665SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICL7665SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 4) JA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . +150°C
Maximum Junction Temperature (CERDIP). . . . . . . . . . . . . .+175°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300°C
(SOIC - Lead Tips Only)
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on an evaluation PC board in free air.
5. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+
+0.3V) or less than (GND - 0.3V) may cause destructive device latchup. For these reasons, it is recommended that no inputs from external
sources not operating from the same power supply be applied to the device before its supply is established, and that in multiple supply systems,
the supply to the ICL7665S be turned on first. If this is not possible, current into inputs and/or outputs must be limited to 0.5mA and voltages
must not exceed those defined above.
Electrical Specifications The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = +25°C,
Test Circuit Figure 7. Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage V+ ICL7665S TA = +25°C1.6-16V
0°C TA +70°C1.8-16V
-25°C TA +85°C1.8-16V
ICL7665SA 0°C TA +70°C1.8-16V
-25°C TA +85°C1.8-16V
Supply Current I+ GND VSET1, VSET2 V+, All Outputs Open Circuit
0°C TA +70°C V+ = 2V - 2.5 10 µA
V+ = 9V - 2.6 10 µA
V+ = 15V - 2.9 10 µA
-40°C TA +85°C V+ = 2V - 2.5 10 µA
V+ = 9V - 2.6 10 µA
V+ = 15V - 2.9 10 µA
Input Trip Voltage VSET1 ICL7665S 1.20 1.30 1.40 V
VSET2 1.20 1.30 1.40 V
VSET1 ICL7665SA 1.275 1.30 1.325 V
VSET2 1.275 1.30 1.325 V
Temperature Coefficient of
VSET
VSET
T
ICL7665S - 200 - ppm
ICL7665SA - 100 - ppm
Supply Voltage Sensitivity of
VSET1, VSET2
VSET
VS
ROUT1, ROUT2, RHYST1, R2HYST2 = 1M
2V V+ 10V
-0.03-%/V
ICL7665S
FN3182 Rev 10.00 Page 4 of 15
August 10, 2015
Output Leakage Currents of
OUT and HYST
IOLK VSET = 0V or VSET 2V - 10 200 nA
IHLK - -10 -100 nA
IOLK V+ = 15V - - 2000 nA
IHLK - - -500 nA
Output Saturation Voltages VOUT1 VSET1 = 2V,
IOUT1 = 2mA
V+ = 2V - 0.2 0.5 V
V+ = 5V - 0.1 0.3 V
V+ = 15V - 0.06 0.2 V
Output Saturation Voltages VHYST1 VSET1 = 2V,
IHYST1 = -0.5mA
V+ = 2V - -0.15 -0.30 V
V+ = 5V - -0.05 -0.15 V
V+ = 15V - -0.02 -0.10 V
Output Saturation Voltages VOUT2 VSET2 = 0V,
IOUT2 = 2mA
V+ = 2V - 0.2 0.5 V
V+ = 5V - 0.15 0.3 V
V+ = 15V - 0.11 0.25 V
Output Saturation Voltages VHYST2 VSET2 = 2V V+ = 2V, IHYST2 = -0.2mA - -0.25 -0.8 V
V+ = 5V, IHYST2 = -0.5mA - -0.43 -1.0 V
V+ = 15V, IHYST2 = -0.5mA - -0.35 -0.8 V
VSET Input Leakage Current ISET GND VSET V+ - 0.01 10 nA
Input for Complete Output
Change
VSET ROUT = 4.7k,
RHYST = 20k,
VOUTLO = 1% V+,
VOUTHI = 99% V+
ICL7665S - 1.0 - mV
ICL7665SA - 0.1 - mV
Difference in Trip Voltages VSET1 -
VSET2
ROUT
, RHYST = 1mW - 550 mV
Output/Hysteresis
Difference
ROUT
, RHYST = 1mW ICL7665S - 1-mV
ICL7665SA - 0.1 - mV
NOTES:
6. Derate above +25°C ambient temperature at 4mW/°C.
7. All significant improvements over the industry standard ICL7665 are highlighted.
Electrical Specifications The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = +25°C,
Test Circuit Figure 7. Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICL7665S
FN3182 Rev 10.00 Page 5 of 15
August 10, 2015
Functional Block Diagram
AC Electrical Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OUTPUT DELAY TIMES
Input Going HI tSO1D VSET Switched between 1.0V to 1.6V
ROUT = 4.7k, CL = 12pF
RHYST = 20k, CL = 12pF
-85-µs
tSH1D -90-µs
tSO2D -55-µs
tSH2D -55-µs
Input Going LO tSO1D VSET Switched between 1.6V to 1.0V
ROUT = 4.7k, CL = 12pF
RHYST = 20k, CL = 12pF
-75-µs
tSH1D -80-µs
tSO2D -60-µs
tSH2D -60-µs
Output Rise Times tO1R VSET Switched between 1.0V to 1.6V
ROUT = 4.7k, CL = 12pF
RHYST = 20k, CL = 12pF
-0.6- µs
tO2R -0.8- µs
tH1R -7.5- µs
tH2R -0.7- µs
Output Fall Times tO1F VSET Switched between 1.0V to 1.6V
ROUT = 4.7k, CL = 12pF
RHYST = 20k, CL = 12pF
-0.6- µs
tO2F -0.7- µs
tH1F -4.0- µs
tH2F -1.8- µs
REF
SET1
SET2
+
-
+
-
V+
HYST2
HYST1
OUT2
OUT1
GND
CONDITIONS (Note 5)
VSET1 > 1.3V, OUT1 Switch ON, HYST1 Switch ON
VSET1 < 1.3V, OUT1 Switch OFF, HYST1 Switch OFF
VSET2 > 1.3V, OUT2 Switch OFF, HYST2 Switch ON
VSET2 < 1.3V, OUT2 Switch ON, HYST2 Switch OFF
NOTE:
8. See Electrical Specifications for exact thresholds.
ICL7665S
FN3182 Rev 10.00 Page 6 of 15
August 10, 2015
Typical Performance Curves
FIGURE 1. OUT1 SATURATION VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
FIGURE 2. OUT2 SATURATION VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
FIGURE 3. HYST1 OUTPUT SATURATION VOLTAGE vs
HYST1 OUTPUT CURRENT
FIGURE 4. HYST2 OUTPUT SATURATION VOLTAGE vs
HYST2 OUTPUT CURRENT
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF AMBIENT
TEMPERATURE
FIGURE 6. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
VOLTAGE SATURATION (V)
2.0
1.5
1.0
0.5
0
0 5 10 15 20
IOUTOUT1 (mA)
V+ = 2V
V+ = 5V
V+ = 15V
V+ = 9V
0 5 10 15 20
2.0
1.5
1.0
0.5
0
VOLTAGE SATURATION (V)
IOUTOUT2 (mA)
V+ = 2V
V+ = 5V
V+ = 9V
V+ = 15V
-20 -16 -12 -8 -4 0
0
-0.4
-0.8
-1.2
-1.6
-2.0
HYST1 OUTPUT SATURATION VOLTAGE (V)
HYST1 OUTPUT CURRENT (mA)
V+ = 15V
V+ = 9V
V+ = 5V V+ = 2V
TA = 25°C
-5.0 -4.0 -3.0 -2.0 -1.0 0 0
-1.0
-2.0
-3.0
-4.0
-5.0
HYST2 OUTPUT CURRENT (mA)
HYST2 OUTPUT SATURATION VOLTAGE (V)
TA = 25°C
V+ = 15V
V+ = 9V
V+ = 5V V+ = 2V
V+ = 2V
V+ = 15V V+ = 9V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-25 0 +20 +40 +60
AMBIENT TEMPERATURE (°C)
SUPPLY CURRENT (A)
0V VSET1, VSET2 V+
0V VSET1, VSET2 V+
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 2 4 6 810121416
SUPPLY VOLTAGE (V+)
SUPPLY CURRENT (A)
TA = -20°C
TA = 25°C
TA = 70°C
ICL7665S
FN3182 Rev 10.00 Page 7 of 15
August 10, 2015
Detailed Description
As shown in the Functional Diagram, the ICL7665S consists
of two comparators which compare input voltages on the
SET1 and SET2 terminals to an internal 1.3V bandgap
reference. The outputs from the two comparators drive
open-drain N-channel transistors for OUT1 and OUT2, and
open-drain P-channel transistors for HYST1 and HYST2
outputs. Each section, the Undervoltage Detector and the
Overvoltage Detector, is independent of the other, although
both use the internal 1.3V reference. The offset voltages of
the two comparators will normally be unequal so VSET1 will
generally not quite equal VSET2.
The input impedance of the SET1 and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting up
the hysteresis, and maximizes the output flexibility. The
operating currents of the bandgap reference and the
comparators are around 100nA each.
Precautions
Junction isolated CMOS devices like the ICL7665S have an
inherent SCR or 4-layer PNPN structure distributed throughout
the die. Under certain circumstances, this can be triggered into
a potentially destructive high current mode. This latchup can be
triggered by forward-biasing an input or output with respect to
the power supply, or by applying excessive supply voltages. In
very low current analog circuits, such as the ICL7665S, this
SCR can also be triggered by applying the input power supply
extremely rapidly (“instantaneously”), e.g., through a low
impedance battery and an ON/OFF switch with short lead
lengths. The rate-of-rise of the supply voltage can exceed
100V/s in such a circuit. A low impedance capacitor (e.g.,
0.05F disc ceramic) between the V+ and GND pins of the
ICL7665S can be used to reduce the rate-of-rise of the supply
voltage in battery applications. In line operated systems, the
rate-of-rise of the supply is limited by other considerations, and
is normally not a problem.
If the SET voltages must be applied before the supply voltage
V+, the input current should be limited to less than 0.5mA by
appropriate external resistors, usually required for voltage
setting anyway. A similar precaution should be taken with the
outputs if it is likely that they will be driven by other circuits to
levels outside the supplies at any time.
Additionally, with a V+ supply that has ringing or drooping after
power up, a false transition on the OUTx output may occur
even though the resistor programmed threshold voltage is not
encroached upon. This occurs as the internal bandgap circuit
time constant, on the order of a microsecond is matched by the
V+ transient. If this occurs connecting a 1F to the SETx pin will
eliminate the OUTx false transition as the additional
capacitance moves the external time constant three orders of
magnitude above the internal time constant.
Simple Threshold Detector
Figure 9 shows the simplest connection of the ICL7665S for
threshold detection. From the graph 9B, it can be seen that
at low input voltage OUT1 is OFF, or high, while OUT2 is
ON, or low. As the input rises (e.g., at power-on) toward
VNOM (usually the eventual operating voltage), OUT2 goes
high on reaching VTR2. If the voltage rises above VNOM as
much as VTR1, OUT1 goes low. The Equations are giving
VSET1 and VSET2 are from Figure 9A:
Since the voltage to trip each comparator is nominally 1.3V,
the value VIN for each trip point can be found from
and
1
2
3
4
8
7
6
5
OUT1
HYST1
SET1
GND
V+
OUT2
SET2
HYST2
INPUT
HYST2
OUT2
OUT1
V+
20
k
12
pF
12
pF
12
pF
12
pF
20
k
4.7k
HYST1
4.7
k
1.0V
1.6V
FIGURE 7. TEST CIRCUITS
VSET1,
VSET2
tSO1D
tO1F tSO1D
tO1R
tSH1D
tH1R
tSH1D
tH1F
tSO2D
tO2R
tSO2D
tO2F
tSH2D
tH2R
tSH2D
tH2F
1.6V
1.0V
V+
GND
GND
GND
GND
(5V)
V+
(5V)
V+
(5V)
V+
(5V)
INPUT
OUT1
HYST1
OUT2
HYST2
FIGURE 8. SWITCHING WAVEFORMS
VSET1 VIN
R11
R11 R21
+
--------------------------------
=VSET2 VIN
R12
R12 R22
+
--------------------------------
=
VTR1 VSET1
R11 R21
+
R11
----------------------------------1.3
R11 R21
+
R11
---------------------------------- for detector 1==
VTR2 VSET2
R12 R22
+
R12
----------------------------------1.3
R12 R22
+
R12
---------------------------------- for detector 2==
ICL7665S
FN3182 Rev 10.00 Page 8 of 15
August 10, 2015
Either detector may be used alone, as well as both together,
in any of the circuits shown here.
When VIN is very close to one of the trip voltage, normal
variations and noise may cause it to wander back and forth
across this level, leading to erratic output ON and OFF
conditions. The addition of hysteresis, making the trip points
slightly different for rising and falling inputs, will avoid this
condition.
Threshold Detector with Hysteresis
Figure 10A shows how to set up such hysteresis, while
Figure 10B shows how the hysteresis around each trip point
produces switching action at different points depending on
whether VIN is rising or falling (the arrows indicated direction
of change. The HYST outputs are basically switches which
short out R31 or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value, the trip
point will be controlled by R1N, R2N, and R3N, until the trip
point is reached. As this value is passed, the detector
changes state, R3N is shorted out, and the trip point
becomes controlled by only R1N and R2N, a lower value.
The input will then have to fall to this new point to restore the
initial comparator state, but as soon as this occurs, the trip
point will be raised again.
An alternative circuit for obtaining hysteresis is shown in
Figure 11. In this configuration, the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ, but the action is essentially the same.
The governing Equations are given in Table 1. These ignore
the effects of the resistance of the HYST outputs, but these
can normally be neglected if the resistor values are above
about 100k.
FIGURE 9A. CIRCUIT CONFIGURATION FIGURE 9B. TRANSFER CHARACTERISTICS
FIGURE 9. SIMPLE THRESHOLD DETECTOR
OUT1
SET1 SET2
OUT2
V+
R21
RP2
VIN
RP1
R22
R11 R12
OFF
VOUT
ON
VTR2 VNOM VTR1
DETECTOR 2 DETECTOR 1
FIGURE 10A. CIRCUIT CONFIGURATION FIGURE 10B. TRANSFER CHARACTERISTICS
FIGURE 10. THRESHOLD DETECTOR WITH HYSTERESIS
HYST1
SET1 SET2
HYST2
V+
VIN
OUT1 OUT2
R31 R32
R12
R11
R21 R22
OVERVOLTAGE OVERVOLTAGE
VL2 VU2 VL1 VU1
ON
OUT
OFF
VNOM
DETECTOR 2 DETECTOR 1
VIN
VTR2 VSET2
R12 R22
+
R12
----------------------------------1.3
R12 R22
+
R12
---------------------------------- for detector 2==
ICL7665S
FN3182 Rev 10.00 Page 9 of 15
August 10, 2015
Applications
Single Supply Fault Monitor
Figure 12 shows an over/under voltage fault monitor for a
single supply. The overvoltage trip point is centered around
5.5V and the undervoltage trip point is centered around 4.5V.
Both have some hysteresis to prevent erratic output ON and
OFF conditions. The two outputs are connected in a wired
OR configuration with a pull-up resistor to generate a power
OK signal.
Multiple Supply Fault Monitor
The ICL7665S can simultaneously monitor several supplies
when connected as shown in Figure 13. The resistors are
chosen such that the sum of the currents through R21A,
R21B, and R31 is equal to the current through R11 when the
two input voltage are at the desired low voltage detection
point. The current through R11 at this point is equal to
1.3V/R11. The voltage at the VSET input depends on the
voltage of both supplies being monitored. The trip voltage of
one supply while the other supply is at the nominal voltage
will be different that the trip voltage when both supplies are
below their nominal voltages.
The other side of the ICL7665S can be used to detect the
absence of negative supplies. The trip points for OUT1
depend on both the negative supply voltages and the actual
voltage of the +5V supply.
TABLE 1. SET-POINT EQUATIONS
NO HYSTERESIS
Overvoltage VTRIP = R11 + R21
R11
x VSET1
Overvoltage VTRIP = R12 + R22
R12
x VSET2
HYSTERESIS PER FIGURE 10A
VU1 =R11 + R21 + R31
R11
x VSET1
Overvoltage VTRIP
VL1 =R11 + R21
R11
x VSET1
VU2 =R12 + R22 + R32
R12
x VSET2
Undervoltage VTRIP
VL2 =R12 + R22
R12
x VSET2
HYSTERESIS PER FIGURE 11
VU1 =R11 + R21
R11
x VSET1
Overvoltage VTRIP
VL1 =
R11 + R21R31
R21 + R31 x VSET1
R11
VU2 =R12 + R22
R12
x VSET2
Overvoltage VTRIP
VL2 =R12 + R22R32
R22 + R32 x VSET2
R12
OUT1
SET1 SET2
OUT2
V+
R21
RP
VIN
RP
R22
R11 R12
HYST1 HYST2
R31 R32
FIGURE 11. AN ALTERNATIVE HYSTERESIS CIRCUIT
HYST1
VSET1 VSET2
HYST2
V+
OUT1 OUT2
324k
13M
5%
100k
249k
7.5M
5%
+5V SUPPLY
POWER
OK
100k
1M
V+
OPEN VOLTAGE
DETECTOR
VU = 5.55V
VL = 5.45V
OPEN VOLTAGE
DETECTOR
VU = 4.55V
VL = 4.45V
R22
R32
R12
R11
R31
R21
FIGURE 12. FAULT MONITOR FOR A SINGLE SUPPLY
ICL7665S
FN3182 Rev 10.00 Page 10 of 15
August 10, 2015
Combination Low Battery Warning and Low
Battery Disconnect
When using rechargeable batteries in a system, it is
important to keep the batteries from being over discharged.
The circuit shown in Figure 14 provides a low battery
warning and also disconnects the low battery from the rest of
the system to prevent damage to the battery. The OUT1 is
used to shutdown the ICL7663S when the battery voltage
drops to the value where the load should be disconnected.
As long as VSET1 is greater than 1.3V, OUT1 is low, but
when VSET1 drops below 1.3V, OUT1 goes high shutting off
the ICL7663S. The OUT2 is used for low battery warning.
When VSET2 is greater than 1.3V, OUT2 is high and the low
battery warning is on. When VSET2 drops below 1.3V, OUT2
is low and the low battery warning goes off. The trip voltage
for low battery warning can be set higher than the trip
voltage for shutdown to give advance low battery warning
before the battery is disconnected.
Power Fail Warning and Power-up/Power-down
Reset
Figure 14 shows a power fail warning circuit with
power-up/power-down reset. When the unregulated DC
input is above the trip point, OUT1 is low. When the DC input
drops below the trip point, OUT1 shuts OFF and the power
fail warning goes high. The voltage on the input of the 7805
will continue to provide 5V out at 1A until VIN is less than
7.3V, this circuit will provide a certain amount of warning
before the 5V output begins to drop.
The ICL7665S OUT2 is used to prevent a microprocessor
from writing spurious data to a CMOS battery backup
memory by causing OUT2 to go low when the 7805 5V
output drops below the ICL7665S trip point.
FIGURE 13. MULTIPLE SUPPLY FAULT MONITOR
HYST1
VSET1 VSET2
HYST2
V+
OUT1 OUT2
274k
R21
100k
22
POWER
OK
301
R11
+5V
-15V-5V
M
k
787
k+5V
1M
1.02M
R21A
R21B
22M
49.9k
+5V
+15V
HYST1
SET1 SET2
HYST2
V+
OUT1 OUT2
R31 R32
R12
R11
R21 R22
GND
+
-
LOW BATTERY SHUTDOWN
1M
V+
OUT1
SHUTDOWN VSET
OUT2
V+
GND
1M
LOW BATTERY WARNING
SENSE
100
+5V
1A
ICL7663S
ICL7665S
FIGURE 14. LOW BATTERY WARNING AND LOW BATTERY DISCONNECT
ICL7665S
FN3182 Rev 10.00 Page 11 of 15
August 10, 2015
Simple High/Low Temperature Alarm
Figure 16 illustrates a simple high/low temperature alarm
which uses the ICL7665S with an NPN transistor. The voltage
at the top of R1 is determined by the VBE of the transistor and
the position of R1’s wiper arm. This voltage has a negative
temperature coefficient. R1 is adjusted so that VSET2 equals
1.3V when the NPN transistor’s temperature reaches the
temperature selected for the high temperature alarm. When
this occurs, OUT2 goes low. R2 is adjusted so that VSET1
equals 1.3V when the NPN transistor’s temperature reaches
the temperature selected for the low temperature alarm. When
the temperature drops below this limit, OUT1 goes low.
AC Power Fail and Brownout Detector
Figure 17 shows a circuit that detects AC undervoltage by
monitoring the secondary side of the transformer. The
capacitor, C1, is charged through R1 when OUT1 is OFF. With
a normal 100 VAC input to the transformer, OUT1 will
discharge C1 once every cycle, approximately every 16.7ms.
When the AC input voltage is reduced, OUT1 will stay OFF, so
that C1 does not discharge. When the voltage on C1 reaches
1.3V, OUT2 turns OFF and the power fail warning goes high.
The time constant, R1C1, is chosen such that it takes longer
than 16.7ms to charge C1 1.3V.
HYST1
VSET1 VSET2
HYST2
V+
OUT1 OUT2
5.86k
130k
BACKUP
BATTERY
7805
5V REGULATOR
UNREGULATED
DC INPUT
1M
22M
2.2M
1M
715k
1M
RESET OR
WRITE
ENABLE
POWER
FAIL
WARNING
470F
4700F
ICL7665S
FIGURE 15. POWER FAIL WARNING AND POWERUP/POWERDOWN RESET
ICL7665S
FN3182 Rev 10.00 Page 12 of 15
August 10, 2015
HYST1
VSET1 VSET2
HYST2
V+
OUT1 OUT2
22k
1.5M
22M
1M
27k
R4
R5
V+
1M
R7
R2
R6
ALARM SIGNAL
FOR DRIVING
LEDS, BELLS,
ETC.
LOW TEMPERATURE
LIMIT ADJUST
+-
5V
470k
R3
TEMPERATURE
SENSOR
(GENERAL PURPOSE
NPN TRANSISTOR)
10k
HIGH
TEMPERATURE
LIMIT ADJUST
R1
ICL7665S
FIGURE 16. SIMPLE HIGH/LOW TEMPERATURE ALARM
110VAC
60Hz
20V
CENTERED
TAPPED
TRANS.
4700µF
601k
100k
HYST1
VSET1 VSET2
HYST2
OUT1 OUT2
1M
1M
7805
5V REGULATOR
5V, 1A
C1
R1
1M
+5V
POWER FAIL
WARNING
ICL7665S
FIGURE 17. AC POWER FAIL AND BROWNOUT DETECTOR
FN3182 Rev 10.00 Page 13 of 15
August 10, 2015
ICL7665S
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2004-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
August 10, 2015 FN3182.10 Added Rev History beginning with Rev 10.
Added About Intersil Verbiage.
Updated Ordering Information Table on page 2.
ICL7665S
FN3182 Rev 10.00 Page 14 of 15
August 10, 2015
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
ICL7665S
FN3182 Rev 10.00 Page 15 of 15
August 10, 2015
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
8°
0°
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
