IGLOO PLUS Starter Kit User's Guide IGLOO PLUS Starter Kit User's Guide Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 IGLOO PLUS Starter Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 Board Components and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 IGLOO PLUS Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connectors, Jumpers, and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 FPGA Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Key Features of AGLP125-CSG289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decaps and Ground Post Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 20 21 3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potentiometer and Voltage-Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 26 4 Operation of Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash*Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Cost Programming Stick (LCPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 30 37 38 39 40 41 42 42 43 44 5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 IGLOO PLUS Board Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Demos Included in the Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Getting Started with the IGLOO PLUS Starter Kit Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 A Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 B List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Revision 1 3 Table of Contents C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 59 59 60 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 R e vi s i o n 1 Introduction IGLOO PLUS Starter Kit Contents The RoHS-compliant, environmentally friendly IGLOO(R) PLUS Starter Kit is packaged in a recyclable cardboard box made from recycled materials. This development kit includes an on-board programmer and demonstrates the ultra-low power of Microsemi(R) IGLOO PLUS devices. Table 1 lists the contents of the box. Table 1 * IGLOO PLUS Starter Kit Contents Quantity Contents 1 IGLOO PLUS board with AGLP125 IGLOO PLUS field programmable gate array (FPGA) 1 Programmer for use with IGLOO PLUS board 1 5 V power supply 2 USB 2.0 high-speed cables 1 Packet of jumpers 1 Microsemi Libero(R) System-on-Chip (SoC) software DVD 1 Quickstart Guide Figure 1 * IGLOO PLUS Starter Kit Board Revision 1 5 1 - Board Components and Settings This chapter describes the components and settings for the IGLOO PLUS Starter Kit Board. Board Description The IGLOO PLUS Starter Kit board is intended to provide a low-cost system platform for evaluating IGLOO PLUS (AGLP) technology, such as low power, I/O state preservation during Flash*Freeze mode, and Schmitt Triggered I/Os. Other advanced features include the ability to use the FPGA I/Os of the Expansion Header as hot-swappable and the Schmitt Triggered FPGA inputs for improved noise immunity. This evaluation board enables you to measure power consumption (dynamic, static, and Flash*Freeze modes) with the core operating between 1.2 V and 1.5 V. When using the board in conjunction with the Microsemi power analysis tools, you will have a clear picture of application power consumption at each stage in your design. In addition, the Libero SoC tool suite now includes power-driven layout (PDL), which can reduce the power consumption of designs up to 30 percent. The evaluation board has a small form factor, measuring 3.7 inches by 4 inches, and supports an AGLP125 IGLOO PLUS device in the 14 mm x 14 mm CSG289 package. All components used on the board, such as LEDs, reset (A range), and oscillator, are low-power components. Also included on the evaluation board is a USB-to-UART interface to allow HyperTerminal on a PC to communicate with the IGLOO PLUS device on the board. The top of the board has a programming stick header which allows the low-cost programming stick LCPS) to be attached to the board for programming the IGLOO PLUS AGLP125-CSG289 device (Figure 1-1). FPGA I/Os have been wired to test pin pads on the board for debug and expandability. Figure 1-1 * IGLOO PLUS Starter Kit Board Note: The clock oscillator for the IGLOO PLUS Starter Kit Board is behind the board. Revision 1 7 Board Components and Settings IGLOO PLUS Board Stackup The IGLOO PLUS board is built on a 10-layer PCB. Figure 1-1 and Figure 1-1 on page 7 show the top (L1) and bottom (L10) silkscreens. The full PCB design layout is provided on the Microsemi SoC Products Group website, on the IGLOO PLUS Starter Kit page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. To view the PCB design layout files, you can use the Allegro Free Physical Viewer, which can be downloaded from the Cadence Allegro Downloads page. 8 * Top Signal (Figure 1-1 on page 7) * GND 1 * Signal * GND 2 * PWR 1 * PWR 2 * GND 3 * Signal * GND 4 * Bottom Signal (Figure 1-2 on page 9) R e vi s i o n 1 IGLOO PLUS Starter Kit User's Guide Figure 1-2 * IGLOO PLUS Top Silkscreen (L1) Revision 1 9 Board Components and Settings Figure 1-3 * IGLOO PLUS Bottom Silkscreen (L10) 10 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Connectors, Jumpers, and Switch Settings Recommended default jumper settings are defined in Table 1-1. The voltage selection jumpers are highlighted in grey. Connect jumpers in the default settings described in Table 1-1 to enable the preprogrammed demo design to function correctly. Table 1-1 * Jumper and Connector Settings Jumper Default Setting Comment J1 Ground post header J2 Ground post header J3 LC JTAG header for programmer J4 JTAG header J5 USB mini receptacle J6 Pin 2-3 Remove jumper to disconnect VCCI_0 power J7 Remove Remove jumper to disconnect external battery source J8 Pin 2-3 Remove jumper to disconnect VCCI_1 power J9 Pin 1-4 Select WALL, BAT, VUSB for 5V_SOURCE Pin 1-4 = VUSB Pin 2-4 = BAT Pin 3-4 = WALL J10 J11 5 V Brick Pin 1-2 Select VCC or VCC_SWEEP for VCORE Pin 1-2 = VCC Pin 3-2 = VCC_SWEEP J12 Pin 2-3 Current measurement header for VCORE J13 Pin 2-3 Current measurement header for VCCI_3 J14 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_1 Pin 1-2 = VCC Pin 3-2 = VCC_SWEEP J15 Pin 3-2 Select VJTAGENB or 3.3 V Pin 3-2 = VJTAGENB Pin 1-2 = 3.3 V J16 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_1 Pin 2-4 = 3.3 V Pin 3-4 = 1.5 V or 1.2 V Pin 1-4 = 2.5 V J17 Pin 2-3 Current measurement header for VCCI_2 J18 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_0 Pin 1-2 = VCC Pin 3-2 = VCC_SWEEP Revision 1 11 Board Components and Settings Table 1-1 * Jumper and Connector Settings (continued) Jumper J19 Default Setting Pin 2-4 Comment Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_0 Pin 2-4 = 3.3 V Pin 3-4 = 1.5 V or 1.2 V Pin 1-4 = 2.5 V J20 Pin 2-3 Current measurement header for VJTAG J21 Pin 1-2 Select 3.3 V or 1.5 / 1.2 V for VJTAG Pin 1-2 = 3.3 V Pin 2-3 = 1.5 V or 1.2 V J22 Pin 2-3 Current measurement header for VPUMP J23-J24 Pin 1-2 Remove each jumper to disconnect any of the 2 FET Switches[1:2] from FPGA. J23 = 3V3_SWITCH1 J24 = 3V3_SWITCH2 J25-J27 Pin 1-2 Remove each jumper to disconnect any of the 3 FET LEDs from FPGA. J25 = FET_P1 J26 = FET_N J27 = FET_P2 J28-J35 Pin 1-2 Remove each jumper to disconnect any of the 8 user DIP switches[1:8] from FPGA. J28 = D_SWITCH1 J29 = D_SWITCH2 J30 = D_SWITCH3 J31 = D_SWITCH4 J32 = D_SWITCH5 J33 = D_SWITCH6 J34 = D_SWITCH7 J35 = D_SWITCH8 J36-J39 Pin 1-2 Remove each jumper to disconnect any of the 4 push-button switches[1:4] from FPGA. J36 = SWITCH1 J37 = SWITCH2 J38 = SWITCH3 J39 = SWITCH4 J40-J47 Pin 1-2 Remove each jumper to disconnect any of the 8 user LEDs[1:8] from FPGA. J42 = LED1 J41 = LED2 J40 = LED3 J47 = LED4 J46 = LED5 J45 = LED6 J44 = LED7 J43 = LED8 12 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Table 1-2 * Switch Settings Switch Default Setting SW1-SW4 Comment Push-button switches for SWITCH[1:4] SW5 CLOSE Contains DIP switches for 3V3_SWITCH[1:2] DSW5 CLOSE Contains DIP switches for D_SWITCH[1:8] SW7 SW8 Push-button switch for system reset PBRESET_N OFF Flash*Freeze: To enable Flash*Freeze mode, SW8 toward ON. In Flash*Freeze mode, current consumption of FPGA goes below 50 A. Revision 1 13 2 - FPGA Description The IGLOO PLUS board is populated with an IGLOO PLUS AGLP125-CSG289 FPGA. Key Features of AGLP125-CSG289 * Low power * 1.2 V to 1.5 V core voltage support for low power * Supports single-voltage system operation * 5 W power consumption in Flash*Freeze mode * Low-power active FPGA operation * Flash*Freeze technology enables ultra-low power consumption while maintaining FPGA content * Configurable hold previous state, tristate, HIGH, or LOW state per I/O in Flash*Freeze mode * Easy entry to / exit from ultra-low-power Flash*Freeze mode * Reprogrammable flash technology * In-system programming (ISP) and security * High-performance routing hierarchy * Advanced I/O * Selectable Schmitt trigger inputs * Clock conditioning circuit (CCC) and PLL * Embedded memory Table 2-1 lists specifications for the AGLP125-CSG289 FPGA. Table 2-1 * IGLOO PLUS AGLP125-CSG289 FPGA Features Feature Specification System Gates 125,000 Typical Equivalent Macrocells 1,024 VersaTiles (D-flip-flops) 3,120 Flash*Freeze Mode (Typical, W) 16 RAM kbits (1,024 bits) 36 4,608-Bit Blocks 8 FlashROM (bits) 1K Secure (AES) ISP Yes Integrated PLLs in CCCs 1 VersaNet Globals 18 I/O Banks 4 Maximum User I/Os 212 For further information, refer to the IGLOO PLUS datasheet: www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf Revision 1 15 FPGA Description Power and Ground Pins Figure 2-1 shows the power and ground pins for AGLP125-CSG289. U5E AGLP125 CSG289 SEC 5/6 VCOMPLF J1 VCCPLF L9 VCC1 G9 VCC2 J7 VCC3 J11 VCC4 B7 VCCIB0_1 B12 VCCIB0_2 VCCIB0_3 VCCIB0_4 E16 VCCIB1_1 H15 VCCIB1_2 L14 VCCIB1_3 M17 VCCIB1_4 N10 VCCIB2_1 P13 VCCIB2_2 R6 VCCIB2_3 T9 VCCIB2_4 E1 VCCIB3_1 F4 VCCIB3_2 J3 VCCIB3_3 M2 VCCIB3_4 POWER C5 E11 GND VCCPLF H1 AGLP125-CSG289 Figure 2-1 * Power and Ground Pins for AGLP125-CSG289 16 R e visio n 1 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 A4 A9 A14 B2 B17 C10 C15 D3 D8 D13 F14 G2 G7 G8 G10 G11 G17 H7 H8 H9 H10 H11 J8 J9 J10 K1 K7 K8 K9 K10 K11 K16 L4 L7 L8 L10 L11 N5 N15 P3 P8 R1 R11 T4 T14 U2 U7 U12 IGLOO PLUS Starter Kit User's Guide Bank I/O Signals Figure 2-2 through Figure 2-5 on page 19 show the schematics for the bank I/O signals. U5A AGLP125 CSG289 TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP AGL_B0_PIN_D5 D5 TP69 AGL_B0_PIN_A3 A3 IO38RSB0 A11 TP96 IO07RSB0 IO39RSB0 B11 TP116 IO08RSB0 IO40RSB0 A12 TP79 IO06RSB0 GPIOA_1 {3} TP GPIOA_3 {3} TP GPIOA_5 {3} TP GPIOA_7 {3} TP71 AGL_B0_PIN_C4 C4 IO09RSB0 IO41RSB0 D10 TP124 TP TP110 AGL_B0_PIN_D6 D6 IO10RSB0 IO42RSB0 A13 TP117 TP TP85 AGL_B0_PIN_A2 A2 IO11RSB0 IO43RSB0 C11 TP77 TP74 AGL_B0_PIN_E6 E6 IO12RSB0 IO44RSB0 B13 TP97 TP86 AGL_B0_PIN_B4 B4 IO13RSB0 IO45RSB0 C12 TP89 TP TP108 AGL_B0_PIN_F7 F7 IO14RSB0 IO46RSB0 B14 TP80 TP TP106 AGL_B0_PIN_B5 B5 IO47RSB0 D11 TP78 TP TP101 AGL_B0_PIN_E7 E7 IO16RSB0 IO48RSB0 A15 TP118 TP120 AGL_B0_PIN_C6 C6 IO17RSB0 IO49RSB0 B15 TP98 TP72 AGL_B0_PIN_D7 D7 IO18RSB0 IO50RSB0 C13 TP111 TP TP70 AGL_B0_PIN_A5 A5 IO19RSB0 IO51RSB0 F11 TP76 TP TP113 AGL_B0_PIN_F8 F8 IO52RSB0 C14 TP109 TP87 AGL_B0_PIN_B6 B6 IO21RSB0 TP114 AGL_B0_PIN_E8 E8 IO22RSB0 TP121 AGL_B0_PIN_C7 C7 IO23RSB0 IO55RSB0 TP107 AGL_B0_PIN_A6 A6 IO24RSB0 IO56RSB0 TP73 AGL_B0_PIN_F9 F9 IO25RSB0 TP115 AGL_B0_PIN_A7 A7 IO26RSB0 TP75 AGL_B0_PIN_C8 C8 IO27RSB0 IO15RSB0 IO20RSB0 GPIOA_9 {3} GPIOA_13 {3} TP GPIOA_15 {3} TP GPIOA_17 {3} GPIOA_19 {3} GPIOA_21 {3} GPIOA_23 {3} TP GPIOA_25 {3} TP GPIOA_27 {3} GPIOA_31 {3} GPIOA_33 {3} IO53RSB0 F12 TP103 TP IO54RSB0 A16 TP81 TP D12 AGL_B0_PIN_D12 TP93 TP E12 AGL_B0_PIN_E12 TP92 TP GAA0/IO00RSB0 C2 AGL_B0_PIN_C2 TP102 TP GAA1/IO01RSB0 B1 AGL_B0_PIN_B1 TP22 TP GAB0/IO02RSB0 D4 AGL_B0_PIN_D4 TP90 TP TP222 AGL_B0_PIN_F10 F10 IO29RSB0 GAB1/IO03RSB0 A1 AGL_B0_PIN_A1 TP68 TP A8 IO30RSB0 GAC0/IO04RSB0 C3 AGL_B0_PIN_C3 TP83 AGL_B0_PIN_E5 TP91 TP95 TP239 TP122 TP240 TP94 TP247 TP123 TP236 AGL_B0_PIN_A8 AGL_B0_PIN_B9 AGL_B0_PIN_E9 AGL_B0_PIN_C9 AGL_B0_PIN_D9 AGL_B0_PIN_A10 AGL_B0_PIN_E10 AGL_B0_PIN_B10 B9 IO31RSB0 GAC1/IO05RSB0 E5 E9 IO32RSB0 GBA0/IO61RSB0 C16 AGL_B0_PIN_C16 TP82 C9 IO33RSB0 GBA1/IO62RSB0 D15 AGL_B0_PIN_D15 TP84 D9 IO34RSB0 GBB0/IO59RSB0 D14 AGL_B0_PIN_D14 TP88 AGL_B0_PIN_E13 TP100 A10 IO35RSB0 GBB1/IO60RSB0 E13 E10 IO36RSB0 GBC0/IO57RSB0 A17 AGL_B0_PIN_A17 TP99 B10 IO37RSB0 GBC1/IO58RSB0 B16 AGL_B0_PIN_B16 TP119 GPIOA_29 {3} TP IO28RSB0 TP TP TP112 B8 TP TP B3 AGL_B0_PIN_B8 TP TP AGL_B0_PIN_B3 TP207 TP TP SEC 1/6 TP105 BANK0 TP GPIOA_35 {3} TP TP TP TP TP TP TP TP AGLP125-CSG289 Figure 2-2 * Bank 0 I/O Signals for AGLP125-CSG289 Revision 1 17 FPGA Description U5B AGLP125 CSG289 TP {3} GPIOA_4 TP {3} GPIOA_6 TP {3} GPIOA_8 TP {3} GPIOA_10 TP {3} GPIOA_12 TP {3} GPIOA_16 TP {3} GPIOA_18 TP {3} GPIOA_20 TP {3} GPIOA_22 TP {3} GPIOA_24 TP {3} GPIOA_26 TP {3} GPIOA_28 TP {3} GPIOA_30 TP {3} GPIOA_32 TP {3} GPIOA_34 TP {3} GPIOA_36 TP TP TP TP TP TP TP TP SEC 2/6 TP38 G13 IO64RSB1 GBA2/IO63RSB1 E14 AGL_B1_PIN_E14 TP39 TP45 D16 IO66RSB1 GBB2/IO65RSB1 E15 AGL_B1_PIN_E15 TP104 TP44 C17 GBC2/IO67RSB1 F13 AGL_B1_PIN_F13 TP42 H14 AGL_B1_PIN_H14 AGL_B1_PIN_J17 TP29 TP40 G14 TP26 IO68RSB1 IO69RSB1 GCA0/IO84RSB1 IO70RSB1 GCA1/IO83RSB1 J17 TP27 F16 IO71RSB1 GCA2/IO85RSB1 H16 AGL_B1_PIN_H16 TP33 G12 IO72RSB1 GCB0/IO82RSB1 J16 AGL_B1_PIN_J16 TP48 TP46 E17 IO73RSB1 GCB1/IO81RSB1 J13 TP17 H13 IO74RSB1 GCB2/IO86RSB1 J12 TP25 F15 IO75RSB1 G16 IO76RSB1 TP47 F17 IO77RSB1 TP32 G15 IO78RSB1 TP36 K12 TP23 J15 TP28 TP37 TP35 TP TP TP TP226 D17 BANK1 {3} GPIOA_2 TP210 AGL_B1_PIN_J13 H17 AGL_B1_PIN_H17 TP208 GCC1/IO79RSB1 H12 AGL_B1_PIN_H12 TP142 AGL_B1_PIN_K17 TP162 GCC2/IO87RSB1 K17 GDA0/IO104RSB1 M14 IO88RSB1 GDA1/IO103RSB1 M13 IO89RSB1 GDB0/IO102RSB1 N16 AGL_B1_PIN_N16 TP50 TP TP AGL_B1_PIN_M13 J14 IO90RSB1 GDB1/IO101RSB1 L13 L17 IO91RSB1 GDC0/IO100RSB1 N17 AGL_B1_PIN_N17 TP31 TP GDC1/IO99RSB1 L12 AGL_B1_PIN_L12 TP19 TP AGL_B1_PIN_L16 L16 IO92RSB1 TP21 AGL_B1_PIN_K15 K15 IO93RSB1 TP34 AGL_B1_PIN_K13 K13 IO94RSB1 TP16 AGL_B1_PIN_K14 K14 IO95RSB1 TP30 AGL_B1_PIN_M16 M16 TP18 AGL_B1_PIN_M15 M15 TP41 AGL_B1_PIN_L15 L15 IO96RSB1 IO97RSB1 IO98RSB1 AGLP125-CSG289 Figure 2-3 * Bank 1 I/O Signals for AGLP125-CSG289 U5C AGLP125 CSG289 SEC 3/6 [6] PACER_D2 P14 IO108RSB2 IO139RSB2 T8 AGL_B2_PIN_T8 [6] PACER_D0 N14 IO109RSB2 IO140RSB2 T7 AGL_B2_PIN_T7 [6] PACER_RES# R15 IO110RSB2 IO141RSB2 R8 AGL_B2_PIN_R8 IO111RSB2 IO142RSB2 U6 AGL_B2_PIN_U6 AGL_B2_PIN_T6 TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP130 AGL_B2_PIN_N12 N12 TP163 AGL_B2_PIN_P12 P12 IO112RSB2 IO143RSB2 T6 TP170 AGL_B2_PIN_M12 M12 IO113RSB2 IO144RSB2 N8 AGL_B2_PIN_N8 TP172 TP TP161 AGL_B2_PIN_R14 R14 IO114RSB2 IO145RSB2 R7 AGL_B2_PIN_R7 TP126 TP TP180 AGL_B2_PIN_T15 T15 IO115RSB2 IO146RSB2 U5 AGL_B2_PIN_U5 TP141 AGL_B2_PIN_R13 R13 IO147RSB2 T5 AGL_B2_PIN_T5 TP160 AGL_B2_PIN_U15 U15 IO117RSB2 IO148RSB2 N7 AGL_B2_PIN_N7 TP181 AGL_B2_PIN_R12 R12 IO118RSB2 IO149RSB2 U4 AGL_B2_PIN_U4 TP150 AGL_B2_PIN_N11 AGL_B2_PIN_R5 N11 IO116RSB2 IO119RSB2 IO150RSB2 R5 IO151RSB2 U3 AGL_B2_PIN_U3 IO152RSB2 P7 AGL_B2_PIN_P7 IO153RSB2 T3 AGL_B2_PIN_T3 TP139 AGL_B2_PIN_U14 U14 IO120RSB2 TP131 AGL_B2_PIN_M11 M11 IO121RSB2 TP179 AGL_B2_PIN_T13 T13 IO122RSB2 BANK2 TP IO154RSB2 P6 AGL_B2_PIN_P6 IO155RSB2 R4 AGL_B2_PIN_R4 IO156RSB2 N6 AGL_B2_PIN_N6 IO157RSB2 P5 AGL_B2_PIN_P5 IO127RSB2 IO158RSB2 R3 AGL_B2_PIN_R3 IO128RSB2 IO159RSB2 M7 AGL_B2_PIN_M7 IO129RSB2 IO160RSB2 P4 AGL_B2_PIN_P4 R10 IO130RSB2 IO161RSB2 M8 AGL_B2_PIN_M8 T10 IO131RSB2 TP159 AGL_B2_PIN_U13 U13 IO123RSB2 TP138 AGL_B2_PIN_T12 T12 IO124RSB2 TP148 AGL_B2_PIN_P10 P10 TP140 AGL_B2_PIN_P11 P11 TP178 AGL_B2_PIN_T11 T11 TP127 AGL_B2_PIN_M10 M10 TP158 AGL_B2_PIN_U11 U11 TP169 AGL_B2_PIN_R10 TP157 AGL_B2_PIN_T10 TP147 AGL_B2_PIN_P9 TP137 AGL_B2_PIN_U10 TP168 IO125RSB2 IO126RSB2 P9 IO132RSB2 U10 IO133RSB2 GDA2/IO105RSB2 P15 AGL_B2_PIN_P15 AGL_B2_PIN_R9 R9 IO134RSB2 GDB2/IO106RSB2 N13 AGL_B2_PIN_N13 TP129 AGL_B2_PIN_M9 M9 IO135RSB2 GDC2/IO107RSB2 P16 AGL_B2_PIN_P16 TP177 AGL_B2_PIN_U9 U9 IO136RSB2 GEA2/IO164RSB2 R2 AGL_B2_PIN_R2 TP149 AGL_B2_PIN_N9 N9 IO137RSB2 FF/GEB2/IO163RSB2 U1 TP136 AGL_B2_PIN_U8 U8 IO138RSB2 GEC2/IO162RSB2 T2 AGLP125-CSG289 Figure 2-4 * Bank 2 I/O Signals for AGLP125-CSG289 18 R e visio n 1 AGL_B2_PIN_T2 TP TP TP TP TP183 AGL_B1_PIN_L13 TP24 TP49 TP TP GCC0/IO80RSB1 AGL_B1_PIN_M14 TP20 TP TP TP223 AGL_B1_PIN_J12 TP43 TP TP TP TP156 TP TP176 TP TP167 TP TP155 TP TP135 TP TP175 TP TP174 TP TP152 TP TP154 TP TP125 TP TP134 TP TP287 TP TP153 TP TP288 TP TP289 TP TP151 TP TP145 TP164 TP TP132 TP TP144 TP TP171 TP TP143 TP TP182 TP TP128 TP TP133 TP IGLOO_FF [6] TP173 TP TP IGLOO PLUS Starter Kit User's Guide U5D AGLP125 CSG289 SEC 4/6 AGL_B3_PIN_P2 P2 IO171RSB3 GAA2/IO211RSB3 E4 AGL_B3_PIN_E4 TP235 AGL_B3_PIN_M4 M4 IO172RSB3 GAB2/IO209RSB3 F5 AGL_B3_PIN_F5 TP203 TP AGL_B3_PIN_L5 L5 IO173RSB3 GAC2/IO207RSB3 E3 AGL_B3_PIN_E3 TP218 TP AGL_B3_PIN_P1 P1 IO174RSB3 GEA0/IO165RSB3 N4 AGL_B3_PIN_N4 TP245 TP AGL_B3_PIN_K5 K5 IO175RSB3 GEA1/IO166RSB3 T1 AGL_B3_PIN_T1 TP227 TP AGL_B3_PIN_M3 M3 IO176RSB3 GEB0/IO167RSB3 M5 AGL_B3_PIN_M5 TP248 TP AGL_B3_PIN_K6 K6 GEB1/IO168RSB3 M6 AGL_B3_PIN_M6 TP215 TP AGL_B3_PIN_N2 N2 GEC0/IO169RSB3 N3 AGL_B3_PIN_N3 TP214 TP GEC1/IO170RSB3 L6 AGL_B3_PIN_L6 TP249 TP K2 AGL_B3_PIN_K2 TP209 TP TP224 TP K4 N1 IO177RSB3 IO178RSB3 IO179RSB3 IO180RSB3 GFA0/IO189RSB3 TP J6 IO181RSB3 GFA1/IO190RSB3 J2 AGL_B3_PIN_J2 AGL_B3_PIN_L3 L3 IO182RSB3 GFA2/IO188RSB3 L1 AGL_B3_PIN_L1 TP225 TP AGL_B3_PIN_J5 J5 IO183RSB3 GFB0/IO191RSB3 H2 AGL_B3_PIN_H2 TP241 TP M1 IO184RSB3 GFB1/IO192RSB3 H6 AGL_B3_PIN_H6 TP206 TP AGL_B3_PIN_J4 J4 IO185RSB3 GFB2/IO187RSB3 K3 AGL_B3_PIN_K3 AGL_B3_PIN_H3 H3 IO195RSB3 GFC0/IO193RSB3 G1 AGL_B3_PIN_G1 F2 IO196RSB3 GFC1/IO194RSB3 F1 OSC_CLK AGL_B3_PIN_H4 H4 IO197RSB3 GFC2/IO186RSB3 L2 PBRESET_N [6] AGL_B3_PIN_G3 G3 IO198RSB3 AGL_B3_PIN_H5 H5 IO199RSB3 E2 IO200RSB3 G5 IO201RSB3 F3 IO202RSB3 G4 IO203RSB3 D1 IO204RSB3 D2 IO205RSB3 AGL_B3_PIN_G6 G6 IO206RSB3 AGL_B3_PIN_F6 F6 IO208RSB3 C1 IO210RSB3 AGL_B3_PIN_G5 AGL_B3_PIN_G4 BANK3 AGL_B3_PIN_J6 TP213 TP TP242 TP [6] AGLP125-CSG289 Figure 2-5 * Bank 3 I/O Signals for AGLP125-CSG289 Revision 1 19 FPGA Description JTAG Pins The AGLP125-CSG289 has advanced I/O features such as JTAG pins for IEEE 1149.1 JTAG Boundary Scan Test. These pins are utilized during programming of the FPGA (Figure 2-6). Low-power flash devices have a separate bank for these dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used or planned for use, the VJTAG pin together with the TRST pin could be tied to GND. VJTAG is the ability to switch between 3.3 V and 1.5 V / 1.2 V source using jumper J21. Four-pin headers can be used for current measurement of the VJTAG and VPUMP rails. U5F AGLP125 CSG289 SEC 6/6 TCK U16 TCK [6] TDI T16 TDI [6] TMS R16 TMS [6] TRST R17 TRST [6] JTAG TDO T17 VJTAG VPUMP R48 39 TDO [6] P17 VJTAG [6] U17 VPUMP [6] VJTAG [6] VPUMP [6] AGLP125-CSG289 J20 HDR_4PIN V3P3 J21 1V5_1V2 2 1 4 3 1 2 3 HDR_3PIN J22 HDR_4PIN Figure 2-6 * JTAG Pins 20 R e visio n 1 2 1 4 3 V3P3 IGLOO PLUS Starter Kit User's Guide Decaps and Ground Post Schematics The schematics for the decaps and ground post are shown in Figure 2-7. DECAPS FOR VCORE C31 10uF 16V C47 0.01uF C49 C45 0.01uF + 0.01uF C40 0.1uF VCORE DECAPS FOR I/O BANK0 , BANK1 ,BANK2 & BANK3 C51 C46 0.01uF 0.01uF C53 C38 0.1uF + 10uF 16V C41 0.1uF C57 0.01uF C54 C58 0.01uF + 10uF 16V C56 VCCI_3 0.1uF C55 10uF 16V 0.1uF C43 C44 0.01uF C52 C48 0.1uF + 0.01uF C36 C28 0.01uF VCCI_2 0.1uF C27 0.01uF C33 C30 0.1uF + 10uF 16V C29 VCCI_1 0.1uF VCCI_0 GROUND POST J2 J1 1 1 HEADER 1 HEADER 1 Figure 2-7 * Schematics for Decaps and Ground Post Revision 1 21 3 - Power The IGLOO PLUS development board is powered through an external voltage power brick or USB. The board does not switch seamlessly between the power brick and USB, so the 4-pin header and jumper must be used to select the desired power source. In the USB option, the in-rush current meets the USB specifications (see Figure 3-1). The power brick option is provided in applications when 100% of the total I/Os are utilized and USB power is insufficient. A green LED next to the USB jack is ON whenever the USB power supply is connected. The development board has an input of a 5 V supply from the power brick or USB. Protection diodes are used to protect against negative voltage. Three voltage rails are provided, as shown in Table 3-1 (3.3 V, 2.5 V, and 1.5 V). The regulator can be switched between the 1.5 V and 1.2 V rail because the FPGA core functions at 1.2 V, but is programmed at 1.5 V. Table 3-1 * Power Regulator Current Ratings Regulator Current Rating 3.3 V 2A 2.5V 1A 1.5 V / 1.2 V 500 mA Manufacturer = CUI INC Mfg P/N = PJ-002AH CONN JACK PWR WALL 1 3 2 5V BRICK 5V_SOURCE J9 J10 5V 3 BAT 5V_USB 2 Q2 4 VUSB C5 C8 C6 C7 0.1uF 0.1uF R8 220K R0402 R4 2.7K R5 R0402 22 OHM R0402 C4 0.027UF C3 6 5 2 1 C0402 3 R65 10K 4PIN_HEADER Si3407DV D10 2 1 0.1uF Q1 ONLY INSTALLED ON FACTORY DEMO 1 BAT54 0.1uF Q1 4 3 3 0.1uF R6 22 OHM R0402 4 VUSB 6 5 2 1 SI3407DV ACTIVE INRUSH LIMITER Figure 3-1 * USB Active Inrush Limiter Revision 1 23 Power Power Modes In addition to the board, the IGLOO PLUS FPGA offers power advantages. Some key power advantages of the IGLOO PLUS FPGAs are as follows: * Flash*Freeze technology enables easy entry and exit from the static Low-power mode, where IGLOO consumes as little as 5 W while retaining the contents of the system memory and data registers. * Sleep (and shutdown) mode allows the IGLOO PLUS FPGA core power supply (or all power supplies) to be powered down when functionally is not required, while the rest of the system remains powered. * The user low static ICC macro (ULSICC) reduces IGLOO PLUS FPGA dynamic and static power consumption. The ULSICC macro, when enabled, disables the FlashROM, reducing the overall power of the device. Table 3-2 gives a summary of the power modes available with IGLOO PLUS devices in general and is extracted from the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS FPGA Fabric User's Guide. Table 3-2 * Power Modes Mode VCC VCCI Core Clocks ULSICC Macro To Enter Mode Active On On On On N/A Idle On On On Off Flash*Freeze Type 1 On On On Flash*Freeze Type 2 On On Sleep On Shutdown Off Static To Resume Operation Trigger Initiate clock None - N/A Stop clock Initiate clock External On* N/A Assert FF pin Deassert FF pin External On Ona Used to enter Flash*Freeze mode Assert FF pin and LSICC Deassert FF pin External Off Off Off N/A Shut down VCC Turn on VCC supply External Off Off Off N/A Shut down VCCand VCCI supplies Turn on VCC and VCCI supplies External a. External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL will be turned off automatically. 24 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Battery In addition to the power brick and USB, this board provides the option to power-up via battery. No battery casing is provided on the board. Jumpers should be set correctly to select the option of either powering through a wall/USB or through batteries hooked up externally. To provide a 3 V input source from battery, two AA Alkaline cells may be used. A 2-pin jumper for VBAT and GND must be provided to the input of the main regulator to give the option of either powering through a wall/USB or powering through batteries hooked up externally. J7 BAT 1 2 EXTERNAL BATTERY SOURCE BATTERY 1x2_100MIL Figure 3-2 * Battery Header and Power Input Schematics Potentiometer and Voltage-Sweep A potentiometer is located on the left hand side of the board to provide the voltage-sweep function to sweep VCC (Figure 3-3). One primary function of the potentiometer is to show battery operation on the IGLOO PLUS device and how the FPGA can operate successfully even if VCC experiences a drop in voltage. You can measure the lowest possible VCC for battery operations. When using the potentiometer, you should also monitor the VCC via current measurement headers (Figure 3-4 on page 26) to make sure it does not go beyond the specified value. Current Measurement 3.3 V IGLOO PLUS 3.3 V VCCI_0 3.3 V VCCI_1 2.5 V VCCI-Sweep VCCI_2 VCCI_3 1.5 V VCC VCCI-Sweep VCCI-Sweep 3.3 V VJTAG 3.3 V VPUMP Figure 3-3 * Current Measurement Headers Revision 1 25 Power 1 1V5_1V2 2 VCC_SWEEP 5K pot 3 1uF C35 RV1 Figure 3-4 * Schematic for Potentiometer Current Measurement Once the IGLOO PLUS evaluation board is powered up, you can evaluate power consumption using the current measurement four-pin headers on the board (Figure 3-5). Current measurement can be made without powering down the board. Set the multimeter to measure current and attach the probes to pins 1 and 4 when the board is in normal operation. Remove jumper from pins 2-3 for current measurement without powering down. Figure 3-5 * Current Measurement 4-Pin Headers Four-pin headers are used for current measurement of the rails shown in Figure 3-6 on page 27. All banks are separated and two of the banks have an option to power-up though a 3.3 V or 2.5 V source, as shown in Figure 3-7 on page 27. Voltage sources can be selected using jumpers or can be selected to sweep between 1.2 V and 1.5 V using the potentiometer on the development board. 26 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Current Measurement IGLOO PLUS 3.3 V VCCI_0 3.3 V VCCI_1 3.3 V or 2.5 V VCCI_2 3.3 V or 2.5 V VCCI_3 1.5 V VCC 3.3 V VJTAG 3.3 V VPUMP Figure 3-6 * Current Measurement Headers for Power Rails The schematic in Figure 3-7 shows the options for power-up. J12 HDR_4PIN 1V5_1V2 J11 VCORE 4 3 1V5_1V2 J19 2 1 1 2 3 V3P3 VCC_SWEEP 3 4 J6 HDR_4PIN HDR_3PIN J18 2V5 VCCI_0 4 3 2 4PIN_HEADER 1V5_1V2 J16 3 VCC_SWEEP 3 J8 HDR_4PIN HDR_3PIN J14 V3P3 2 2 1 1 1 4 VCCI_1 1 4 3 2V5 2 1 2 2 1 3 VCC_SWEEP J17 HDR_4PIN 4PIN_HEADER HDR_3PIN VCCI_2 2 1 4 3 V3P3 J13 HDR_4PIN VCCI_3 2 1 4 3 V3P3 Figure 3-7 * Power-Up Options Revision 1 27 4 - Operation of Board Components This chapter describes operation of the IGLOO PLUS evaluation board. Clock Oscillator One 20 MHz clock oscillator with 50 PPM is provided on the board. This clock oscillator is connected to the FPGA to provide a system or reference clock. The PLL can be configured and instantiated in the FPGA to generate a wide range of clock frequencies. Reference For more information, refer to the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. Schematic Figure 4-1 shows the schematic for the clock oscillator. V3P3 U10 0.1uF C39 4 VDD OUTPUT 3 R64 OSC_CLK [4] 22 R43 10K 1 OUT_EN GND 2 OSCILLATOR Mfg P/N = SIT8002AC-43-33E Manufacturer = SI TIME Figure 4-1 * Clock Oscillator Schematic Reset An RC type push-button reset switch to the FPGA is provided on-board. The Schmitt Trigger chip (U13), however, is NOT populated. An on-board Schmitt Trigger chip is not required because Schmitt Trigger is one of the many advanced I/O features of the IGLOO PLUS FPGA family. To improve noise immunity, ensure that the Schmitt Trigger option for this reset input pin is enabled in the FPGA design. If the IGLOO PLUS FPGA is swapped out with a device that does not have the advance Schmitt Trigger I/O feature, the Schmitt Trigger chip (U13) should be populated. Revision 1 29 Operation of Board Components Schematic Figure 4-2 shows the schematic for reset. V3P3 V3P3 R62 10K U13 2 C65 VCC RST 0.1uF 3 R63 1 PBRESET_N [4] 0 GND DNP RST Mfr P/N :DS1818R-20+T&R Mfr: Dallas 0.1uF C66 SW7 2 1 4 3 KSC403J Mfr P/N :KSC403J 50SH LFG Mfr:ITT INDUSTRIES Figure 4-2 * Reset Schematic Flash*Freeze Mode The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation (Figure 4-1). Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks can still be driven and can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or can be tristated during Flash*Freeze mode. IGLOO PLUS FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 4-3 * Flash*Freeze Mode Control There are two ways to use Flash*Freeze mode. In Flash*Freeze type 1, entering and exiting the mode is exclusively controlled by the assertion and deassertion of the FF pin. This enables an external processor or human interface device to directly control Flash*Freeze mode. In Flash*Freeze mode type 2, entering and exiting the mode is controlled by both the FF pin AND user-defined logic. Flash*Freeze management IP can be used in type 2 mode for clock and data management while entering and exiting Flash*Freeze mode. For more information and detailed usage of Flash*Freeze modes, refer to the "Microsemi's Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS FPGA Fabric User's Guide. 30 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Flash*Freeze Types Type 1: Controlled by dedicated Flash*Freeze Pin. Type 2: Controlled by dedicated Flash*Freeze Pin and Internal Logic. Flash*Freeze Type 1: Controlled by Dedicated Flash*Freeze Pin Flash*Freeze type 1 is intended for systems where either the device is reset upon exiting Flash*Freeze mode, or data and clock are managed externally. The device enters Flash*Freeze mode 1 s after the dedicated FF pin is asserted (active low), and returns to normal operation when the FF pin is deasserted (high). In this mode, FF pin assertion or deassertion is the only condition that determines entering or exiting Flash*Freeze mode (Figure 4-4). An INBUF_FF I/O buffer macro must be used to identify the Flash*Freeze input in your design. IGLOO, IGLOO PLUS, IGLOO nano, ProASIC3L, or RT ProASIC3 Device INBUF_FF Flash*Freeze Mode Control To FPGA Core or Floating Flash*Freeze (FF) Pin Flash*Freeze Signal Enables Entering Flash*Freeze Mode 1 AND Flash*Freeze Mode Flash*Freeze Technology User Design Figure 4-4 * Flash*Freeze Mode Type 1 - Controlled by the Flash*Freeze Pin Normal Operation Normal Operation Flash*Freeze Mode Flash*Freeze Pin t = 1 s t = 1 s Figure 4-5 * Flash*Freeze Mode Type 1 - Timing Diagram Revision 1 31 Operation of Board Components Flash*Freeze Type 2: Controlled by Dedicated Flash*Freeze Pin and Internal Logic The device can be made to enter Flash*Freeze mode by activating the FF pin together with the Flash*Freeze management IP core or user-defined control logic (Figure 4-6) within the FPGA core. This method enables the design to perform important activities before allowing the device to enter Flash*Freeze mode, such as transitioning into a safe state, completing the processing of a critical event. Designers are encouraged to take advantage of the Flash*Freeze Management IP of Microsemi to handle clean entry and exit of Flash*Freeze mode. The device will only enter Flash*Freeze mode when the Flash*Freeze pin is asserted (active low) and the User Low Static ICC (ULSICC) macro input signal, called the LSICC signal, is asserted (high). One condition is not sufficient to enter Flash*Freeze mode type 2; both the FF pin and LSICC signal must be asserted. Figure 4-7 shows the timing diagram for entering and exiting Flash*Freeze mode type 2. After exiting Flash*Freeze mode type 2 by deasserting the Flash*Freeze pin, the LSICC signal must be deasserted by the user design. This will prevent entering Flash*Freeze mode by asserting the Flash*Freeze pin only. Refer to Figure 4-1 on page 29 for Flash*Freeze (FF) pin and LSICC signal assertion and deassertion values. IGLOO, IGLOO PLUS, IGLOO nano, ProASIC3L, or RT ProASIC3 Device Flash*Freeze (FF) Pin Connect to Top-Level Port Auto-Connected to IP INBUF_FF Flash*Freeze Signal Enables Entering Flash*Freeze Mode ULSICC Macro Flash*Freeze Management IP AND Flash*Freeze Mode Flash*Freeze Technology User Design Figure 4-6 * Flash*Freeze Mode Type 2 - Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal) 32 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Normal Operation Flash*Freeze Mode Normal Operation Flash*Freeze Pin LSICC Signal t = 1 s t = 1 s Figure 4-7 * Flash*Freeze Mode Type 1 and Type 2 - Signal Assertion and Deassertion Values Table 4-1 * Flash*Freeze Mode Type 1 and Type 2 - Signal Assertion and Deassertion Values Signal Assertion Value Deassertion Value Flash*Freeze (FF) pin Low High LSICC signal High Low Note: 1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal. 2. The LSICC signal is used only in Flash*Freeze mode type 2. IGLOO PLUS I/O State in Flash*Freeze Mode In IGLOO PLUS devices, users have multiple options in how to configure I/Os during Flash*Freeze mode: 1. Hold the previous state. 2. Set I/O pad to weak pull-up or pull-down. 3. Tristate I/O pads. The I/O configuration must be configured by the user in the I/O Attribute Editor or in a PDC constraint file, and can be done on a pin-by-pin basis. The output hold feature will hold the output in the last registered state, using the I/O pad weak pull-up or pull-down resistor when the FF pin is asserted. When inputs are configured with the hold feature enabled, the FPGA core side of the input will hold the last valid state of the input pad before the device entered Flash*Freeze mode. The input pad can be driven to any value, configured as tristate, or configured with the weak pull-up or pull-down I/O pad feature during Flash*Freeze mode, without affecting the hold state. If the weak pull-up or pull-down feature is used without the output hold feature, the input and output pads will maintain the configured weak pull-up or pull-down status during Flash*Freeze mode and normal operation. If a fixed weak pull-up or pull-down is defined on an output buffer or as bidirectional in output mode, and a hold state is also defined for the same pin, the pin will be configured in hold state mode during Flash*Freeze mode. During normal operation, the pin will be configured with the predefined weak pull-up or pull-down. Any I/Os that do not use the hold state or I/O pad weak pull-up or pull-down features will be tristated during Flash*Freeze mode and the FPGA core will be driven high by inputs. Inputs that are tristated during Flash*Freeze mode may be left floating without any reliability concern or impact to power consumption. Revision 1 33 Operation of Board Components Table 4-2 shows the I/O pad state based on the configuration and buffer type. Table 4-2 * IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)--I/O Pad State Buffer Type Input Output Bidirectional / Tristate Buffer E=0 (input/tristate) E = 1 (output) Hold State I/O Pad Weak Pull-Up/-Down I/O Pad State in Flash*Freeze Mode Enabled Enabled Weak pull-up/pull-down 1 Disabled Enabled Weak pull-up/pull-down 2 Enabled Disabled Tristate 1 Disabled Disabled Tristate 2 Enabled "Don't care" Weak pull to hold state Disabled Enabled Weak pull-up/pull-down Disabled Disabled Tristate Enabled Enabled Weak pull-up/pull-down 1 Disabled Enabled Weak pull-up/pull-down 2 Enabled Disabled Tristate 1 Disabled Disabled Tristate 2 Enabled "Don't care" Weak pull to hold state 3 Disabled Enabled Weak pull-up/pull-down Disabled Disabled Tristate Note: 1) Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode. 2) Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode. 3) For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state. 34 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Flash*Freeze Switch An F*F switch is provided on the board for designs that utilize the Flash*Freeze technology. Setting the F*F switch to FF_ON will enable the Flash*Freeze mode of the IGLOO PLUS device. Since the Schmitt Trigger chip (U12) is NOT populated on-board for the F*F switch, the Schmitt Trigger feature should be enabled in the FPGA design for the Flash*Freeze input to enhance noise immunity (Figure 4-8). The Schmitt Trigger is an advanced I/O feature of the IGLOO PLUS FPGA family. If the IGLOO PLUS FPGA is swapped out with a device that does not have the advanced Schmitt Trigger I/O feature, the Schmitt Trigger chip (U12) should be populated. V3P3 V3P3 R61 10K R52 C61 0 SW8 U12 3 0.1uF Mfr P/N :AYZ0102AGRL Mfr: ITT INDUSTRIES 2 2.2uF C63 C62 + 0.1uF C64 + 10uF 1 AYZ0102AGRL 1 NC 2 A 3 GND VCC 5 Y 4 IGLOO_FF [4] DNP Mfg P/N = SN74AUP1G17DCKR Manufacturer = TI Figure 4-8 * Flash*Freeze Schematic, Schmitt Triggered Some features on this board are included to demonstrate the Flash*Freeze variants of the IGLOO PLUS FPGA. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state (high or low) using weak pull-up or pull-down I/O attribute configurations. These Flash*Freeze variants can be demonstrated by configuring the I/Os in Designer and using switches as inputs to control the FET LEDs. Refer to the demo design, which provides additional details on demonstrating these Flash*Freeze variants ("IGLOO PLUS Board Demo" on page 51). Flash*Freeze Variant Dip Switch Two regular DIP switches are located on the board, next to the FET LEDs (Figure 4-9). The DIP switches can be programmed to help debug or demonstrate the Flash*Freeze variants. Refer to the demo design that demonstrates the Flash*Freeze variants with these switches. [4] 3V3_SWITCH1 R20 10K R22 10K [4] 3V3_SWITCH2 SW5 [4] 3V3_SWITCH1 1 3 [4] 3V3_SWITCH2 2 4 R19 DNL R21 DNL 76SB02ST D12 LO T67K-L1M2-24-Z_DNL D11 LO T67K-L1M2-24-Z_DNL Figure 4-9 * Two I/Os Controlled through DIP Switch Toggling High or Low Revision 1 35 Operation of Board Components Flash*Freeze Variant FET LEDs These FET LEDs can be used for debugging, such as for viewing the state of I/Os in Flash*Freeze mode. These LEDs can be activated (ON) before entering Flash*Freeze mode, and have the ability to remain activated (ON) in Flash*Freeze mode. In low-power or Flash*Freeze mode, the FET LEDs can continue to function normally. There is one N-Type FET LED and two P-Type FET LEDs on the board (Figure 4-10). Refer to "Demo 4 - Flash*Freeze Variant: Configuration Settings of Demo Design" on page 52, which will help demonstrate the Flash*Freeze variants. P TYPE FET 1 FET_P1 [4] FET_P2 N TYPE FET V3P3 R50 1.5K [4] FET_N Figure 4-10 * FET LEDs for Debugging R e visio n 1 S 1 G 2 D D15 LO T67K-L1M2-24-Z Q5 MOSFET_NTYPE Mfg P/N = FDV301N Manufacturer = FairChild 36 S MOSFET_PTYPE Mfg P/N = FDV304P Manufacturer = FairChild D14 LO T67K-L1M2-24-Z D13 LO T67K-L1M2-24-Z MOSFET_PTYPE Mfg P/N = FDV304P Manufacturer = FairChild 3 G R51 1.5K G R49 1.5K 2 3 V3P3 D S D 2 Q6 V3P3 1 Q4 3 [4] IGLOO PLUS Starter Kit User's Guide Push-Button Switches Four active low push-button switches are provided on the board for debug purposes. You can remove the corresponding jumpers to detach or isolate any of the four push-button test switches from the FPGA I/O. Schematics are shown in Figure 4-11 and Figure 4-12. SW1 SW2 1 2 1 3 4 3 SWITCH1 KSC403J [4] 2 4 KSC403J Mfr P/N :KSC403J 50SH LFG Mfr:ITT INDUSTRIES SWITCH2 [4] Mfr P/N :KSC403J 50SH LFG Mfr:ITT INDUSTRIES SW4 SW3 1 2 3 4 1 SWITCH3 KSC403J 2 4 3 [4] KSC403J SWITCH4 [4] Mfr P/N :KSC403J 50SH LFG Mfr:ITT INDUSTRIES Mfr P/N :KSC403J 50SH LFG Mfr:ITT INDUSTRIES V3P3 R23 10K R32 10K R33 R34 10K 10K SWITCH1 [4] SWITCH2 [4] SWITCH3 [4] SWITCH4 [4] Figure 4-11 * Push-Button Switches Schematic 1 2 J39 HDR1X2 1 2 J23 HDR1X2 1 2 J38 HDR1X2 J37 HDR1X2 1 2 1 2 J36 HDR1X2 SWITCH1 [6] SWITCH2 [6] SWITCH3 [6] SWITCH4 [6] 3V3_SWITCH1 [8] Figure 4-12 * Jumper Header Schematic for Push-Button Switches Revision 1 37 Operation of Board Components .DIP Switches A DIP switch pack (8 switches) is provided on the board (Figure 4-13 and Figure 4-14). You can remove the corresponding jumpers to detach or isolate any of the eight DIP Switches from the FPGA I/Os.. DSW5 1 16 D_SWITCH1 [4] 2 15 D_SWITCH2 [4] 3 14 D_SWITCH3 [4] 4 13 D_SWITCH4 [4] 5 12 D_SWITCH5 [4] 6 11 D_SWITCH6 [4] 7 10 D_SWITCH7 [4] 8 9 D_SWITCH8 [4] DIP_SWITCH Mfg P/N = 76SB08ST Manufacturer = GRAYHILL Inc V3P3 R60 4.7K R59 4.7K R58 4.7K R57 4.7K R56 4.7K R55 4.7K R54 4.7K R53 4.7K D_SWITCH1 [4] D_SWITCH2 [4] D_SWITCH3 [4] D_SWITCH4 [4] D_SWITCH5 [4] D_SWITCH6 [4] D_SWITCH7 [4] D_SWITCH8 [4] Figure 4-13 * DIP Switches Schematic J32 HDR1X2 2 1 J34 HDR1X2 Figure 4-14 * Jumper Header Schematic for DIP Switches 38 D_SWITCH1 [6] D_SWITCH2 [6] D_SWITCH3 [6] D_SWITCH4 [6] D_SWITCH5 [6] D_SWITCH6 [6] D_SWITCH7 [6] D_SWITCH8 [6] 2 1 J35 HDR1X2 2 1 J33 HDR1X2 2 1 J31 HDR1X2 2 1 2 1 J30 HDR1X2 2 1 2 1 J28 HDR1X2 J29 HDR1X2 R e visio n 1 IGLOO PLUS Starter Kit User's Guide User LEDs Eight active low debug LEDs are provided on the board (Figure 4-15 and Figure 4-16). You can remove the corresponding jumpers from the 8 x 2 headers to detach or isolate any of the eight LEDs from the FPGA I/Os. V3P3 R24 [4] D1 LED1 1.5K LO T67K-L1M2-24-Z R25 [4] D2 LED2 1.5K LO T67K-L1M2-24-Z R26 [4] D3 LED3 1.5K LO T67K-L1M2-24-Z R27 [4] D4 LED4 1.5K LO T67K-L1M2-24-Z Mfr P/N :LO T67K-L1M2-24-Z Mfr: Osram Opto Semiconductors Inc V3P3 R28 [4] D5 LED5 1.5K LO T67K-L1M2-24-Z R29 [4] D6 LED6 1.5K LO T67K-L1M2-24-Z R30 [4] D7 LED7 1.5K LO T67K-L1M2-24-Z R31 [4] D8 LED8 1.5K LO T67K-L1M2-24-Z Figure 4-15 * User LEDs Schematic J32 HDR1X2 2 1 J34 HDR1X2 D_SWITCH1 [6] D_SWITCH2 [6] D_SWITCH3 [6] D_SWITCH4 [6] D_SWITCH5 [6] D_SWITCH6 [6] D_SWITCH7 [6] D_SWITCH8 [6] 2 1 J35 HDR1X2 2 1 J33 HDR1X2 2 1 J31 HDR1X2 2 1 2 1 J30 HDR1X2 2 1 2 1 J28 HDR1X2 J29 HDR1X2 Figure 4-16 * Jumper Header Schematic for User LEDs Revision 1 39 Operation of Board Components I/O Test Pins All IGLOO PLUS FPGA I/Os are available on headers located on the top and bottom of the device (Figure 4-17 and Figure 4-18). These test pins are multiples of 100 mils apart, so developers can easily attach headers and place an extension card on top with an off-the-shelf breadboard for a low-cost solution for integration. In order to use I/Os assigned to the LEDs, DIP Switches, and push-button switches, the 2-pin jumper on their path must be removed first to disconnect the assignment. IO_B0 GND IO_B1 100 mils x N (N = 1, 2, 3, 4, ...) IGLOO PLUS IO_B2 GND IO_B3 Figure 4-17 * I/O Test Pins TP307 TP TP308 TP TP322 TP TP318 TP TP319 TP TP320 TP TP321 TP TP326 TP TP323 TP TP324 TP TP325 TP TP313 TP TP309 TP TP310 TP TP311 TP TP312 TP TP317 TP TP314 TP TP315 TP TP316 TP TP290 TP TP291 TP TP302 TP TP298 TP TP299 TP TP300 TP TP301 TP TP306 TP TP303 TP TP304 TP TP305 TP TP293 TP TP328 TP TP165 TP TP327 TP TP292 TP TP297 TP TP294 TP TP295 TP TP296 TP TP279 TP TP280 TP TP62 TP TP58 TP TP59 TP TP60 TP TP61 TP TP66 TP TP200 TP TP64 TP TP65 TP TP53 TP TP63 TP TP67 TP TP51 TP TP52 TP TP57 TP TP54 TP TP55 TP TP56 TP TP281 TP TP282 TP TP286 TP TP283 TP TP284 TP TP285 TP TP274 TP TP270 TP TP271 TP TP272 TP TP273 TP TP278 TP TP275 TP TP276 TP TP277 TP TP251 TP TP250 TP TP197 TP TP193 TP TP194 TP TP195 TP TP196 TP TP201 TP TP198 TP TP199 TP TP202 TP TP188 TP TP185 TP TP184 TP TP186 TP TP187 TP TP192 TP TP189 TP TP190 TP TP191 TP TP265 TP TP261 TP TP262 TP TP263 TP TP264 TP TP268 TP TP266 TP TP267 TP TP269 TP TP256 TP TP253 TP TP252 TP TP254 TP TP255 TP TP260 TP TP257 TP TP258 TP TP259 TP V3P3 1V5_1V2 2V5 TP5 TP TP3 TP TP1 TP TP13 TP TP11 TP TP12 TP Figure 4-18 * I/O Test Pins Schematic 40 R e visio n 1 TP6 TP TP9 TP TP8 TP IGLOO PLUS Starter Kit User's Guide OLED A 96 x 16 pixel low-power blue organic light emitting diode (OLED) is available on the board above the IGLOO PLUS FPGA (Figure 4-19). The OLED features a serial I2C interface, and is capable of displaying sharp images or text. The demo design included in this kit contains a roulette game that uses the OLED for display and the push-button switch for game control. Additional OLED info is available at the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. V3P3 VP_10V U3 V3P3 + C21 4.7uF 16V C19 C20 0.01uF R37 2M 30 29 28 11 12 13 VCC VCOMH IREF VDD BS1 BS2 1 8 9 10 14 31 NC1 NC2 NC3 NC4 NC5 NC6 1uF 3 4 5 6 7 TEST5 TEST4 TEST3 TEST2 TEST1 2 VSS D7 D6 D5 D4 D3 D2 D1 D0 27 26 25 24 23 22 21 20 RD# WR# D/C# RES# CS# 19 18 17 16 15 R36 10K R35 10K SDA SCL PACER_D2 [4] PACER_D0 [4] PACER_RES# [4] PMO13701 Mfr P/N :PMO13701 Mfr: PACER Figure 4-19 * OLED Display Schematic Revision 1 41 Operation of Board Components Interface Connector A standard interface connector on the board can be used to connect additional daughter cards, some of which are developed by partners and third party vendors (Figure 4-20). The interface possibilities are numerous, such as flash and SRAM memory interfaces, keyboard interfaces for embedded applications, LCD interfaces, and motor control interfaces. GPIOA_1, GPIOA_2, GPIOA_4, and GPIOA_31 pins can be used for critical signals, such as clock and reset, because proper series termination has been provided on these signal lines. V3P3 VUSB J48 {3} {3} {3} {3} {3} GPIOA_1 GPIOA_3 GPIOA_5 GPIOA_7 GPIOA_9 1 3 5 7 9 11 13 2 4 6 8 10 12 14 {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} {3} GPIOA_13 GPIOA_15 GPIOA_17 GPIOA_19 GPIOA_21 GPIOA_23 GPIOA_25 GPIOA_27 GPIOA_29 GPIOA_31 GPIOA_33 GPIOA_35 17 19 21 23 25 27 29 31 33 35 37 39 18 20 22 24 26 28 30 32 34 36 38 40 GPIOA_2 {3} GPIOA_4 {3} GPIOA_6 {3} GPIOA_8 {3} GPIOA_10 {3} GPIOA_12 {3} GPIOA_16 GPIOA_18 GPIOA_20 GPIOA_22 GPIOA_24 GPIOA_26 GPIOA_28 GPIOA_30 GPIOA_32 {3} {3} {3} {3} {3} {3} {3} {3} {3} GPIOA_34 {3} GPIOA_36 {3} HDR_20x2 20x2 Edge Fingers Matting Conn P/N: MEC1-120-02-F-S-EM2 Mfr : Samtec Pin No:15 & 16 Should be NC For Matting Connector Polarised Pins Figure 4-20 * Interface Connector Schematic USB-to-UART Interface Included on the starter kit board is a USB-to-UART interface with ESD protection. This interface includes an integrated USB-to-UART bridge controller to provide a standard UART connection with the IGLOO PLUS FPGA. Any standard UART controller can be implemented in the IGLOO PLUS FPGA to allow access with this interface. In addition, the Microsemi IP catalog includes various UART controllers, specifically CoreUART, which can be instantiated in the FPGA design with an embedded processor. CoreUART controller supports both asynchronous and synchronous modes with configurable parameters for various applications. One application of the USB-to-UART interface is to allow for Hyper-terminal on a PC to communicate with the IGLOO PLUS FPGA. HyperTerminal is a serial communications application program that can be installed in the Windows(R) operating system. A basic HyperTerminal program is usually distributed with Windows. With an USB driver properly installed, and correct COM port and communication settings selected, you can use the HyperTerminal program to communicate with a design running in the IGLOO PLUS FPGA device. Information on the USB-to-UART bridge datasheet and device drivers are available at the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. 42 R e visio n 1 IGLOO PLUS Starter Kit User's Guide The USB-to-UART schematic is shown in Figure 4-21. V3P3 JP1 CON2 5V_USB Mfr P/N :BLM31PG500SN1L Mfr: Murata VUSB PTC1 U2 FB1 2 1 8 7 FERRITE BEAD DTR RTS CTS DSR RI DCD TXD RXD 28 24 23 27 2 1 26 25 SUSPEND NSUSPEND RST 12 11 9 NC7 NC8 NC9 NC10 NC11 18 19 20 21 22 VBUS REGIN FUSE R2 147 Mfr P/N :MICROSMD050F-2 Mfr:Tyco D- 2 GND1 7 GND2 D+ 3 8 GND3 NC 4 9 GND4 GND 5 U1 1 IO1A 2 G 3 IO2A IO1B 6 V 5 IO2B 4 5 D- 4 D+ GND GNDNW GNDCNTR 0.1uF LED_GREEN 6 NC1 NC2 NC3 NC4 NC5 NC6 CP2102 USB_MINI_RECEP Mfr P/N :UX60-MB-5ST Mfr: Hirose USBLC6-2 0 R1 10K AGL_UART_RXD [4] AGL_UART_TXD [4] 3 30 29 1uF D9 J5 1 VDD 10 13 14 15 16 17 C1 C2 VBUS 6 R67 Mfr P/N :CP2102-GM Mfr: Silicon Labs C18 0.1uF Mfr P/N :USBLC6-2SC6 Mfr: ST Micro. Figure 4-21 * USB-to-UART Interface Schematic SPI Flash One 2 Mbyte SPI flash is available on the board and can be used by CoreABC-type applications for access of additional memory. The flash interface, serial peripheral interface bus (SPI), is a synchronous serial data link standard that is used to access the flash memory. Some advantages of the SPI interface are full duplex communication and higher throughput than I2C. In the schematics shown in Figure 4-22, either the Winbond or Atmel 2 Mbyte SPI flash will be populated on-board. Winbond and Atmel SPI flash datasheets are available at the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. 2 MByte U11 SPI FLASH 16M bit [4] [4] [4] [4] [4] [4] 5 2 6 1 3 7 SPI_DIO SPI_DO SPI_CLK SPI_CS_N SPI_WP_N SPI_HOLD_N R47 4.87K DIO DO CLK CS WP HOLD Vcc V3P3 8 C50 0.1uF 10V GND 4 W25X16 Mfr P/N : W25X16-VSSIG Mfr: Winbond U23 SPI FLASH 16M BIT [4] [4] [4] [4] [4] [4] SPI_DIO SPI_DO SPI_CLK SPI_CS_N SPI_WP_N SPI_HOLD_N 1 8 2 4 5 3 SI SO SCK CS WP RESET VCC V3P3 6 C67 0.1uF 10V GND 7 AT45DB161D-SU MANUFACTURER P/N = AT45BD161D-SU Manufacturer = Atmel Figure 4-22 * SPI Flash Schematics Note: Either the Winbond or Atmel SPI flash will be populated on the board. Revision 1 43 Operation of Board Components Low-Cost Programming Stick (LCPS) Interface The development board can be programmed by the low-cost programming stick (LCPS) or via a 10-pin FP3 header (Figure 4-24). Regardless of the programming dongle used, IGLOO PLUS is programmed the same way as IGLOO nano, ProASIC3, and Fusion FPGA devices.The LCPS is a special version for the FlashPro3 programming circuitry that is compatible with FlashPro3 and the generic FlashPro programming software. The LCPS, like the IGLOO PLUS board, is RoHS-compliant and is completely lead (Pb) free. To use the LCPS with the FlashPro software, all you need to do is to select the FlashPro3 from the list of programmer types. The LCPS behaves exactly as if it were a regular encased FlashPro3 programmer, except regarding VPUMP. The LCPS does not supply VPUMP; it must be supplied by the IGLOO PLUS board. The 12-pin female connector socket is designed to interface to the 12-pin rightangle male header on the IGLOO PLUS kit. One of the pins is a special VJTAGENB signal that goes high when programming is taking place and returns to a low level when programming has completed. This signal is connected to the FET on the 1.5 V regulator circuit. The IGLOO PLUS board uses this signal to effect a change in the value of VCC from 1.2 V to 1.5 V, which is required for programming all IGLOO PLUS devices. You do not need to have the LCPS connected to the IGLOO PLUS board to operate it, after the FPGA has been programmed. The LCPS must be connected to the IGLOO PLUS board only when programming the AGLP125-CSG289. Figure 4-23 * Low-Cost Programming Stick (LCPS) Note: 1. The LCPS supplied with this kit is intended for use with the IGLOO PLUS Starter Kit. An LCPS supplied for other kits, although electrically and functionally equivalent, may not connect seamlessly with the IGLOO PLUS Starter Kit board. 2. The LCPS is not designed to supply VPUMP on its own as does the FlashPro3/4 programmer, so the IGLOO PLUS board must supply VPUMP. Use a 5 V brick or USB port to power-up the board. If you disconnect the VPUMP jumper, the LCPS will not work. 44 R e visio n 1 IGLOO PLUS Starter Kit User's Guide J3 [3] VJTAGENB [5] [5] [5] TMS 1 Programmer VJTAGENB 3 TMS 5 GND2 VJTAG 7 TDO 9 11 VJTAG TDO GND4 TCK 2 GND3 4 TDI TCK [5] 6 TDI [5] TRSTB 8 TRST [5] VPUMP 10 VPUMP [5] GND5 12 HEADER 6x2/SM 6X2 Right Angled Header Mfr P/N :TSW-106-08-T-D-RA Mfr: SAMTEC Figure 4-24 * FPGA Programming Headers Schematic Revision 1 45 Operation of Board Components LCPS Stackup The LCPS is built on a four-layer PCB with the layers arranged in the following stackup: 1. Top signal layer (Figure 4-25) 2. Ground plane 3. Power plane 1. Bottom signal layer (Figure 4-26 on page 47) Figure 4-25 * Low-Cost Programming Stick - Top Silkscreen 46 R e visio n 1 IGLOO PLUS Starter Kit User's Guide Figure 4-26 * Low-Cost Programming Stick - Bottom Silkscreen Revision 1 47 5 - Programming Program a Design into the IGLOO PLUS Evaluation Board 1. To program a design into the IGLOO PLUS evaluation board, attach the LCPS board to the IGLOO PLUS evaluation board. 2. Attach a USB cable to the LCPS. This allows a programming data file, in programming database format (*.pdb) or STAPL format (*.stp), to be downloaded via the FlashPro software to the IGLOO PLUS device fitted to the board. 3. A separate USB connection is required for the IGLOO PLUS Board if no other power source (power brick) is attached to the IGLOO PLUS board. 4. When using the FlashPro software, the programmer to select is the FlashPro3. The LCPS is functionally equivalent to a FlashPro programmer but designed specifically for use with the IGLOO PLUS Starter Kit. 5. Alternatively, an option (10-pin FP3 header) is provided to program the FPGA with a FlashPro3 instead (Figure 5-1). J4 R66 [5] TCK [5] [5] [5] [5] TDO TMS VPUMP TDI 1 3 5 7 9 0 2 4 6 8 10 VJTAG TRST [5] [5] HDR_5x2_DNL DNL Mfr P/N :15-91-2100 Mfr: Molex [5] TRST TCK R39 1K [5] R38 1K Figure 5-1 * Schematic of JTAG header for Programming Directly with a FlashPro3 Revision 1 49 6 - IGLOO PLUS Board Demo The IGLOO PLUS FPGA is pre-programmed with a simple demo to quickly get you started. This demo design will provide a quick overview as well as a quick check of this board. Demos Included in the Starter Kit There are a few demos included in this starter kit, such as a binary counter to light up the 8 user LEDs. These 8 LEDs retain their count value in Flash*Freeze mode and restart counting from that value after exiting Flash*Freeze mode. During Flash*Freeze mode, the active LEDs will be weakly ON, since they are driven by the weak hold state resistors. Flash*Freeze variants can be demonstrated using the F*F switches and FET LEDs. The IGLOO PLUS demo design RTL and design files are available at the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. Refer to the Quick Start Guide available on the website to run the demo. Powering Up the Board 1. Before running the demos, refer to Table 1-1 on page 11 to check the default jumper and board settings. 2. The board is powered from the USB connection and no external power supply is required. - A 5 V wall-jack connector could be used when USB cable is not available. - The board does not switch seamlessly between the power brick and USB, so the power source 4-pin header and jumper must be used to select the desired power source. 3. Once the USB cable is attached securely, verify the green LED next to the USB jack is ON. Getting Started with the IGLOO PLUS Starter Kit Demo Design Demo 1 - IGLOO PLUS Counter 1. Before starting Demo 1, check the jumper settings and set all switches to the OFF or CLOSE position. Ensure the F*F switch is in the OFF position. 2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in the starter kit. 3. Press and release System Reset to reset the IGLOO PLUS FPGA. 4. Observe that LED D1 is ON during Reset. 5. The LEDs D[3:8] represent a binary counter which counts up from 000000 to 111111 and loops back. After reset, LEDs D[3:8] should restart counting from zero. Table 6-1 * LED[8:1] LED Description LED D1 On during reset LED D2 On when any push-button is pressed or DIP switch is in the open position LED D3 Binary Counter[5] LED D4 Binary Counter[4] LED D5 Binary Counter[3] Revision 1 51 IGLOO PLUS Board Demo Table 6-1 * LED[8:1] (continued) LED Description LED D6 Binary Counter[2] LED D7 Binary Counter[1] LED D8 Binary Counter[0] Demo 2 - OLED Interface Demonstration This demo includes a simple Roulette game provided by Avnet Memec that demonstrates control and operation of the OLED display. 1. Press SW1 to begin a bet and press SW1 again to stop at the number you want to bet on. 2. Once you have selected your number, press SW2 to spin. Your results will display in the OLED. 3. Continue with steps 1 and 2 to bet and play again. Demo 3 - Simple Flash*Freeze Demonstration This demo demonstrates the IGLOO PLUS FPGA's ability to save power while holding internal logic state during Flash*Freeze mode. 1. Enter Flash*Freeze mode by switching the F*F switch to ON. - In Flash*Freeze mode, observe the LEDs D[1:8] retain the last state they were driven to when Flash*Freeze mode was asserted. They may be weakly ON, since they are driven by the weak hold state resistors. - The OLED will remain on, since it is self-powered. - See Demo 4 below for the settings and states of LEDs D[13:15] during Flash*Freeze mode. 2. Exit Flash*Freeze mode by switching the F*F switch to OFF. - After exiting Flash*Freeze mode, LEDs D[3:8] resume counting from the count value prior to entering Flash*Freeze mode. 3. To measure power of the FPGA core during and after Flash*Freeze mode, simply remove jumper J12 and use a multimeter capable of reading A current across J12. Demo 4 - Flash*Freeze Variant: Configuration Settings of Demo Design One feature of the IGLOO PLUS FPGA family is the ability to hold input and output states during Flash*Freeze mode. This demonstration will showcase this feature by displaying the result of various input and output hold configurations. In this portion of the design, two inputs named FET Switch 1 and FET Switch 2 are used to drive different logic values into the FPGA. FET Switch 1 directly drives FET LED D13 and FET Switch 2 directly drives FET LED D14 and FET LED D15. FET switches are used on this board to provide the required current to drive the LEDs when the FPGA is in Flash*Freeze mode. FETs are not required to enter Flash*Freeze mode or to take advantage of the I/O hold state feature. The FPGA configurations of the inputs and outputs of this circuit are described in Table 6-2 and Table 6-3 on page 53. Table 6-2 * FET Input Configuration in Demo Design Name I/O Hold Internal Weak Resister Pull FET Switch 1 Enabled Down Drives FET LED D13 directly FET Switch 2 Disabled Down Drives FET LED D14 and D15 directly 52 R e visio n 1 Description IGLOO PLUS Starter Kit User's Guide When HOLD is disabled at the output buffer, the output will depend on the resister pull-up or pull-down direction in Flash*Freeze mode. If HOLD is enabled at the output buffer, then the output will depend on the state right before entering Flash*Freeze mode. Table 6-3 * FET Output Configuration in Demo Design FET LED I/O Hold Internal Weak Resister Pull Description FET LED D13 Enabled Down P-Type FET LED D14 Disabled Down P-Type FET LED D15 Disabled Up N-Type 1. Similar to Demo 1, before starting Demo 4, check the jumper settings and set all switches to the OFF or CLOSED position. Ensure the F*F switch is in the OFF position. 2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in the starter kit. 3. Press and release the System Reset button (SW7) to reset the IGLOO PLUS FPGA. - Observe that LED D1 is ON during Reset. 4. Example A: Set both FET Switches [2:1] to the CLOSE position. - Based on the logic in this demo design, both P-Type FET LEDs D13 and D14 should be ON and N-Type FET LED D15 should be OFF. Refer to the board schematic for reference on the FET LED connections. - Enable Flash*Freeze mode by setting the F*F Switch to ON. After entering Flash*Freeze mode, observe that P-Type FET LED D13 stays ON because the HOLD state for this output configuration was enabled. Also observe that P-Type FET LED D14 is ON due to the pull-down resister configuration. N-Type FET LED D15 turns ON due to the pull-up resister configuration. Toggle the FET Switches back and forth. Observe that the LEDs are unaffected, because the device is in Flash*Freeze mode. The inputs are not able to pass data into the device. Return the FET Switches [2:1] back to the CLOSE position - Disable Flash*Freeze mode by setting the F*F Switch to OFF. After exiting the Flash*Freeze mode, observe that N-Type FET LED D15 turns OFF. 5. Example B: Set both FET Switches [2:1] to the OPEN position - Based on the logic in this demo design, both P-type FET LEDs D13 and D14 should be OFF and N-type FET LED D15 should be ON. - Enable Flash*Freeze mode by setting the F*F Switch to ON. After entering Flash*Freeze mode, observe that P-Type FET LED D13 remains OFF because the HOLD state for this output configuration was enabled. Also observe that P-Type FET LED D14 turns ON due to the pull-down resister configuration. N-Type FET LED D15 is ON due to the pull-up resister configuration. - Disable Flash*Freeze mode by setting the F*F to OFF. After exiting the Flash*Freeze mode, observe that P-Type FET LED D14 turns OFF. Revision 1 53 IGLOO PLUS Board Demo The FET Truth Table (Table 6-4) shows the Flash*Freeze variants based on the FET I/O HOLD and resister pull configured for this demo design. For the output FET LEDs, NORMAL represents the LED state before entering and after exiting Flash*Freeze mode, while F*F Mode represents the LED state during Flash*Freeze mode. Table 6-4 * FET Truth Table Input FET Switch 1 54 Output P-Type FET LED D13 (active low): HOLD P-Type FET LED D14 (active low): Pull-down N-Type FET LED D15 (active high): Pull-up FET Switch 2 NORMAL F*F Mode Normal F*F Mode Normal F*F Mode CLOSE (0) CLOSE (0) ON (0) ON (0) ON (0) ON (0) OFF (0) ON (1) CLOSE (0) OPEN (1) ON (0) ON (0) OFF (1) ON (0) ON (1) ON (1) OPEN (1) CLOSE (0) OFF (1) OFF (1) ON (0) ON (0) OFF (0) ON (1) OPEN (1) OPEN (1) OFF (1) OFF (1) OFF (1) ON (0) ON (1) ON (1) R e visio n 1 A - Resources IGLOO PLUS Starter Kit www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx IGLOO PLUS Overview www.microsemi.com/soc/products/iglooplus/default.aspx IGLOO PLUS Datasheet www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf IGLOO PLUS FPGA Fabric User's Guide www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf Libero IDE Design Software www.microsemi.com/soc/products/software/libero/default.aspx Revision 1 55 B - List of Changes The following table lists critical changes that were made in the current version of the chapter. Date Revision 1 (February, 2013) Changes Added note in "Low-Cost Programming Stick (LCPS)" section. (SAR 22976) Page 44 Note: *The part number is located on the last page of the document. The digits following the slash indicate the month and year of publication. Revision 1 57 C - Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world, 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues, and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website. Website You can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is soc_tech@microsemi.com. Revision 1 59 Product Support My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email (soc_tech@microsemi.com) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via soc_tech_itar@microsemi.com. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. 60 R e visio n 1 Index B Bank 0 I/O Signals for AGLP125-CSG289 17, 18, 19, 20, 21 M Microsemi SoC Products Group email 59 web-based technical support 59 website 59 board description 7 stackup 8 board stackup 57 P product support 59-?? C customer service 59 email 59 My Cases 60 outside the U.S. 60 technical support 59 website 59 contacting Microsemi SoC Products Group customer service 59 email 59 web-based technical support 59 contents 5 current measurement 26 customer service 59 D push-button switches 37 R resources 55 demo Flash*Freeze variant configuration settings of demo design 52 IGLOO PLUS counter 51 OLED interface 52 simple Flash*Freeze demonstration 52 DIP switches 38 S switches DIP 38 push-button 37 settings 11 T F Flash*Freeze mode control 30 switch 35 H hardware components 7 tech support ITAR 60 My Cases 60 outside the U.S. 60 technical support 59 U USB-to-UART interface 42 I User LEDs 39 I/O test pins 40 Introduction 5 W web-based technical support 59 J jumper settings 11 jumpers settings 11 L LCPS 44 stackup 46 LEDs 39 low-cost programming stick (LCPS) 44 R e v is i o n 1 61 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 (c) 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 50200152-1/2.13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microsemi: AGLP-EVAL-KIT