IGLOO PLUS Starter Kit
User’s Guide
IGLOO PLUS Starter Kit User’s Guide
Revision 1 3
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
IGLOO PLUS Starter Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Board Components and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IGLOO PLUS Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connectors, Jumpers, and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 FPGA Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Key Features of AGLP125-CSG289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Decaps and Ground Post Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Potentiometer and Voltage-Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Operation of Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash*Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
.DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
OLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Low-Cost Programming Stick (LCPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6 IGLOO PLUS Board Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Demos Included in the Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Getting Started with the IGLOO PLUS Starter Kit Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
B List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table of Contents
4 Revision 1
C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Revision 1 5
Introduction
IGLOO PLUS Starter Kit Contents
The RoHS-compliant, environmentally friendly IGLOO® PLUS Starter Kit is packaged in a recyclable
cardboard box made from recycled materials. This development kit includes an on-board programmer
and demonstrates the ultra-low power of Microsemi® IGLOO PLUS devices. Ta b l e 1 lists the contents of
the box.
Table 1 • IGLOO PLUS Starter Kit Contents
Quantity Contents
1 IGLOO PLUS board with AGLP125 IGLOO PLUS field programmable gate array (FPGA)
1 Programmer for use with IGLOO PLUS board
1 5 V power supply
2 USB 2.0 high-speed cables
1 Packet of jumpers
1 Microsemi Libero® System-on-Chip (SoC) software DVD
1 Quickstart Guide
Figure 1 • IGLOO PLUS Starter Kit Board
Revision 1 7
1 – Board Components and Settings
This chapter describes the components and settings for the IGLOO PLUS Starter Kit Board.
Board Description
The IGLOO PLUS Starter Kit board is intended to provide a low-cost system platform for evaluating
IGLOO PLUS (AGLP) technology, such as low power, I/O state preservation during Flash*Freeze mode,
and Schmitt Triggered I/Os. Other advanced features include the ability to use the FPGA I/Os of the
Expansion Header as hot-swappable and the Schmitt Triggered FPGA inputs for improved noise
immunity.
This evaluation board enables you to measure power consumption (dynamic, static, and Flash*Freeze
modes) with the core operating between 1.2 V and 1.5 V. When using the board in conjunction with the
Microsemi power analysis tools, you will have a clear picture of application power consumption at each
stage in your design. In addition, the Libero SoC tool suite now includes power-driven layout (PDL),
which can reduce the power consumption of designs up to 30 percent.
The evaluation board has a small form factor, measuring 3.7 inches by 4 inches, and supports an
AGLP125 IGLOO PLUS device in the 14 mm × 14 mm CSG289 package. All components used on the
board, such as LEDs, reset (µA range), and oscillator, are low-power components. Also included on the
evaluation board is a USB-to-UART interface to allow HyperTerminal on a PC to communicate with the
IGLOO PLUS device on the board.
The top of the board has a programming stick header which allows the low-cost programming stick
LCPS) to be attached to the board for programming the IGLOO PLUS AGLP125-CSG289 device
(Figure 1-1). FPGA I/Os have been wired to test pin pads on the board for debug and expandability.
Note: The clock oscillator for the IGLOO PLUS Starter Kit Board is behind the board.
Figure 1-1 • IGLOO PLUS Starter Kit Board
Board Components and Settings
8 Revision 1
IGLOO PLUS Board Stackup
The IGLOO PLUS board is built on a 10-layer PCB. Figure 1-1 and Figure 1-1 on page 7 show the top
(L1) and bottom (L10) silkscreens. The full PCB design layout is provided on the Microsemi SoC
Products Group website, on the IGLOO PLUS Starter Kit page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. To view the PCB
design layout files, you can use the Allegro Free Physical Viewer, which can be downloaded from the
Cadence Allegro Downloads page.
• Top Signal (Figure 1-1 on page 7)
•GND 1
•Signal
•GND 2
•PWR 1
•PWR 2
•GND 3
•Signal
•GND 4
• Bottom Signal (Figure 1-2 on page 9)
IGLOO PLUS Starter Kit User’s Guide
Revision 1 9
Figure 1-2 • IGLOO PLUS Top Silkscreen (L1)
Board Components and Settings
10 Revision 1
Figure 1-3 • IGLOO PLUS Bottom Silkscreen (L10)
IGLOO PLUS Starter Kit User’s Guide
Revision 1 11
Connectors, Jumpers, and Switch Settings
Recommended default jumper settings are defined in Table 1-1. The voltage selection jumpers are
highlighted in grey. Connect jumpers in the default settings described in Table 1 -1 to enable the pre-
programmed demo design to function correctly.
Table 1-1 • Jumper and Connector Settings
Jumper Default Setting Comment
J1 Ground post header
J2 Ground post header
J3 LC JTAG header for programmer
J4 JTAG header
J5 USB mini receptacle
J6 Pin 2-3 Remove jumper to disconnect VCCI_0 power
J7 Remove Remove jumper to disconnect external battery source
J8 Pin 2-3 Remove jumper to disconnect VCCI_1 power
J9 Pin 1-4 Select WALL, BAT, VUSB for 5V_SOURCE
Pin 1-4 = VUSB
Pin 2-4 = BAT
Pin 3-4 = WALL
J10 5 V Brick
J11 Pin 1-2 Select VCC or VCC_SWEEP for VCORE
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
J12 Pin 2-3 Current measurement header for VCORE
J13 Pin 2-3 Current measurement header for VCCI_3
J14 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_1
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
J15 Pin 3-2 Select VJTAGENB or 3.3 V
Pin 3-2 = VJTAGENB
Pin 1-2 = 3.3 V
J16 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_1
Pin 2-4 = 3.3 V
Pin 3-4 = 1.5 V or 1.2 V
Pin 1-4 = 2.5 V
J17 Pin 2-3 Current measurement header for VCCI_2
J18 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_0
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
Board Components and Settings
12 Revision 1
J19 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_0
Pin 2-4 = 3.3 V
Pin 3-4 = 1.5 V or 1.2 V
Pin 1-4 = 2.5 V
J20 Pin 2-3 Current measurement header for VJTAG
J21 Pin 1-2 Select 3.3 V or 1.5 / 1.2 V for VJTAG
Pin 1-2 = 3.3 V
Pin 2-3 = 1.5 V or 1.2 V
J22 Pin 2-3 Current measurement header for VPUMP
J23-J24 Pin 1-2 Remove each jumper to disconnect any of the 2 FET Switches[1:2] from
FPGA.
J23 = 3V3_SWITCH1
J24 = 3V3_SWITCH2
J25-J27 Pin 1-2 Remove each jumper to disconnect any of the 3 FET LEDs from FPGA.
J25 = FET_P1
J26 = FET_N
J27 = FET_P2
J28-J35 Pin 1-2 Remove each jumper to disconnect any of the 8 user DIP switches[1:8] from
FPGA.
J28 = D_SWITCH1
J29 = D_SWITCH2
J30 = D_SWITCH3
J31 = D_SWITCH4
J32 = D_SWITCH5
J33 = D_SWITCH6
J34 = D_SWITCH7
J35 = D_SWITCH8
J36-J39 Pin 1-2 Remove each jumper to disconnect any of the 4 push-button switches[1:4] from
FPGA.
J36 = SWITCH1
J37 = SWITCH2
J38 = SWITCH3
J39 = SWITCH4
J40-J47 Pin 1-2 Remove each jumper to disconnect any of the 8 user LEDs[1:8] from FPGA.
J42 = LED1
J41 = LED2
J40 = LED3
J47 = LED4
J46 = LED5
J45 = LED6
J44 = LED7
J43 = LED8
Table 1-1 • Jumper and Connector Settings (continued)
Jumper Default Setting Comment
IGLOO PLUS Starter Kit User’s Guide
Revision 1 13
Table 1-2 • Switch Settings
Switch Default Setting Comment
SW1–SW4 Push-button switches for SWITCH[1:4]
SW5 CLOSE Contains DIP switches for 3V3_SWITCH[1:2]
DSW5 CLOSE Contains DIP switches for D_SWITCH[1:8]
SW7 Push-button switch for system reset PBRESET_N
SW8 OFF Flash*Freeze: To enable Flash*Freeze mode, SW8 toward ON.
In Flash*Freeze mode, current consumption of FPGA goes below 50 µA.
Revision 1 15
2 – FPGA Description
The IGLOO PLUS board is populated with an IGLOO PLUS AGLP125-CSG289 FPGA.
Key Features of AGLP125-CSG289
• Low power
• 1.2 V to 1.5 V core voltage support for low power
• Supports single-voltage system operation
• 5 µW power consumption in Flash*Freeze mode
• Low-power active FPGA operation
• Flash*Freeze technology enables ultra-low power consumption while maintaining FPGA content
• Configurable hold previous state, tristate, HIGH, or LOW state per I/O in Flash*Freeze mode
• Easy entry to / exit from ultra-low-power Flash*Freeze mode
• Reprogrammable flash technology
• In-system programming (ISP) and security
• High-performance routing hierarchy
• Advanced I/O
• Selectable Schmitt trigger inputs
• Clock conditioning circuit (CCC) and PLL
• Embedded memory
Table 2-1 lists specifications for the AGLP125-CSG289 FPGA.
For further information, refer to the IGLOO PLUS datasheet:
www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf
Table 2-1 • IGLOO PLUS AGLP125-CSG289 FPGA Features
Feature Specification
System Gates 125,000
Typical Equivalent Macrocells 1,024
VersaTiles (D-flip-flops) 3,120
Flash*Freeze Mode (Typical, µW) 16
RAM kbits (1,024 bits) 36
4,608-Bit Blocks 8
FlashROM (bits) 1 K
Secure (AES) ISP Yes
Integrated PLLs in CCCs 1
VersaNet Globals 18
I/O Banks 4
Maximum User I/Os 212
FPGA Description
16 Revision 1
Power and Ground Pins
Figure 2-1 shows the power and ground pins for AGLP125-CSG289.
Figure 2-1 • Power and Ground Pins for AGLP125-CSG289
VCCPLF
VCCIB0_1
B7
VCCIB0_2
B12
VCCIB0_3
C5
VCCIB0_4
E11
VCCIB1_1
E16
VCCIB1_2
H15
VCCIB1_3
L14
VCCIB1_4
M17
VCCIB2_1
N10
VCCIB2_2
P13
VCCIB2_3
R6
VCCIB2_4
T9
VCCIB3_1
E1
VCCIB3_2
F4
VCCIB3_3
J3
VCCIB3_4
M2
VCC1
L9
VCC2
G9
VCC3
J7
VCC4
J11
VCOMPLF
H1
VCCPLF
J1
GND1 A4
GND2 A9
GND3 A14
GND4 B2
GND5 B17
GND6 C10
GND7 C15
GND8 D3
GND9 D8
GND10 D13
GND11 F14
GND12 G2
GND13 G7
GND14 G8
GND15 G10
GND16 G11
GND17 G17
GND18 H7
GND19 H8
GND20 H9
GND21 H10
GND22 H11
GND23 J8
GND24 J9
GND25 J10
GND26 K1
GND27 K7
GND28 K8
GND29 K9
GND30 K10
GND31 K11
GND32 K16
GND33 L4
GND34 L7
GND35 L8
GND36 L10
GND37 L11
GND38 N5
GND39 N15
GND40 P3
GND41 P8
GND42 R1
GND43 R11
GND44 T4
GND45 T14
GND46 U2
GND47 U7
GND48 U12
SEC 5/6
AGLP125 CSG289
POWER
GND
U5E
AGLP125-CSG289
SEC 5/6
POWER
GND
U5E
IGLOO PLUS Starter Kit User’s Guide
Revision 1 17
Bank I/O Signals
Figure 2-2 through Figure 2-5 on page 19 show the schematics for the bank I/O signals.
Figure 2-2 • Bank 0 I/O Signals for AGLP125-CSG289
AGL_B0_PIN_D5
AGL_B0_PIN_A3
AGL_B0_PIN_A2
AGL_B0_PIN_D6
AGL_B0_PIN_F7
AGL_B0_PIN_B4
AGL_B0_PIN_C6
AGL_B0_PIN_E7
AGL_B0_PIN_F8
AGL_B0_PIN_A5
AGL_B0_PIN_C7
AGL_B0_PIN_E8
AGL_B0_PIN_A7
AGL_B0_PIN_F9
AGL_B0_PIN_A8
AGL_B0_PIN_E9
AGL_B0_PIN_D9
AGL_B0_PIN_E10
AGL_B0_PIN_D12
AGL_B0_PIN_E12
AGL_B0_PIN_E5
AGL_B0_PIN_C16
AGL_B0_PIN_A1
AGL_B0_PIN_E13
AGL_B0_PIN_B16
AGL_B0_PIN_D14
AGL_B0_PIN_B3
AGL_B0_PIN_C4
AGL_B0_PIN_E6
AGL_B0_PIN_B5
AGL_B0_PIN_D7
AGL_B0_PIN_B6
AGL_B0_PIN_A6
AGL_B0_PIN_C8
AGL_B0_PIN_C2
AGL_B0_PIN_C3
AGL_B0_PIN_D15
AGL_B0_PIN_A17
AGL_B0_PIN_D4
AGL_B0_PIN_B1
AGL_B0_PIN_F10
AGL_B0_PIN_B9
AGL_B0_PIN_B8
AGL_B0_PIN_C9
AGL_B0_PIN_A10
AGL_B0_PIN_B10
GPIOA_29 {3}
GPIOA_33 {3}
GPIOA_31 {3}
GPIOA_35 {3}
GPIOA_9 {3}
GPIOA_13 {3}
GPIOA_15 {3}
GPIOA_17 {3}
GPIOA_19 {3}
GPIOA_21 {3}
GPIOA_23 {3}
GPIOA_7 {3}
GPIOA_5 {3}
GPIOA_1 {3}
GPIOA_3 {3}
GPIOA_25 {3}
GPIOA_27 {3}
IO06RSB0
B3
IO07RSB0
D5
IO08RSB0
A3
IO09RSB0
C4
IO10RSB0
D6
IO11RSB0
A2
IO12RSB0
E6
IO13RSB0
B4
IO14RSB0
F7
IO15RSB0
B5
IO16RSB0
E7
IO17RSB0
C6
IO18RSB0
D7
IO19RSB0
A5
IO20RSB0
F8
IO21RSB0
B6
IO22RSB0
E8
IO23RSB0
C7
IO24RSB0
A6
IO25RSB0
F9
IO26RSB0
A7
IO27RSB0
C8
IO28RSB0
B8
IO29RSB0
F10
IO30RSB0
A8
IO31RSB0
B9
IO32RSB0
E9
IO33RSB0
C9
IO34RSB0
D9
IO35RSB0
A10
IO36RSB0
E10
IO37RSB0
B10
IO56RSB0 E12
IO55RSB0 D12
IO54RSB0 A16
IO53RSB0 F12
IO52RSB0 C14
IO51RSB0 F11
IO50RSB0 C13
IO49RSB0 B15
IO48RSB0 A15
IO47RSB0 D11
IO46RSB0 B14
IO45RSB0 C12
IO44RSB0 B13
IO43RSB0 C11
IO42RSB0 A13
IO41RSB0 D10
IO40RSB0 A12
IO39RSB0 B11
IO38RSB0 A11
GAA0/IO00RSB0 C2
GAA1/IO01RSB0 B1
GAB0/IO02RSB0 D4
GAB1/IO03RSB0 A1
GAC0/IO04RSB0 C3
GAC1/IO05RSB0 E5
GBA0/IO61RSB0 C16
GBA1/IO62RSB0 D15
GBB0/IO59RSB0 D14
GBB1/IO60RSB0 E13
GBC0/IO57RSB0 A17
GBC1/IO58RSB0 B16
BANK0
AGLP125 CSG289
SEC 1/6
U5A
AGLP125-CSG289
BANK0
SEC 1/6
U5A
TP86
TP TP86
TP
TP69
TP TP69
TP
TP99 TP
TP99 TP
TP71
TP TP71
TP
TP106
TP TP106
TP
TP239
TP TP239
TP
TP102 TP
TP102 TP
TP83 TP
TP83 TP
TP80 TP
TP80 TP
TP92 TP
TP92 TP
TP123
TP TP123
TP
TP75
TP TP75
TP
TP95
TP TP95
TP
TP207
TP TP207
TP
TP109 TP
TP109 TP
TP76 TP
TP76 TP
TP124 TP
TP124 TP
TP120
TP TP120
TP
TP100 TP
TP100 TP
TP103 TP
TP103 TP
TP111 TP
TP111 TP
TP101
TP TP101
TP
TP94
TP TP94
TP
TP97 TP
TP97 TP
TP105
TP TP105
TP
TP240
TP TP240
TP
TP119 TP
TP119 TP
TP22 TP
TP22 TP
TP98 TP
TP98 TP
TP91 TP
TP91 TP
TP74
TP TP74
TP
TP82 TP
TP82 TP
TP88 TP
TP88 TP
TP96 TP
TP96 TP
TP247
TP TP247
TP
TP117 TP
TP117 TP
TP112
TP TP112
TP
TP77 TP
TP77 TP
TP81 TP
TP81 TP
TP68 TP
TP68 TP
TP89 TP
TP89 TP
TP121
TP TP121
TP
TP236
TP TP236
TP
TP118 TP
TP118 TP
TP114
TP TP114
TP
TP90 TP
TP90 TP
TP122
TP TP122
TP
TP93 TP
TP93 TP
TP115
TP TP115
TP
TP87
TP TP87
TP
TP85
TP TP85
TP
TP72
TP TP72
TP
TP73
TP TP73
TP
TP116 TP
TP116 TP
TP78 TP
TP78 TP
TP113
TP TP113
TP
TP107
TP TP107
TP
TP110
TP TP110
TP
TP84 TP
TP84 TP
TP222
TP TP222
TP
TP70
TP TP70
TP
TP108
TP TP108
TP
TP79 TP
TP79 TP
FPGA Description
18 Revision 1
Figure 2-3 • Bank 1 I/O Signals for AGLP125-CSG289
AGL_B1_PIN_L16
AGL_B1_PIN_K15
AGL_B1_PIN_K14
AGL_B1_PIN_M16
AGL_B1_PIN_L15
AGL_B1_PIN_L13
AGL_B1_PIN_N17
AGL_B1_PIN_L12
AGL_B1_PIN_N16
AGL_B1_PIN_E14
AGL_B1_PIN_F13
AGL_B1_PIN_J17
AGL_B1_PIN_J16
AGL_B1_PIN_J12
AGL_B1_PIN_M14
AGL_B1_PIN_K13
AGL_B1_PIN_M15
AGL_B1_PIN_E15
AGL_B1_PIN_H14
AGL_B1_PIN_H16
AGL_B1_PIN_J13
AGL_B1_PIN_H17
AGL_B1_PIN_M13
AGL_B1_PIN_H12
AGL_B1_PIN_K17
GPIOA_34{3}
GPIOA_36{3}
GPIOA_26{3}
GPIOA_28{3}
GPIOA_30
{3}
GPIOA_32{3}
GPIOA_10
{3}
GPIOA_8{3}
GPIOA_6{3}
GPIOA_12{3}
GPIOA_16{3}
GPIOA_18{3}
GPIOA_20{3}
GPIOA_24{3}
GPIOA_22
{3}
GPIOA_2{3}
GPIOA_4
{3}
TP19 TP
TP19 TP
TP37
TP TP37
TP
TP49
TP TP49
TP
TP44
TP TP44
TP
TP38
TP TP38
TP
TP21
TP TP21
TP
TP28
TP TP28
TP
TP40
TP TP40
TP
TP47
TP TP47
TP
TP46
TP TP46
TP
TP50 TP
TP50 TP
TP20 TP
TP20 TP
TP32
TP TP32
TP
TP27
TP TP27
TP
TP34
TP TP34
TP
TP33
TP TP33
TP
TP223 TP
TP223 TP
TP43 TP
TP43 TP
TP36
TP TP36
TP
TP16
TP TP16
TP
TP26
TP TP26
TP
TP210 TP
TP210 TP
TP183 TP
TP183 TP
TP30
TP TP30
TP
TP42 TP
TP42 TP
TP226 TP
TP226 TP
TP208 TP
TP208 TP
TP17
TP TP17
TP
TP48 TP
TP48 TP
TP142 TP
TP142 TP
TP25
TP TP25
TP
TP45
TP TP45
TP
TP35
TP TP35
TP
TP162 TP
TP162 TP
TP41
TP TP41
TP
IO64RSB1
G13
IO66RSB1
D16
IO68RSB1
C17
IO69RSB1
G14
IO70RSB1
D17
IO71RSB1
F16
IO72RSB1
G12
IO73RSB1
E17
IO74RSB1
H13
IO75RSB1
F15
IO76RSB1
G16
IO77RSB1
F17
IO78RSB1
G15
IO88RSB1
K12
IO89RSB1
J15
IO90RSB1
J14
IO91RSB1
L17
IO92RSB1
L16
IO93RSB1
K15
IO94RSB1
K13
IO95RSB1
K14
IO96RSB1
M16
IO97RSB1
M15
IO98RSB1
L15
GBA2/IO63RSB1 E14
GBB2/IO65RSB1 E15
GBC2/IO67RSB1 F13
GCA0/IO84RSB1 H14
GCA1/IO83RSB1 J17
GCA2/IO85RSB1 H16
GCB0/IO82RSB1 J16
GCB1/IO81RSB1 J13
GCB2/IO86RSB1 J12
GCC0/IO80RSB1 H17
GCC1/IO79RSB1 H12
GCC2/IO87RSB1 K17
GDA0/IO104RSB1 M14
GDA1/IO103RSB1 M13
GDB0/IO102RSB1 N16
GDB1/IO101RSB1 L13
GDC0/IO100RSB1 N17
GDC1/IO99RSB1 L12
BANK1
AGLP125 CSG289
SEC 2/6
U5B
BANK1
SEC 2/6
U5B
AGLP125-CSG289
TP104 TP
TP104 TP
TP29 TP
TP29 TP
TP24 TP
TP24 TP
TP18
TP TP18
TP
TP39 TP
TP39 TP
TP31 TP
TP31 TP
TP23
TP TP23
TP
Figure 2-4 • Bank 2 I/O Signals for AGLP125-CSG289
AGL_B2_PIN_P12
AGL_B2_PIN_M12
AGL_B2_PIN_T15
AGL_B2_PIN_R13
AGL_B2_PIN_R12
AGL_B2_PIN_N11
AGL_B2_PIN_M11
AGL_B2_PIN_T13
AGL_B2_PIN_U13
AGL_B2_PIN_T12
AGL_B2_PIN_P10
AGL_B2_PIN_T11
AGL_B2_PIN_M10
AGL_B2_PIN_R10
AGL_B2_PIN_T10
AGL_B2_PIN_P9
AGL_B2_PIN_U10
AGL_B2_PIN_R9
AGL_B2_PIN_M9
AGL_B2_PIN_U9
AGL_B2_PIN_N9
AGL_B2_PIN_U8
AGL_B2_PIN_R3
AGL_B2_PIN_M7
AGL_B2_PIN_P4
AGL_B2_PIN_M8
AGL_B2_PIN_R2
AGL_B2_PIN_P15
AGL_B2_PIN_N13
AGL_B2_PIN_P16
AGL_B2_PIN_T2
AGL_B2_PIN_N8
AGL_B2_PIN_U5
AGL_B2_PIN_N7
AGL_B2_PIN_T5
AGL_B2_PIN_U4
AGL_B2_PIN_T6
AGL_B2_PIN_U6
AGL_B2_PIN_R8
AGL_B2_PIN_T7
AGL_B2_PIN_N12
AGL_B2_PIN_R14
AGL_B2_PIN_U15
AGL_B2_PIN_U14
AGL_B2_PIN_U11
AGL_B2_PIN_P11
AGL_B2_PIN_P7
AGL_B2_PIN_R4
AGL_B2_PIN_R5
AGL_B2_PIN_U3
AGL_B2_PIN_T3
AGL_B2_PIN_P6
AGL_B2_PIN_N6
AGL_B2_PIN_P5
AGL_B2_PIN_T8
AGL_B2_PIN_R7
IGLOO_FF [6]
PACER_D2[6]
PACER_D0
[6]
PACER_RES#
[6]
TP143
TP
TP143
TP
TP147
TP TP147
TP
TP177
TP TP177
TP
TP144
TP
TP144
TP
TP137
TP TP137
TP
TP149
TP TP149
TP
TP171
TP
TP171
TP
TP182
TP
TP182
TP
TP168
TP TP168
TP
TP128
TP
TP128
TP
TP179
TP TP179
TP
TP154
TP TP154
TP
TP133
TP
TP133
TP
TP151
TP TP151
TP
TP134
TP TP134
TP
TP175
TP TP175
TP
TP138
TP TP138
TP
TP136
TP TP136
TP
TP172 TP
TP172 TP
TP148
TP TP148
TP
TP140
TP TP140
TP
TP173
TP
TP173
TP
TP178
TP TP178
TP
TP130
TP TP130
TP
TP126 TP
TP126 TP
TP141
TP TP141
TP
TP127
TP TP127
TP
TP163
TP TP163
TP
IO108RSB2
P14
IO109RSB2
N14
IO110RSB2
R15
IO111RSB2
N12
IO112RSB2
P12
IO113RSB2
M12
IO114RSB2
R14
IO115RSB2
T15
IO116RSB2
R13
IO117RSB2
U15
IO118RSB2
R12
IO119RSB2
N11
IO120RSB2
U14
IO121RSB2
M11
IO122RSB2
T13
IO123RSB2
U13
IO124RSB2
T12
IO125RSB2
P10
IO126RSB2
P11
IO127RSB2
T11
IO128RSB2
M10
IO129RSB2
U11
IO130RSB2
R10
IO131RSB2
T10
IO132RSB2
P9
IO133RSB2
U10
IO134RSB2
R9
IO135RSB2
M9
IO136RSB2
U9
IO137RSB2
N9
IO138RSB2
U8
IO139RSB2 T8
IO140RSB2 T7
IO141RSB2 R8
IO142RSB2 U6
IO143RSB2 T6
IO144RSB2 N8
IO145RSB2 R7
IO146RSB2 U5
IO147RSB2 T5
IO148RSB2 N7
IO149RSB2 U4
IO150RSB2 R5
IO151RSB2 U3
IO152RSB2 P7
IO153RSB2 T3
IO154RSB2 P6
IO155RSB2 R4
IO156RSB2 N6
IO157RSB2 P5
IO158RSB2 R3
IO159RSB2 M7
IO160RSB2 P4
IO161RSB2 M8
FF/GEB2/IO163RSB2 U1
GDA2/IO105RSB2 P15
GDB2/IO106RSB2 N13
GDC2/IO107RSB2 P16
GEA2/IO164RSB2 R2
GEC2/IO162RSB2 T2
SEC 3/6
AGLP125 CSG289
BANK2
U5C
AGLP125-CSG289
SEC 3/6
BANK2
U5C
TP155
TP TP155
TP
TP170
TP TP170
TP
TP160
TP TP160
TP
TP158
TP TP158
TP
TP164
TP
TP164
TP
TP153
TP TP153
TP
TP181
TP TP181
TP
TP288
TP TP288
TP
TP174
TP TP174
TP
TP161
TP TP161
TP
TP125
TP TP125
TP
TP145
TP TP145
TP
TP150
TP TP150
TP
TP157
TP TP157
TP
TP135
TP TP135
TP
TP180
TP TP180
TP
TP132
TP
TP132
TP
TP139
TP TP139
TP
TP131
TP TP131
TP
TP289
TP TP289
TP
TP152
TP TP152
TP
TP287
TP TP287
TP
TP169
TP TP169
TP
TP156
TP TP156
TP
TP176
TP TP176
TP
TP167
TP TP167
TP
TP159
TP TP159
TP
TP129
TP TP129
TP
IGLOO PLUS Starter Kit User’s Guide
Revision 1 19
Figure 2-5 • Bank 3 I/O Signals for AGLP125-CSG289
AGL_B3_PIN_H4
AGL_B3_PIN_G3
AGL_B3_PIN_H5
AGL_B3_PIN_G5
AGL_B3_PIN_G4
AGL_B3_PIN_G6
AGL_B3_PIN_F6
AGL_B3_PIN_J2
AGL_B3_PIN_L1
AGL_B3_PIN_H2
AGL_B3_PIN_H6
AGL_B3_PIN_K2
AGL_B3_PIN_K3
AGL_B3_PIN_F5
AGL_B3_PIN_E3
AGL_B3_PIN_N4
AGL_B3_PIN_T1
AGL_B3_PIN_E4
AGL_B3_PIN_M6
AGL_B3_PIN_N3
AGL_B3_PIN_L6
AGL_B3_PIN_M5
AGL_B3_PIN_N2
AGL_B3_PIN_P1
AGL_B3_PIN_M3
AGL_B3_PIN_M4
AGL_B3_PIN_P2
AGL_B3_PIN_L5
AGL_B3_PIN_K5
AGL_B3_PIN_K6
AGL_B3_PIN_J6
AGL_B3_PIN_L3
AGL_B3_PIN_J5
AGL_B3_PIN_H3
AGL_B3_PIN_J4
AGL_B3_PIN_G1
OSC_CLK [6]
PBRESET_N [6]
TP242 TP
TP242 TP
TP235 TP
TP235 TP
TP248 TP
TP248 TP
TP215 TP
TP215 TP
TP241 TP
TP241 TP
IO171RSB3
P2
IO172RSB3
M4
IO173RSB3
L5
IO174RSB3
P1
IO175RSB3
K5
IO176RSB3
M3
IO177RSB3
K6
IO178RSB3
N2
IO179RSB3
K4
IO180RSB3
N1
IO181RSB3
J6
IO182RSB3
L3
IO183RSB3
J5
IO184RSB3
M1
IO185RSB3
J4
IO195RSB3
H3
IO196RSB3
F2
IO197RSB3
H4
IO198RSB3
G3
IO199RSB3
H5
IO200RSB3
E2
IO201RSB3
G5
IO202RSB3
F3
IO203RSB3
G4
IO204RSB3
D1
IO205RSB3
D2
IO206RSB3
G6
IO208RSB3
F6
IO210RSB3
C1
GAA2/IO211RSB3 E4
GAB2/IO209RSB3 F5
GAC2/IO207RSB3 E3
GEA0/IO165RSB3 N4
GEA1/IO166RSB3 T1
GEB0/IO167RSB3 M5
GEB1/IO168RSB3 M6
GEC0/IO169RSB3 N3
GEC1/IO170RSB3 L6
GFA0/IO189RSB3 K2
GFA1/IO190RSB3 J2
GFA2/IO188RSB3 L1
GFB0/IO191RSB3 H2
GFB1/IO192RSB3 H6
GFB2/IO187RSB3 K3
GFC0/IO193RSB3 G1
GFC1/IO194RSB3 F1
GFC2/IO186RSB3 L2
BANK3
AGLP125 CSG289
SEC 4/6
U5D
AGLP125-CSG289
BANK3
SEC 4/6
U5D
TP206 TP
TP206 TP
TP213 TP
TP213 TP
TP209 TP
TP209 TP
TP225 TP
TP225 TP
TP203 TP
TP203 TP
TP218 TP
TP218 TP
TP214 TP
TP214 TP
TP245 TP
TP245 TP
TP227 TP
TP227 TP
TP224 TP
TP224 TP
TP249 TP
TP249 TP
FPGA Description
20 Revision 1
JTAG Pins
The AGLP125-CSG289 has advanced I/O features such as JTAG pins for IEEE 1149.1 JTAG Boundary
Scan Test. These pins are utilized during programming of the FPGA (Figure 2-6). Low-power flash
devices have a separate bank for these dedicated JTAG pins. The JTAG pins can be run at any voltage
from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if
the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be
supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O
bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used or planned for use, the VJTAG pin together with the TRST pin could be tied to
GND.
VJTAG is the ability to switch between 3.3 V and 1.5 V / 1.2 V source using jumper J21. Four-pin
headers can be used for current measurement of the VJTAG and VPUMP rails.
Figure 2-6 • JTAG Pins
V3P3
1V5_1V2
V3P3
VJTAG [6]
VPUMP [6]
VJTAG [6]
VPUMP [6]
TDI
[6]
TCK[6]
TRST
[6]
TMS[6]
TDO [6]
R48 39R48 39
1
2
3
4
J20
HDR_4PIN
J20
HDR_4PIN
TCK
U16
TDI
T16
TMS
R16
TRST
R17
VJTAG P17
TDO T17
VPUMP U17
SEC 6/6
AGLP125 CSG289
JTAG
U5F
SEC 6/6
JTAG
U5F
AGLP125-CSG289
1
2
3
J21
HDR_3PIN
J21
HDR_3PIN
1
2
3
4
J22
HDR_4PIN
J22
HDR_4PIN
IGLOO PLUS Starter Kit User’s Guide
Revision 1 21
Decaps and Ground Post Schematics
The schematics for the decaps and ground post are shown in Figure 2-7.
Figure 2-7 • Schematics for Decaps and Ground Post
VCCI_1 VCCI_2 VCCI_3
VCORE
VCCI_0
DECAPS FOR I/O BANK0 , BANK1 ,BANK2 & BANK3
DECAPS FOR VCORE
GROUND POST
C290.1uF C290.1uF
C550.1uF C550.1uF
C560.1uF C560.1uF
C570.01uF C570.01uF
C510.01uF C510.01uF
C480.1uF C480.1uF
C580.01uF C580.01uF
C300.1uF C300.1uF
C440.01uF C440.01uF
C490.01uF C490.01uF
C520.01uF C520.01uF
+
C54
10uF 16V
+
C54
10uF 16V
+
C31
10uF 16V
+
C31
10uF 16V
+
C43
10uF 16V
+
C43
10uF 16V
C380.1uF C380.1uF
1
J2
HEADER 1
J2
HEADER 1
C360.1uF C360.1uF
1
J1
HEADER 1
J1
HEADER 1
C280.01uF C280.01uF
C410.1uF C410.1uF
+
C53
10uF 16V
+
C53
10uF 16V
C270.01uF C270.01uF
C400.1uF C400.1uF
C450.01uF C450.01uF
C460.01uF C460.01uF
C470.01uF C470.01uF
+
C33
10uF 16V
+
C33
10uF 16V
Revision 1 23
3 – Power
The IGLOO PLUS development board is powered through an external voltage power brick or USB. The
board does not switch seamlessly between the power brick and USB, so the 4-pin header and jumper
must be used to select the desired power source. In the USB option, the in-rush current meets the USB
specifications (see Figure 3-1). The power brick option is provided in applications when 100% of the total
I/Os are utilized and USB power is insufficient. A green LED next to the USB jack is ON whenever the
USB power supply is connected.
The development board has an input of a 5 V supply from the power brick or USB. Protection diodes are
used to protect against negative voltage. Three voltage rails are provided, as shown in Ta b le 3-1 (3.3 V,
2.5 V, and 1.5 V).
The regulator can be switched between the 1.5 V and 1.2 V rail because the FPGA core functions at
1.2 V, but is programmed at 1.5 V.
Table 3-1 • Power Regulator Current Ratings
Regulator Current Rating
3.3 V 2A
2.5V 1A
1.5 V / 1.2 V 500 mA
Figure 3-1 • USB Active Inrush Limiter
5V
WALL
VUSB
5V_USB
5V_SOURCE
VUSB
BAT
ACTIVE INRUSH LIMITER
Q1 ONLY
INSTALLED ON
FACTORY DEMO
5V BRICK
C5
0.1uF
C5
0.1uF
1
2
3
4
J9
4PIN_HEADER
J9
4PIN_HEADER
C4
0.027UF
C0402
C4
0.027UF
C0402
3
1 4
2
5
6
Q1
SI3407DV
Q1
SI3407DV
2
3
1
J10
CONN JACK PWR
Mfg P/N = PJ-002AH
Manufacturer = CUI INC
J10
CONN JACK PWR
Mfg P/N = PJ-002AH
Manufacturer = CUI INC
R5
22 OHM
R0402
R5
22 OHM
R0402
R65
10K
R65
10K
C8
0.1uF
C8
0.1uF
R8
220K
R0402
R8
220K
R0402
R6
22 OHM
R0402
R6
22 OHM
R0402
R4
2.7K
R0402
R4
2.7K
R0402
3
1
4
2
5
6
Q2
Si3407DV
Q2
Si3407DV
C3
0.1uF
C3
0.1uF
C6
0.1uF
C6
0.1uF
1 3
2
D10
BAT54
D10
BAT54
C7
0.1uF
C7
0.1uF
Power
24 Revision 1
Power Modes
In addition to the board, the IGLOO PLUS FPGA offers power advantages. Some key power advantages
of the IGLOO PLUS FPGAs are as follows:
• Flash*Freeze technology enables easy entry and exit from the static Low-power mode, where
IGLOO consumes as little as 5 µW while retaining the contents of the system memory and data
registers.
• Sleep (and shutdown) mode allows the IGLOO PLUS FPGA core power supply (or all power
supplies) to be powered down when functionally is not required, while the rest of the system
remains powered.
• The user low static ICC macro (ULSICC) reduces IGLOO PLUS FPGA dynamic and static power
consumption. The ULSICC macro, when enabled, disables the FlashROM, reducing the overall
power of the device.
Table 3-2 gives a summary of the power modes available with IGLOO PLUS devices in general and is
extracted from the “Flash*Freeze Technology and Low Power Modes” chapter of the IGLOO PLUS
FPGA Fabric User’s Guide.
Table 3-2 • Power Modes
Mode VCC VCCI Core Clocks
ULSICC
Macro
To Enter
Mode
To Resume
Operation Trigger
Active On On On On N/A Initiate clock None –
Static Idle On On On Off N/A Stop clock Initiate clock External
Flash*Freeze
Type 1
On On On On* N/A Assert FF pin Deassert FF
pin
External
Flash*Freeze
Type 2
On On On OnaUsed to enter
Flash*Freeze
mode
Assert FF pin
and LSICC
Deassert FF
pin
External
Sleep On Off Off Off N/A Shut down
VCC
Turn on
VCC supply
External
Shutdown Off Off Off Off N/A Shut down
VCCand
VCCI
supplies
Turn on
VCC and
VCCI
supplies
External
a. External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL
will be turned off automatically.
IGLOO PLUS Starter Kit User’s Guide
Revision 1 25
Battery
In addition to the power brick and USB, this board provides the option to power-up via battery. No battery
casing is provided on the board. Jumpers should be set correctly to select the option of either powering
through a wall/USB or through batteries hooked up externally. To provide a 3 V input source from battery,
two AA Alkaline cells may be used. A 2-pin jumper for VBAT and GND must be provided to the input of
the main regulator to give the option of either powering through a wall/USB or powering through batteries
hooked up externally.
Potentiometer and Voltage-Sweep
A potentiometer is located on the left hand side of the board to provide the voltage-sweep function to
sweep VCC (Figure 3-3). One primary function of the potentiometer is to show battery operation on the
IGLOO PLUS device and how the FPGA can operate successfully even if VCC experiences a drop in
voltage. You can measure the lowest possible VCC for battery operations. When using the potentiometer,
you should also monitor the VCC via current measurement headers (Figure 3-4 on page 26) to make sure
it does not go beyond the specified value.
Figure 3-2 • Battery Header and Power Input Schematics
BAT
EXTERNAL
BATTERY
SOURCE
1
2
J7
BATTERY
1x2_100MIL
J7
BATTERY
1x2_100MIL
Figure 3-3 • Current Measurement Headers
VCCI_0
VCCI_1
VCCI_2
VCCI_3
VCC
VJTAG
VPUMP
3.3 V
Current
Measurement IGLOO PLUS
2.5 V
VCCI-Sweep
VCCI-Sweep
VCCI-Sweep
3.3 V
3.3 V
1.5 V
3.3 V
3.3 V
Power
26 Revision 1
Current Measurement
Once the IGLOO PLUS evaluation board is powered up, you can evaluate power consumption using the
current measurement four-pin headers on the board (Figure 3-5). Current measurement can be made
without powering down the board.
Four-pin headers are used for current measurement of the rails shown in Figure 3-6 on page 27. All
banks are separated and two of the banks have an option to power-up though a 3.3 V or 2.5 V source, as
shown in Figure 3-7 on page 27. Voltage sources can be selected using jumpers or can be selected to
sweep between 1.2 V and 1.5 V using the potentiometer on the development board.
Figure 3-4 • Schematic for Potentiometer
1V5_1V2
VCC_SWEEP
13
2
RV1
5K pot
RV1
5K pot
C351uF C351uF
Set the multimeter to measure current and attach the probes to pins 1 and 4
when the board is in normal operation.
Remove jumper from pins 2-3 for current measurement without
powering down.
Figure 3-5 • Current Measurement 4-Pin Headers
IGLOO PLUS Starter Kit User’s Guide
Revision 1 27
The schematic in Figure 3-7 shows the options for power-up.
Figure 3-6 • Current Measurement Headers for Power Rails
VCCI_0
VCCI_1
VCCI_2
VCCI_3
VCC
VJTAG
VPUMP
Current
Measurement IGLOO PLUS
3.3 V
3.3 V
3.3 V
1.5 V
3.3 V or 2.5 V
3.3 V or 2.5 V
3.3 V
Figure 3-7 • Power-Up Options
VCORE
VCCI_1
VCCI_0
VCCI_2
VCCI_3
1V5_1V2
V3P3
V3P3
V3P3
2V5
1V5_1V2
V3P3
2V5
1V5_1V2
VCC_SWEEP
VCC_SWEEP
VCC_SWEEP
1
2
3
4
J12
HDR_4PIN
J12
HDR_4PIN
1
2
3
4
J8
HDR_4PIN
J8
HDR_4PIN
1
2
3
J18
HDR_3PIN
J18
HDR_3PIN
1
2
3
J14
HDR_3PIN
J14
HDR_3PIN
1
2
3
4
J16
4PIN_HEADER
J16
4PIN_HEADER
1
2
3
J11
HDR_3PIN
J11
HDR_3PIN
1
2
3
4
J17
HDR_4PIN
J17
HDR_4PIN
1
2
3
4
J19
4PIN_HEADER
J19
4PIN_HEADER
1
2
3
4
J13
HDR_4PIN
J13
HDR_4PIN
1
2
3
4
J6
HDR_4PIN
J6
HDR_4PIN
Revision 1 29
4 – Operation of Board Components
This chapter describes operation of the IGLOO PLUS evaluation board.
Clock Oscillator
One 20 MHz clock oscillator with 50 PPM is provided on the board. This clock oscillator is connected to
the FPGA to provide a system or reference clock. The PLL can be configured and instantiated in the
FPGA to generate a wide range of clock frequencies.
Reference
For more information, refer to the IGLOO PLUS Starter Kit website page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.
Schematic
Figure 4-1 shows the schematic for the clock oscillator.
Reset
An RC type push-button reset switch to the FPGA is provided on-board. The Schmitt Trigger chip (U13),
however, is NOT populated. An on-board Schmitt Trigger chip is not required because Schmitt Trigger is
one of the many advanced I/O features of the IGLOO PLUS FPGA family. To improve noise immunity,
ensure that the Schmitt Trigger option for this reset input pin is enabled in the FPGA design. If the IGLOO
PLUS FPGA is swapped out with a device that does not have the advance Schmitt Trigger I/O feature,
the Schmitt Trigger chip (U13) should be populated.
Figure 4-1 • Clock Oscillator Schematic
V3P3
OSC_CLK [4]
R43
10K
R43
10K
R64
22
R64
22
C390.1uF C390.1uF
OUT_EN
1GND 2
OUTPUT 3
VDD
4
U10
OSCILLATOR
Mfg P/N = SIT8002AC-43-33E
Manufacturer = SI TIME
U10
OSCILLATOR
Mfg P/N = SIT8002AC-43-33E
Manufacturer = SI TIME
Operation of Board Components
30 Revision 1
Schematic
Figure 4-2 shows the schematic for reset.
Flash*Freeze Mode
The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which retains
all SRAM and register information and can still quickly return to normal operation (Figure 4-1).
Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by
activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os,
and clocks can still be driven and can be toggling without impact on power consumption, and the device
retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either
hold their previous state or can be tristated during Flash*Freeze mode.
There are two ways to use Flash*Freeze mode. In Flash*Freeze type 1, entering and exiting the mode is
exclusively controlled by the assertion and deassertion of the FF pin. This enables an external processor
or human interface device to directly control Flash*Freeze mode. In Flash*Freeze mode type 2, entering
and exiting the mode is controlled by both the FF pin AND user-defined logic. Flash*Freeze management
IP can be used in type 2 mode for clock and data management while entering and exiting Flash*Freeze
mode.
For more information and detailed usage of Flash*Freeze modes, refer to the “Microsemi’s Flash*Freeze
Technology and Low Power Modes” chapter of the IGLOO PLUS FPGA Fabric User’s Guide.
Figure 4-2 • Reset Schematic
V3P3
V3P3
PBRESET_N [4]
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
Mfr P/N :DS1818R-20+T&R
Mfr: Dallas
RST
C65 0.1uF
C65 0.1uF
VCC
2
GND
3
RST 1
U13
DNP
U13
DNP
R63
0
R63
0
12
34
SW7
KSC403J
SW7
KSC403J
R62
10K
R62
10K
C660.1uF C660.1uF
Figure 4-3 • Flash*Freeze Mode Control
IGLOO PLUS
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
IGLOO PLUS Starter Kit User’s Guide
Revision 1 31
Flash*Freeze Types
Type 1: Controlled by dedicated Flash*Freeze Pin.
Type 2: Controlled by dedicated Flash*Freeze Pin and Internal Logic.
Flash*Freeze Type 1: Controlled by Dedicated Flash*Freeze Pin
Flash*Freeze type 1 is intended for systems where either the device is reset upon exiting Flash*Freeze
mode, or data and clock are managed externally. The device enters Flash*Freeze mode 1 µs after the
dedicated FF pin is asserted (active low), and returns to normal operation when the FF pin is deasserted
(high). In this mode, FF pin assertion or deassertion is the only condition that determines entering or
exiting Flash*Freeze mode (Figure 4-4). An INBUF_FF I/O buffer macro must be used to identify the
Flash*Freeze input in your design.
Figure 4-4 • Flash*Freeze Mode Type 1 – Controlled by the Flash*Freeze Pin
User Design
IGL OO , IGLOO PLUS, IGLOO nano,
ProASIC3L, or RT ProA SIC3 Device
Flash*Freeze
Mode
Enables Entering
Flash* Freeze Mode
Flash*Freeze
Signal
Flash*Freeze
Technology
Flash* Freeze (FF) Pin
INBUF_FF
Flash*Freeze
M
ode Control
AND
T o FPGA Core or Floating
1
Figure 4-5 • Flash*Freeze Mode Type 1 – Timing Diagram
Normal
Operation
Flash*Freeze
Mode
Normal
Operation
F
lash*Freeze Pin
t = 1 µs t = 1 µs
Operation of Board Components
32 Revision 1
Flash*Freeze Type 2: Controlled by Dedicated Flash*Freeze Pin and
Internal Logic
The device can be made to enter Flash*Freeze mode by activating the FF pin together with the
Flash*Freeze management IP core or user-defined control logic (Figure 4-6) within the FPGA core. This
method enables the design to perform important activities before allowing the device to enter
Flash*Freeze mode, such as transitioning into a safe state, completing the processing of a critical event.
Designers are encouraged to take advantage of the Flash*Freeze Management IP of Microsemi to
handle clean entry and exit of Flash*Freeze mode. The device will only enter Flash*Freeze mode when
the Flash*Freeze pin is asserted (active low) and the User Low Static ICC (ULSICC) macro input signal,
called the LSICC signal, is asserted (high). One condition is not sufficient to enter Flash*Freeze mode
type 2; both the FF pin and LSICC signal must be asserted.
Figure 4-7 shows the timing diagram for entering and exiting Flash*Freeze mode type 2. After exiting
Flash*Freeze mode type 2 by deasserting the Flash*Freeze pin, the LSICC signal must be deasserted by
the user design. This will prevent entering Flash*Freeze mode by asserting the Flash*Freeze pin only.
Refer to Figure 4-1 on page 29 for Flash*Freeze (FF) pin and LSICC signal assertion and deassertion
values.
Figure 4-6 • Flash*Freeze Mode Type 2 – Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal)
INBUF_FF
Auto-Connected to IP
ULSICC Macro
Flash*Freeze
Management IP
User Design
IGLOO, IGLOO PLUS, IGLOO nano,
ProASIC3L, or RT ProASIC3 Device
Flash*Freeze
Mode
Enables Entering
Flash*Freeze Mode
Flash*Freeze
Signal
Flash*Freeze
Technology
Flash*Freeze (FF) Pin
AND
Connect to Top-Level Port
IGLOO PLUS Starter Kit User’s Guide
Revision 1 33
IGLOO PLUS I/O State in Flash*Freeze Mode
In IGLOO PLUS devices, users have multiple options in how to configure I/Os during Flash*Freeze
mode:
1. Hold the previous state.
2. Set I/O pad to weak pull-up or pull-down.
3. Tristate I/O pads.
The I/O configuration must be configured by the user in the I/O Attribute Editor or in a PDC constraint file,
and can be done on a pin-by-pin basis. The output hold feature will hold the output in the last registered
state, using the I/O pad weak pull-up or pull-down resistor when the FF pin is asserted. When inputs are
configured with the hold feature enabled, the FPGA core side of the input will hold the last valid state of
the input pad before the device entered Flash*Freeze mode. The input pad can be driven to any value,
configured as tristate, or configured with the weak pull-up or pull-down I/O pad feature during
Flash*Freeze mode, without affecting the hold state. If the weak pull-up or pull-down feature is used
without the output hold feature, the input and output pads will maintain the configured weak pull-up or
pull-down status during Flash*Freeze mode and normal operation. If a fixed weak pull-up or pull-down is
defined on an output buffer or as bidirectional in output mode, and a hold state is also defined for the
same pin, the pin will be configured in hold state mode during Flash*Freeze mode. During normal
operation, the pin will be configured with the predefined weak pull-up or pull-down. Any I/Os that do not
use the hold state or I/O pad weak pull-up or pull-down features will be tristated during Flash*Freeze
mode and the FPGA core will be driven high by inputs. Inputs that are tristated during Flash*Freeze
mode may be left floating without any reliability concern or impact to power consumption.
Figure 4-7 • Flash*Freeze Mode Type 1 and Type 2 – Signal Assertion and Deassertion Values
LSICC Signal
Normal
Operation
Flash*Freeze
Mode
Normal
Operation
F
lash*Freeze Pin
t = 1 µs t = 1 µs
Table 4-1 • Flash*Freeze Mode Type 1 and Type 2 – Signal Assertion and Deassertion Values
Signal Assertion Value Deassertion Value
Flash*Freeze (FF) pin Low High
LSICC signal High Low
Note:
1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal.
2. The LSICC signal is used only in Flash*Freeze mode type 2.
Operation of Board Components
34 Revision 1
Table 4-2 shows the I/O pad state based on the configuration and buffer type.
Table 4-2 • IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)—I/O Pad State
Buffer Type Hold State
I/O Pad
Weak Pull-Up/-Down
I/O Pad State in Flash*Freeze
Mode
Input Enabled Enabled Weak pull-up/pull-down 1
Disabled Enabled Weak pull-up/pull-down 2
Enabled Disabled Tristate 1
Disabled Disabled Tristate 2
Output Enabled “Don't care” Weak pull to hold state
Disabled Enabled Weak pull-up/pull-down
Disabled Disabled Tristate
Bidirectional /
Tristate Buffer
E = 0
(input/tristate)
Enabled Enabled Weak pull-up/pull-down 1
Disabled Enabled Weak pull-up/pull-down 2
Enabled Disabled Tristate 1
Disabled Disabled Tristate 2
E = 1 (output) Enabled “Don't care” Weak pull to hold state 3
Disabled Enabled Weak pull-up/pull-down
Disabled Disabled Tristate
Note:
1) Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze
mode.
2) Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode.
3) For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to
the hold state.
IGLOO PLUS Starter Kit User’s Guide
Revision 1 35
Flash*Freeze Switch
An F*F switch is provided on the board for designs that utilize the Flash*Freeze technology. Setting the
F*F switch to FF_ON will enable the Flash*Freeze mode of the IGLOO PLUS device. Since the Schmitt
Trigger chip (U12) is NOT populated on-board for the F*F switch, the Schmitt Trigger feature should be
enabled in the FPGA design for the Flash*Freeze input to enhance noise immunity (Figure 4-8). The
Schmitt Trigger is an advanced I/O feature of the IGLOO PLUS FPGA family. If the IGLOO PLUS FPGA
is swapped out with a device that does not have the advanced Schmitt Trigger I/O feature, the Schmitt
Trigger chip (U12) should be populated.
Some features on this board are included to demonstrate the Flash*Freeze variants of the IGLOO PLUS
FPGA. I/Os can be individually configured to either hold their previous state or be tristated during
Flash*Freeze mode. Alternatively, they can be set to a certain state (high or low) using weak pull-up or
pull-down I/O attribute configurations. These Flash*Freeze variants can be demonstrated by configuring
the I/Os in Designer and using switches as inputs to control the FET LEDs. Refer to the demo design,
which provides additional details on demonstrating these Flash*Freeze variants ("IGLOO PLUS Board
Demo" on page 51).
Flash*Freeze Variant Dip Switch
Two regular DIP switches are located on the board, next to the FET LEDs (Figure 4-9). The DIP switches
can be programmed to help debug or demonstrate the Flash*Freeze variants. Refer to the demo design
that demonstrates the Flash*Freeze variants with these switches.
Figure 4-8 • Flash*Freeze Schematic, Schmitt Triggered
V3P3
V3P3
IGLOO_FF [4]
Mfr P/N :AYZ0102AGRL
Mfr: ITT INDUSTRIES
R61
10K
R61
10K
2
1
3
SW8
AYZ0102AGRL
SW8
AYZ0102AGRL
+
C6410uF
+
C6410uF
C630.1uF C630.1uF
R52
0
R52
0
C61
0.1uF
C61
0.1uF
NC
1
A
2
GND
3
VCC 5
Y4
U12
DNP
Mfg P/N = SN74AUP1G17DCKR
Manufacturer = TI
U12
DNP
Mfg P/N = SN74AUP1G17DCKR
Manufacturer = TI
+
C622.2uF
+
C622.2uF
Figure 4-9 • Two I/Os Controlled through DIP Switch Toggling High or Low
3V3_SWITCH2
[4]
3V3_SWITCH1
[4]
3V3_SWITCH1
[4]
3V3_SWITCH2
[4]
R22 10K
R22 10K
D11
LO T67K-L1M2-24-Z_DNL
D11
LO T67K-L1M2-24-Z_DNL
R21
DNL
R21
DNL
R20 10K
R20 10K
R19
DNL
R19
DNL
1
2
3
4
SW5
76SB02ST
SW5
76SB02ST
D12
LO T67K-L1M2-24-Z_DNL
D12
LO T67K-L1M2-24-Z_DNL
Operation of Board Components
36 Revision 1
Flash*Freeze Variant FET LEDs
These FET LEDs can be used for debugging, such as for viewing the state of I/Os in Flash*Freeze mode.
These LEDs can be activated (ON) before entering Flash*Freeze mode, and have the ability to remain
activated (ON) in Flash*Freeze mode. In low-power or Flash*Freeze mode, the FET LEDs can continue
to function normally. There is one N-Type FET LED and two P-Type FET LEDs on the board
(Figure 4-10). Refer to "Demo 4 – Flash*Freeze Variant: Configuration Settings of Demo Design" on
page 52, which will help demonstrate the Flash*Freeze variants.
Figure 4-10 • FET LEDs for Debugging
V3P3
V3P3 V3P3
FET_N[4]
FET_P1 [4] FET_P2 [4]
P TYPE FET
N TYPE FET
D13
LO T67K-L1M2-24-Z
D13
LO T67K-L1M2-24-Z
1
23
G
S
D
Q6
MOSFET_PTYPE
Mfg P/N = FDV304P
Manufacturer = FairChild
G
S
D
Q6
MOSFET_PTYPE
Mfg P/N = FDV304P
Manufacturer = FairChild
R50
1.5K
R50
1.5K
D15
LO T67K-L1M2-24-Z
D15
LO T67K-L1M2-24-Z
R49
1.5K
R49
1.5K
1
23
G
S
D
Q4
MOSFET_PTYPE
Mfg P/N = FDV304P
Manufacturer = FairChild
G
S
D
Q4
MOSFET_PTYPE
Mfg P/N = FDV304P
Manufacturer = FairChild
1
2 3
G
S
D
Q5
MOSFET_NTYPE
Mfg P/N = FDV301N
Manufacturer = FairChild
G
S
D
Q5
MOSFET_NTYPE
Mfg P/N = FDV301N
Manufacturer = FairChild
R51
1.5K
R51
1.5K
D14
LO T67K-L1M2-24-Z
D14
LO T67K-L1M2-24-Z
IGLOO PLUS Starter Kit User’s Guide
Revision 1 37
Push-Button Switches
Four active low push-button switches are provided on the board for debug purposes. You can remove the
corresponding jumpers to detach or isolate any of the four push-button test switches from the FPGA I/O.
Schematics are shown in Figure 4-11 and Figure 4-12.
Figure 4-11 • Push-Button Switches Schematic
V3P3
SWITCH1 [4] SWITCH2 [4]
SWITCH1 [4]
SWITCH2 [4]
SWITCH3 [4] SWITCH4 [4]
SWITCH3 [4]
SWITCH4 [4]
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
Mfr P/N :KSC403J 50SH LFG
Mfr:ITT INDUSTRIES
R32 10K
R32 10K
1 2
34
SW1
KSC403J
SW1
KSC403J
R33 10K
R33 10K
1 2
34
SW4
KSC403J
SW4
KSC403J
12
34
SW3
KSC403J
SW3
KSC403J
1 2
3 4
SW2
KSC403J
SW2
KSC403J
R34 10K
R34 10K
R23 10K
R23 10K
Figure 4-12 • Jumper Header Schematic for Push-Button Switches
3V3_SWITCH1 [8]
SWITCH4 [6]
SWITCH3 [6]
SWITCH2 [6]
SWITCH1 [6]
1
2
J23
HDR1X2
J23
HDR1X2
1
2
J36
HDR1X2
J36
HDR1X2
1
2
J37
HDR1X2
J37
HDR1X2
1
2
J39
HDR1X2
J39
HDR1X2
1
2
J38
HDR1X2
J38
HDR1X2
Operation of Board Components
38 Revision 1
.DIP Switches
A DIP switch pack (8 switches) is provided on the board (Figure 4-13 and Figure 4-14). You can remove
the corresponding jumpers to detach or isolate any of the eight DIP Switches from the FPGA I/Os..
Figure 4-13 • DIP Switches Schematic
V3P3
D_SWITCH1 [4]
D_SWITCH2 [4]
D_SWITCH3 [4]
D_SWITCH4 [4]
D_SWITCH5 [4]
D_SWITCH6 [4]
D_SWITCH7 [4]
D_SWITCH8 [4]
D_SWITCH1 [4]
D_SWITCH2 [4]
D_SWITCH3 [4]
D_SWITCH4 [4]
D_SWITCH5 [4]
D_SWITCH6 [4]
D_SWITCH7 [4]
D_SWITCH8 [4]
R54 4.7KR54 4.7K
R56 4.7KR56 4.7K
R53 4.7KR53 4.7K
R57 4.7KR57 4.7K
R55 4.7KR55 4.7K
R60 4.7KR60 4.7K
R58 4.7KR58 4.7K
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DSW5
DIP_SWITCH
Manufacturer = GRAYHILL Inc
Mfg P/N = 76SB08ST
DSW5
DIP_SWITCH
Manufacturer = GRAYHILL Inc
Mfg P/N = 76SB08ST
R59 4.7KR59 4.7K
Figure 4-14 • Jumper Header Schematic for DIP Switches
D_SWITCH1 [6]
D_SWITCH8 [6]
D_SWITCH7 [6]
D_SWITCH6 [6]
D_SWITCH5 [6]
D_SWITCH4 [6]
D_SWITCH3 [6]
D_SWITCH2 [6]
1
2
J34
HDR1X2
J34
HDR1X2
1
2
J31
HDR1X2
J31
HDR1X2
1
2
J30
HDR1X2
J30
HDR1X2
1
2
J29
HDR1X2
J29
HDR1X2
1
2
J33
HDR1X2
J33
HDR1X2
1
2
J28
HDR1X2
J28
HDR1X2
1
2
J32
HDR1X2
J32
HDR1X2
1
2
J35
HDR1X2
J35
HDR1X2
IGLOO PLUS Starter Kit User’s Guide
Revision 1 39
User LEDs
Eight active low debug LEDs are provided on the board (Figure 4-15 and Figure 4-16). You can remove
the corresponding jumpers from the 8 × 2 headers to detach or isolate any of the eight LEDs from the
FPGA I/Os.
Figure 4-15 • User LEDs Schematic
V3P3
V3P3
LED1[4]
LED2
[4]
LED3
[4]
LED4[4]
LED8[4]
LED5
[4]
LED6[4]
LED7
[4]
Mfr P/N :LO T67K-L1M2-24-Z
Mfr: Osram Opto Semiconductors Inc
D8
LO T67K-L1M2-24-Z
D8
LO T67K-L1M2-24-Z
D5
LO T67K-L1M2-24-Z
D5
LO T67K-L1M2-24-Z
D4
LO T67K-L1M2-24-Z
D4
LO T67K-L1M2-24-Z
R29
1.5K
R29
1.5K
D7
LO T67K-L1M2-24-Z
D7
LO T67K-L1M2-24-Z
R31
1.5K
R31
1.5K
R30
1.5K
R30
1.5K
D6
LO T67K-L1M2-24-Z
D6
LO T67K-L1M2-24-Z
R27
1.5K
R27
1.5K
R28
1.5K
R28
1.5K
R25
1.5K
R25
1.5K
R24
1.5K
R24
1.5K
R26
1.5K
R26
1.5K
D1
LO T67K-L1M2-24-Z
D1
LO T67K-L1M2-24-Z
D3
LO T67K-L1M2-24-Z
D3
LO T67K-L1M2-24-Z
D2
LO T67K-L1M2-24-Z
D2
LO T67K-L1M2-24-Z
Figure 4-16 • Jumper Header Schematic for User LEDs
D_SWITCH1 [6]
D_SWITCH8 [6]
D_SWITCH7 [6]
D_SWITCH6 [6]
D_SWITCH5 [6]
D_SWITCH4 [6]
D_SWITCH3 [6]
D_SWITCH2 [6]
1
2
J34
HDR1X2
J34
HDR1X2
1
2
J31
HDR1X2
J31
HDR1X2
1
2
J30
HDR1X2
J30
HDR1X2
1
2
J29
HDR1X2
J29
HDR1X2
1
2
J33
HDR1X2
J33
HDR1X2
1
2
J28
HDR1X2
J28
HDR1X2
1
2
J32
HDR1X2
J32
HDR1X2
1
2
J35
HDR1X2
J35
HDR1X2
Operation of Board Components
40 Revision 1
I/O Test Pins
All IGLOO PLUS FPGA I/Os are available on headers located on the top and bottom of the device
(Figure 4-17 and Figure 4-18). These test pins are multiples of 100 mils apart, so developers can easily
attach headers and place an extension card on top with an off-the-shelf breadboard for a low-cost
solution for integration. In order to use I/Os assigned to the LEDs, DIP Switches, and push-button
switches, the 2-pin jumper on their path must be removed first to disconnect the assignment.
Figure 4-17 • I/O Test Pins
GND
GND
IGLOO P LU S
IO_B0
IO_B1
IO_B2
IO_B3
100 mils × N
(N = 1, 2, 3, 4, ...)
Figure 4-18 • I/O Test Pins Schematic
TP272
TP
TP272
TP
TP57
TP
TP57
TP
TP263
TP
TP263
TP
TP194
TP
TP194
TP
TP306
TP
TP306
TP
TP313
TP
TP313
TP
TP51
TP
TP51
TP
TP257
TP
TP257
TP
TP324
TP
TP324
TP
TP188
TP
TP188
TP
TP300
TP
TP300
TP
TP283
TP
TP283
TP
TP318
TP
TP318
TP
TP294
TP
TP294
TP
TP277
TP
TP277
TP
TP62
TP
TP62
TP
TP268
TP
TP268
TP
TP327
TP
TP327
TP
TP251
TP
TP251
TP
TP199
TP
TP199
TP
TP291
TP
TP291
TP
TP328
TP
TP328
TP
TP271
TP
TP271
TP
TP56
TP
TP56
TP
TP262
TP
TP262
TP
TP250
TP
TP250
TP
TP193
TP
TP193
TP
TP305
TP
TP305
TP
TP312
TP
TP312
TP
TP67
TP
TP67
TP
TP256
TP
TP256
TP
TP323
TP
TP323
TP
TP187
TP
TP187
TP
TP299
TP
TP299
TP
TP282
TP
TP282
TP
TP198
TP
TP198
TP
TP317
TP
TP317
TP
TP293
TP
TP293
TP
TP276
TP
TP276
TP
TP61
TP
TP61
TP
TP267
TP
TP267
TP
TP304
TP
TP304
TP
TP311
TP
TP311
TP
TP270
TP
TP270
TP
TP55
TP
TP55
TP
TP261
TP
TP261
TP
TP280
TP
TP280
TP
TP192
TP
TP192
TP
TP281
TP
TP281
TP
TP66
TP
TP66
TP
TP63
TP
TP63
TP
TP255
TP
TP255
TP
TP322
TP
TP322
TP
TP186
TP
TP186
TP
TP298
TP
TP298
TP
TP197
TP
TP197
TP
TP316
TP
TP316
TP
TP292
TP
TP292
TP
TP275
TP
TP275
TP
TP60
TP
TP60
TP
TP266
TP
TP266
TP
TP191
TP
TP191
TP
TP303
TP
TP303
TP
TP310
TP
TP310
TP
TP286
TP
TP286
TP
TP54
TP
TP54
TP
TP260
TP
TP260
TP
TP279
TP
TP279
TP
TP297
TP
TP297
TP
TP65
TP
TP65
TP
TP254
TP
TP254
TP
TP321
TP
TP321
TP
TP307
TP
TP307
TP
TP185
TP
TP185
TP
TP59
TP
TP59
TP
TP265
TP
TP265
TP
TP196
TP
TP196
TP
TP315
TP
TP315
TP
TP274
TP
TP274
TP
TP326
TP
TP326
TP
TP190
TP
TP190
TP
TP302
TP
TP302
TP
TP309
TP
TP309
TP
TP285
TP
TP285
TP
TP53
TP
TP53
TP
TP259
TP
TP259
TP
TP184
TP
TP184
TP
TP296
TP
TP296
TP
TP64
TP
TP64
TP
TP202
TP
TP202
TP
TP253
TP
TP253
TP
TP320
TP
TP320
TP
TP165
TP
TP165
TP
TP273
TP
TP273
TP
TP58
TP
TP58
TP
TP264
TP
TP264
TP
TP195
TP
TP195
TP
TP314
TP
TP314
TP TP258
TP
TP258
TP
TP325
TP
TP325
TP
TP189
TP
TP189
TP
TP301
TP
TP301
TP
TP290
TP
TP290
TP
TP308
TP
TP308
TP
TP284
TP
TP284
TP
TP52
TP
TP52
TP
TP295
TP
TP295
TP
TP278
TP
TP278
TP
TP200
TP
TP200
TP
TP269
TP
TP269
TP
TP201
TP
TP201
TP
TP252
TP
TP252
TP
TP319
TP
TP319
TP
V3P3
2V5
1V5_1V2
TP13
TP
TP13
TP
TP1
TP
TP1
TP TP12
TP
TP12
TP
TP3
TP
TP3
TP TP11
TP
TP11
TP
TP8
TP
TP8
TP
TP5
TP
TP5
TP TP6
TP
TP6
TP
TP9
TP
TP9
TP
IGLOO PLUS Starter Kit User’s Guide
Revision 1 41
OLED
A 96 × 16 pixel low-power blue organic light emitting diode (OLED) is available on the board above the
IGLOO PLUS FPGA (Figure 4-19). The OLED features a serial I2C interface, and is capable of
displaying sharp images or text. The demo design included in this kit contains a roulette game that uses
the OLED for display and the push-button switch for game control.
Additional OLED info is available at the IGLOO PLUS Starter Kit website page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.
Figure 4-19 • OLED Display Schematic
VP_10V
V3P3
V3P3
PACER_D0 [4]
PACER_RES# [4]
PACER_D2 [4]
SCL
SDA
Mfr P/N :PMO13701
Mfr: PACER
VCC
30
VCOMH
29
IREF
28
VDD
11
BS1
12
BS2
13
NC1
1
NC2
8
NC3
9
NC4
10
NC5
14
NC6
31
VSS
2
D7 27
D6 26
D5 25
D4 24
D3 23
D2 22
D1 21
D0 20
TEST5
3
TEST4
4
TEST3
5
TEST2
6
TEST1
7
RD# 19
WR# 18
D/C# 17
RES# 16
CS# 15
U3
PMO13701
U3
PMO13701
C20
0.01uF
C20
0.01uF
R36
10K
R36
10K
+
C21
4.7uF 16V
+
C21
4.7uF 16V
R37
2M
R37
2M
C19
1uF
C19
1uF
R35
10K
R35
10K
Operation of Board Components
42 Revision 1
Interface Connector
A standard interface connector on the board can be used to connect additional daughter cards, some of
which are developed by partners and third party vendors (Figure 4-20). The interface possibilities are
numerous, such as flash and SRAM memory interfaces, keyboard interfaces for embedded applications,
LCD interfaces, and motor control interfaces. GPIOA_1, GPIOA_2, GPIOA_4, and GPIOA_31 pins can
be used for critical signals, such as clock and reset, because proper series termination has been
provided on these signal lines.
USB-to-UART Interface
Included on the starter kit board is a USB-to-UART interface with ESD protection. This interface includes
an integrated USB-to-UART bridge controller to provide a standard UART connection with the IGLOO
PLUS FPGA. Any standard UART controller can be implemented in the IGLOO PLUS FPGA to allow
access with this interface. In addition, the Microsemi IP catalog includes various UART controllers,
specifically CoreUART, which can be instantiated in the FPGA design with an embedded processor.
CoreUART controller supports both asynchronous and synchronous modes with configurable
parameters for various applications.
One application of the USB-to-UART interface is to allow for Hyper-terminal on a PC to communicate
with the IGLOO PLUS FPGA. HyperTerminal is a serial communications application program that can be
installed in the Windows® operating system. A basic HyperTerminal program is usually distributed with
Windows. With an USB driver properly installed, and correct COM port and communication settings
selected, you can use the HyperTerminal program to communicate with a design running in the IGLOO
PLUS FPGA device.
Information on the USB-to-UART bridge datasheet and device drivers are available at the IGLOO PLUS
Starter Kit website page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.
Figure 4-20 • Interface Connector Schematic
VUSB V3P3
GPIOA_29
{3}
GPIOA_33
{3}
GPIOA_31
{3}
GPIOA_35
{3}
GPIOA_34 {3}
GPIOA_36 {3}
GPIOA_26 {3}
GPIOA_28 {3}
GPIOA_30 {3}
GPIOA_32 {3}
GPIOA_10 {3}
GPIOA_8 {3}
GPIOA_6 {3}
GPIOA_12 {3}
GPIOA_16 {3}
GPIOA_18 {3}
GPIOA_20 {3}
GPIOA_24 {3}
GPIOA_22 {3}
GPIOA_2 {3}
GPIOA_4 {3}
GPIOA_9
{3}
GPIOA_13{3}
GPIOA_15{3}
GPIOA_17{3}
GPIOA_19{3}
GPIOA_21{3}
GPIOA_23
{3}
GPIOA_7{3}
GPIOA_5{3}
GPIOA_1{3}
GPIOA_3{3}
GPIOA_25
{3}
GPIOA_27{3}
20x2 Edge Fingers
Pin No:15 & 16 Should be NC For Matting Connector Polarised Pins
Matting Conn P/N: MEC1-120-02-F-S-EM2
Mfr : Samtec
2
4
6
8
10
12
14
18
20
24
22
26
28
30
32
34
36
38
40
39
37
35
33
31
29
27
25
23
21
19
17
13
11
9
7
5
3
1
J48
HDR_20x2
J48
HDR_20x2
IGLOO PLUS Starter Kit User’s Guide
Revision 1 43
The USB-to-UART schematic is shown in Figure 4-21.
SPI Flash
One 2 Mbyte SPI flash is available on the board and can be used by CoreABC-type applications for
access of additional memory. The flash interface, serial peripheral interface bus (SPI), is a synchronous
serial data link standard that is used to access the flash memory. Some advantages of the SPI interface
are full duplex communication and higher throughput than I2C. In the schematics shown in Figure 4-22,
either the Winbond or Atmel 2 Mbyte SPI flash will be populated on-board.
Winbond and Atmel SPI flash datasheets are available at the IGLOO PLUS Starter Kit website page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.
Note: Either the Winbond or Atmel SPI flash will be populated on the board.
Figure 4-21 • USB-to-UART Interface Schematic
V3P3
5V_USB VUSB
AGL_UART_RXD [4]
AGL_UART_TXD [4]
Mfr P/N :UX60-MB-5ST
Mfr: Hirose
Mfr P/N :USBLC6-2SC6
Mfr: ST Micro.
Mfr P/N :CP2102-GM
Mfr: Silicon Labs
Mfr P/N :MICROSMD050F-2
Mfr:Tyco
Mfr P/N :BLM31PG500SN1L
Mfr: Murata
R67
0
R67
0
C1
0.1uF
C1
0.1uF
R1
10K
R1
10K
FB1
FERRITE BEAD
FB1
FERRITE BEAD
C2
1uF
C2
1uF
VBUS
8
REGIN
7
VDD
6
NC1
10
NC2
13
NC3
14
NC4
15
NC5
16
NC6
17
D-
5
D+
4
GND
3
GNDNW
30
GNDCNTR
29
RST 9
NSUSPEND 11
SUSPEND 12
NC7 18
NC8 19
NC9 20
NC10 21
NC11 22
DTR 28
RTS 24
CTS 23
DSR 27
RI 2
TXD 26
RXD 25
DCD 1
U2
CP2102
U2
CP2102
R2
147
R2
147
PTC1
FUSE
PTC1
FUSE
C18
0.1uF
C18
0.1uF
D9
LED_GREEN
D9
LED_GREEN
1
2
JP1
CON2
JP1
CON2
IO1A
1
G
2
IO2A
3IO2B 4
V5
IO1B 6
U1
USBLC6-2
U1
USBLC6-2
VBUS 1
D- 2
D+ 3
NC 4
GND 5
GND1
6
GND2
7
GND3
8
GND4
9
J5
USB_MINI_RECEP
J5
USB_MINI_RECEP
Figure 4-22 • SPI Flash Schematics
V3P3
V3P3
SPI_DIO[4]
SPI_DO[4]
SPI_CLK[4]
SPI_CS_N
[4]
SPI_WP_N[4]
SPI_HOLD_N[4]
SPI_DIO[4]
SPI_DO[4]
SPI_CLK
[4]
SPI_CS_N[4]
SPI_WP_N[4]
SPI_HOLD_N[4]
2 MByte
Mfr P/N : W25X16-VSSIG
Mfr: Winbond
C67
0.1uF 10V
C67
0.1uF 10V
HOLD
7
Vcc 8
CS
1
DIO
5
WP
3
GND 4
DO
2
CLK
6
SPI FLASH
16M bit
U11
W25X16
SPI FLASH
U11
W25X16
SI
1
SO
8
SCK
2
CS
4
WP
5
RESET
3
VCC 6
GND 7
SPI FLASH
16M BIT
U23
Manufacturer = Atmel
MANUFACTURER P/N = AT45BD161D-SU
SPI FLASH
16M BIT
U23
AT45DB161D-SU
Manufacturer = Atmel
MANUFACTURER P/N = AT45BD161D-SU
R47
4.87K
R47
4.87K
C50
0.1uF 10V
C50
0.1uF 10V
Operation of Board Components
44 Revision 1
Low-Cost Programming Stick (LCPS)
Interface
The development board can be programmed by the low-cost programming stick (LCPS) or via a 10-pin
FP3 header (Figure 4-24). Regardless of the programming dongle used, IGLOO PLUS is programmed
the same way as IGLOO nano, ProASIC3, and Fusion FPGA devices.The LCPS is a special version for
the FlashPro3 programming circuitry that is compatible with FlashPro3 and the generic FlashPro
programming software. The LCPS, like the IGLOO PLUS board, is RoHS-compliant and is completely
lead (Pb) free. To use the LCPS with the FlashPro software, all you need to do is to select the FlashPro3
from the list of programmer types. The LCPS behaves exactly as if it were a regular encased FlashPro3
programmer, except regarding VPUMP. The LCPS does not supply VPUMP; it must be supplied by the
IGLOO PLUS board. The 12-pin female connector socket is designed to interface to the 12-pin right-
angle male header on the IGLOO PLUS kit. One of the pins is a special VJTAGENB signal that goes high
when programming is taking place and returns to a low level when programming has completed. This
signal is connected to the FET on the 1.5 V regulator circuit. The IGLOO PLUS board uses this signal to
effect a change in the value of VCC from 1.2 V to 1.5 V, which is required for programming all IGLOO
PLUS devices.
You do not need to have the LCPS connected to the IGLOO PLUS board to operate it, after the FPGA
has been programmed. The LCPS must be connected to the IGLOO PLUS board only when
programming the AGLP125-CSG289.
Note:
1. The LCPS supplied with this kit is intended for use with the IGLOO PLUS Starter Kit. An LCPS
supplied for other kits, although electrically and functionally equivalent, may not connect
seamlessly with the IGLOO PLUS Starter Kit board.
2. The LCPS is not designed to supply VPUMP on its own as does the FlashPro3/4 programmer, so
the IGLOO PLUS board must supply VPUMP. Use a 5 V brick or USB port to power-up the board.
If you disconnect the VPUMP jumper, the LCPS will not work.
Figure 4-23 • Low-Cost Programming Stick (LCPS)
IGLOO PLUS Starter Kit User’s Guide
Revision 1 45
Figure 4-24 • FPGA Programming Headers Schematic
VJTAGENB[3] TCK [5]
VPUMP [5]
TRST [5]
TDI [5]
TMS[5]
VJTAG
[5]
TDO
[5]
Programmer
Mfr P/N :TSW-106-08-T-D-RA
Mfr: SAMTEC
6X2 Right Angled Header
TCK 2
GND3 4
TDI 6
TRSTB 8
VPUMP 10
VJTAGENB
1
TMS
3
GND2
5
VJTAG
7
TDO
9
GND4
11 GND5 12
J3
HEADER 6x2/SM
J3
HEADER 6x2/SM
Operation of Board Components
46 Revision 1
LCPS Stackup
The LCPS is built on a four-layer PCB with the layers arranged in the following stackup:
1. Top signal layer (Figure 4-25)
2. Ground plane
3. Power plane
1. Bottom signal layer (Figure 4-26 on page 47)
Figure 4-25 • Low-Cost Programming Stick – Top Silkscreen
IGLOO PLUS Starter Kit User’s Guide
Revision 1 47
Figure 4-26 • Low-Cost Programming Stick – Bottom Silkscreen
Revision 1 49
5 – Programming
Program a Design into the IGLOO PLUS Evaluation Board
1. To program a design into the IGLOO PLUS evaluation board, attach the LCPS board to the
IGLOO PLUS evaluation board.
2. Attach a USB cable to the LCPS. This allows a programming data file, in programming database
format (*.pdb) or STAPL format (*.stp), to be downloaded via the FlashPro software to the IGLOO
PLUS device fitted to the board.
3. A separate USB connection is required for the IGLOO PLUS Board if no other power source
(power brick) is attached to the IGLOO PLUS board.
4. When using the FlashPro software, the programmer to select is the FlashPro3. The LCPS is
functionally equivalent to a FlashPro programmer but designed specifically for use with the
IGLOO PLUS Starter Kit.
5. Alternatively, an option (10-pin FP3 header) is provided to program the FPGA with a FlashPro3
instead (Figure 5-1).
Figure 5-1 • Schematic of JTAG header for Programming Directly with a FlashPro3
VJTAG [5]
VPUMP[5]
TMS[5]
TDI[5]
TRST [5]
TCK[5]
TDO[5]
TCK
[5] TRST [5]
Mfr P/N :15-91-2100
Mfr: Molex
R38
1K
R38
1K
1
3
5
7 8
6
4
2
910
J4
HDR_5x2_DNL
DNL
J4
HDR_5x2_DNL
DNL
R39
1K
R39
1K
R66
0
R66
0
Revision 1 51
6 – IGLOO PLUS Board Demo
The IGLOO PLUS FPGA is pre-programmed with a simple demo to quickly get you started. This demo
design will provide a quick overview as well as a quick check of this board.
Demos Included in the Starter Kit
There are a few demos included in this starter kit, such as a binary counter to light up the 8 user LEDs.
These 8 LEDs retain their count value in Flash*Freeze mode and restart counting from that value after
exiting Flash*Freeze mode. During Flash*Freeze mode, the active LEDs will be weakly ON, since they
are driven by the weak hold state resistors. Flash*Freeze variants can be demonstrated using the F*F
switches and FET LEDs.
The IGLOO PLUS demo design RTL and design files are available at the IGLOO PLUS Starter Kit
website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. Refer
to the Quick Start Guide available on the website to run the demo.
Powering Up the Board
1. Before running the demos, refer to Table 1-1 on page 11 to check the default jumper and board
settings.
2. The board is powered from the USB connection and no external power supply is required.
– A 5 V wall-jack connector could be used when USB cable is not available.
– The board does not switch seamlessly between the power brick and USB, so the power
source 4-pin header and jumper must be used to select the desired power source.
3. Once the USB cable is attached securely, verify the green LED next to the USB jack is ON.
Getting Started with the IGLOO PLUS Starter Kit Demo Design
Demo 1 – IGLOO PLUS Counter
1. Before starting Demo 1, check the jumper settings and set all switches to the OFF or CLOSE
position. Ensure the F*F switch is in the OFF position.
2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in the
starter kit.
3. Press and release System Reset to reset the IGLOO PLUS FPGA.
4. Observe that LED D1 is ON during Reset.
5. The LEDs D[3:8] represent a binary counter which counts up from 000000 to 111111 and loops
back. After reset, LEDs D[3:8] should restart counting from zero.
Table 6-1 • LED[8:1]
LED Description
LED D1 On during reset
LED D2 On when any push-button is pressed or DIP switch is in the open position
LED D3 Binary Counter[5]
LED D4 Binary Counter[4]
LED D5 Binary Counter[3]
IGLOO PLUS Board Demo
52 Revision 1
Demo 2 – OLED Interface Demonstration
This demo includes a simple Roulette game provided by Avnet Memec that demonstrates control and
operation of the OLED display.
1. Press SW1 to begin a bet and press SW1 again to stop at the number you want to bet on.
2. Once you have selected your number, press SW2 to spin. Your results will display in the OLED.
3. Continue with steps 1 and 2 to bet and play again.
Demo 3 – Simple Flash*Freeze Demonstration
This demo demonstrates the IGLOO PLUS FPGA’s ability to save power while holding internal logic state
during Flash*Freeze mode.
1. Enter Flash*Freeze mode by switching the F*F switch to ON.
– In Flash*Freeze mode, observe the LEDs D[1:8] retain the last state they were driven to when
Flash*Freeze mode was asserted. They may be weakly ON, since they are driven by the
weak hold state resistors.
– The OLED will remain on, since it is self-powered.
– See Demo 4 below for the settings and states of LEDs D[13:15] during Flash*Freeze mode.
2. Exit Flash*Freeze mode by switching the F*F switch to OFF.
– After exiting Flash*Freeze mode, LEDs D[3:8] resume counting from the count value prior to
entering Flash*Freeze mode.
3. To measure power of the FPGA core during and after Flash*Freeze mode, simply remove jumper
J12 and use a multimeter capable of reading µA current across J12.
Demo 4 – Flash*Freeze Variant: Configuration Settings of Demo
Design
One feature of the IGLOO PLUS FPGA family is the ability to hold input and output states during
Flash*Freeze mode. This demonstration will showcase this feature by displaying the result of various
input and output hold configurations.
In this portion of the design, two inputs named FET Switch 1 and FET Switch 2 are used to drive different
logic values into the FPGA. FET Switch 1 directly drives FET LED D13 and FET Switch 2 directly drives
FET LED D14 and FET LED D15. FET switches are used on this board to provide the required current to
drive the LEDs when the FPGA is in Flash*Freeze mode. FETs are not required to enter Flash*Freeze
mode or to take advantage of the I/O hold state feature. The FPGA configurations of the inputs and
outputs of this circuit are described in Tab le 6 -2 and Table 6-3 on page 53.
LED D6 Binary Counter[2]
LED D7 Binary Counter[1]
LED D8 Binary Counter[0]
Table 6-1 • LED[8:1] (continued)
LED Description
Table 6-2 • FET Input Configuration in Demo Design
Name I/O Hold
Internal Weak
Resister Pull Description
FET Switch 1 Enabled Down Drives FET LED D13 directly
FET Switch 2 Disabled Down Drives FET LED D14 and D15 directly
IGLOO PLUS Starter Kit User’s Guide
Revision 1 53
When HOLD is disabled at the output buffer, the output will depend on the resister pull-up or pull-down
direction in Flash*Freeze mode. If HOLD is enabled at the output buffer, then the output will depend on
the state right before entering Flash*Freeze mode.
1. Similar to Demo 1, before starting Demo 4, check the jumper settings and set all switches to the
OFF or CLOSED position. Ensure the F*F switch is in the OFF position.
2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in the
starter kit.
3. Press and release the System Reset button (SW7) to reset the IGLOO PLUS FPGA.
– Observe that LED D1 is ON during Reset.
4. Example A: Set both FET Switches [2:1] to the CLOSE position.
– Based on the logic in this demo design, both P-Type FET LEDs D13 and D14 should be ON
and N-Type FET LED D15 should be OFF. Refer to the board schematic for reference on the
FET LED connections.
– Enable Flash*Freeze mode by setting the F*F Switch to ON.
After entering Flash*Freeze mode, observe that P-Type FET LED D13 stays ON because the
HOLD state for this output configuration was enabled.
Also observe that P-Type FET LED D14 is ON due to the pull-down resister configuration.
N-Type FET LED D15 turns ON due to the pull-up resister configuration.
Toggle the FET Switches back and forth.
Observe that the LEDs are unaffected, because the device is in Flash*Freeze mode. The
inputs are not able to pass data into the device.
Return the FET Switches [2:1] back to the CLOSE position
– Disable Flash*Freeze mode by setting the F*F Switch to OFF.
After exiting the Flash*Freeze mode, observe that N-Type FET LED D15 turns OFF.
5. Example B: Set both FET Switches [2:1] to the OPEN position
– Based on the logic in this demo design, both P-type FET LEDs D13 and D14 should be OFF
and N-type FET LED D15 should be ON.
– Enable Flash*Freeze mode by setting the F*F Switch to ON.
After entering Flash*Freeze mode, observe that P-Type FET LED D13 remains OFF because
the HOLD state for this output configuration was enabled.
Also observe that P-Type FET LED D14 turns ON due to the pull-down resister configuration.
N-Type FET LED D15 is ON due to the pull-up resister configuration.
– Disable Flash*Freeze mode by setting the F*F to OFF.
After exiting the Flash*Freeze mode, observe that P-Type FET LED D14 turns OFF.
Table 6-3 • FET Output Configuration in Demo Design
FET LED I/O Hold
Internal Weak Resister
Pull Description
FET LED D13 Enabled Down P-Type
FET LED D14 Disabled Down P-Type
FET LED D15 Disabled Up N-Type
IGLOO PLUS Board Demo
54 Revision 1
The FET Truth Table (Table 6-4) shows the Flash*Freeze variants based on the FET I/O HOLD and
resister pull configured for this demo design. For the output FET LEDs, NORMAL represents the LED
state before entering and after exiting Flash*Freeze mode, while F*F Mode represents the LED state
during Flash*Freeze mode.
Table 6-4 • FET Truth Table
Input Output
FET
Switch 1
FET
Switch 2
P-Type FET LED D13
(active low): HOLD
P-Type FET LED D14
(active low): Pull-down
N-Type FET LED D15
(active high): Pull-up
NORMAL F*F Mode Normal F*F Mode Normal F*F Mode
CLOSE (0) CLOSE (0) ON (0) ON (0) ON (0) ON (0) OFF (0) ON (1)
CLOSE (0) OPEN (1) ON (0) ON (0) OFF (1) ON (0) ON (1) ON (1)
OPEN (1) CLOSE (0) OFF (1) OFF (1) ON (0) ON (0) OFF (0) ON (1)
OPEN (1) OPEN (1) OFF (1) OFF (1) OFF (1) ON (0) ON (1) ON (1)
Revision 1 55
A – Resources
IGLOO PLUS Starter Kit
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx
IGLOO PLUS Overview
www.microsemi.com/soc/products/iglooplus/default.aspx
IGLOO PLUS Datasheet
www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf
IGLOO PLUS FPGA Fabric User’s Guide
www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf
Libero IDE Design Software
www.microsemi.com/soc/products/software/libero/default.aspx
Revision 1 57
B – List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Date Changes Page
Revision 1
(February, 2013)
Added note in "Low-Cost Programming Stick (LCPS)" section. (SAR 22976) 44
Note: *The part number is located on the last page of the document. The digits following the slash indicate the month
and year of publication.
Revision 1 59
C – Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is soc_tech@microsemi.com.
Product Support
60 Revision 1
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
(soc_tech@microsemi.com) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via soc_tech_itar@microsemi.com. Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
Revision 1 61
B
Bank 0 I/O Signals for AGLP125-CSG289 17, 18, 19,
20, 21
board
description 7
stackup 8
board stackup 57
C
contacting Microsemi SoC Products Group
customer service 59
email 59
web-based technical support 59
contents 5
current measurement 26
customer service 59
D
demo
Flash*Freeze variant
configuration settings of demo design 52
IGLOO PLUS counter 51
OLED interface 52
simple Flash*Freeze demonstration 52
DIP switches 38
F
Flash*Freeze mode
control 30
switch 35
H
hardware
components 7
I
I/O test pins 40
Introduction 5
J
jumper settings 11
jumpers
settings 11
L
LCPS 44
stackup 46
LEDs 39
low-cost programming stick (LCPS) 44
M
Microsemi SoC Products Group
email 59
web-based technical support 59
website 59
P
product support 59–??
customer service 59
email 59
My Cases 60
outside the U.S. 60
technical support 59
website 59
push-button switches 37
R
resources 55
S
switches
DIP 38
push-button 37
settings 11
T
tech support
ITAR 60
My Cases 60
outside the U.S. 60
technical support 59
U
USB-to-UART
interface 42
User LEDs 39
W
web-based technical support 59
Index
50200152-1/2.13
© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
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