SECTION 2 NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 Symbols and Operators + - / > < = * NOT : % $ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addition Subtraction or negation (two's complement) Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal AND Inclusive OR (OR) Exclusive OR (EOR) Complementation Concatenation Transferred Exchanged Sign bit; also used to show tolerance Sign extension Binary value Hexadecimal value MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-1 2.2 CPU32 Registers A6-A0 A7 (SSP) A7 (USP) CCR D7-D0 DFC PC SFC SR VBR X N Z V C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address registers (index registers) Supervisor stack pointer User stack pointer Condition code register (user portion of SR) Data registers (index registers) Alternate function code register Program counter Alternate function code register Status register Vector base register Extend indicator Negative indicator Zero indicator Two's complement overflow indicator Carry/borrow indicator 2.3 Pin and Signal Mnemonics ADDR[23:0] -- Address Bus AN[59:48]/[3:0] -- QADC Analog Input AN[w, x, y, z] AS AVEC BERR BG BGACK BKPT BR CANRX0 CANTX0 CLKOUT CS[10:0] CSBOOT CPWM[8:5] CTD[10:9]/[4:3] CTM2C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QADC Analog Input Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request TouCAN Receive Data TouCAN Transmit Data System Clock Chip Selects Boot ROM Chip Select CTM Pulse Width Modulation Channel CTM Double Action Channel CTM Modulus Clock MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-2 DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO ECLK ETRIG[2:1] EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MA[2:0] MISO MODCLK MOSI PCS[3:0] PQA[7:0] PQB[7:0] PC[6:0] PE[7:0] PF[7:0] QUOT R/W RESET RMC RXD SCK SIZ[1:0] SS T2CLK TPUCH[15:0] TSC TSTME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data Bus Data Strobe Data and Size Acknowledge Development Serial Clock Development Serial Input Development Serial Output MC6800 Devices and Peripherals Bus Clock QADC External Trigger Crystal Oscillator Input Function Codes Freeze Halt Instruction Fetch Instruction Pipeline Interrupt Request QADC Multiplexed Address QSM Master In Slave Out Clock Mode Select QSM Master Out Slave In QSM Peripheral Chip-Selects QADC Port A QADC Port B SIM Port C SIM Port E SIM Port F Quotient Out Read/Write Reset Read-Modify-Write Cycle SCI Receive Data QSPI Serial Clock Size Slave Select TPU Clock In TPU Channel Signals Three-State Control Test Mode Enable MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-3 VRH -- QADC High Reference Voltage VRL -- QADC Low Reference Voltage XFC -- External Filter Capacitor XTAL -- Crystal Oscillator Output 2.4 Register Mnemonics BIUMCR BIUTEST BIUTBR CANCTRL[0:2] CANICR IFLAG IMASK CANMCR CANTCR CCW[0:27] CFSR[0:3] CIER CISR CPCR CPR[0:1] CPTR CR[0:F] CREG CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DASM[3:4]/[9:10]A DASM[3:4]/[9:10]B DASM[3:4]/[9:10]SIC DCNR -- CTM4 BIUSM Module Configuration -- CTM4 BIUSM Test Register -- CTM4 BIUSM Time Base Register TouCAN Control Register [0:2] -- TouCAN Interrupt Configuration Register -- TouCAN Interrupt Flags Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TouCAN Interrupt Masks Register TouCAN Module Configuration Register TouCAN Test Configuration Register QADC Command Conversion Words [0:27] TPU Channel Function Select Registers [0:3] TPU Channel Interrupt Enable Register TPU Channel Interrupt Status Register CTM4 CPSM Control Register TPU Channel Priority Registers [0:1] CTM4 CPSM Test Register QSM Command RAM SIM Test Control Register C SIM Chip-Select Base Address Register Boot ROM SIM Chip-Select Base Address Registers [0:10] SIM Chip-Select Option Register Boot ROM SIM Chip-Select Option Registers [0:10] SIM Chip-Select Pin Assignment Registers [0:1] CTM4 DASM A Registers [3:4]/[9:10] CTM4 DASM B Registers [3:4]/[9:10] CTM4 DASM Status/Interrupt/Control Registers [3:4]/[9:10] Decoded Channel Number Register DDRE -- SIM Port E Data Direction Register DDRF -- SIM Port F Data Direction Register DDRQA -- QADC Port A Data Direction Register MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-4 DDRQS DREG DSCR DSSR ESTAT FCSM12CNT FCSM12SIC HSQR[0:1] HSRR[0:1] LJSRR[0:27] LJURR[0:27] LR MCSM[2]/[11]CNT MCSM[2]/[11]ML MCSM[2]/[11]SIC MRMCR PEPAR PFPAR PICR PITR PORTC PORTE PORTF PORTQA PORTQB PORTQS PQSPAR PRESDIV PWM[5:8]C PWM[5:8]A PWM[5:8]B PWM[5:8]SIC QACR[0:1] QADCINT QADCMCR QADCTEST QASR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QSM Port QS Data Direction Register SIM Test Module Distributed Register TPU Development Support Control Register TPU Development Support Status Register TouCAN Error and Status Register CTM4 FCSM12 Counter Register CTM4 FCSM12 Status/Interrupt/Control Register TPU Host Sequence Registers [0:1] TPU Host Service Request Registers [0:1] QADC Left-Justified Signed Result Registers [0:27] QADC Left-Justified Unsigned Result Registers [0:27] Link Register CTM4 MCSM Counter Registers [2]/[11] CTM4 MCSM Modulus Latch Registers [2]/[11] CTM4 MCSM Status/Interrupt/Control Registers [2]/[11] Masked ROM Module Configuration Register SIM Port E Pin Assignment Register SIM Port F Pin Assignment Register SIM Periodic Interrupt Control Register SIM Periodic Interrupt Timer Register SIM Port C Data Register SIM Port E Data Register SIM Port F Data Register QADC Port A Data Register QADC Port B Data Register QSM Port QS Data Register QSM Port QS Pin Assignment Register TouCAN Prescaler Divide Register CTM4 PWMSM Counter Registers [5:8] CTM4 PWMSM Period Registers [5:8] CTM4 PWMSM Pulse Width Registers [5:8] CTM4 PWMSM Status/Interrupt/Control Registers [5:8] QADC Control Registers [0:2] QADC Interrupt Register QADC Module Configuration Register QADC Test Register QADC Status Register MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-5 QILR QIVR QSMCR QTEST RAMBAH RAMBAL RAMMCR RAMTST ROMBAH ROMBAL RR[0:F] RSIGHI RSIGLO ROMBS[0:3] RXGMSKHI RXGMSKLO RX[14:15]MSKHI RX[14:15]MSKLO RJURR[0:27] RSR RXECTR SCCR[0:1] SCDR SCSR SGLR SIMCR SIMTR SIMTRE SPCR[0:3] SPSR SWSR SYNCR SYPCR TICR TIMER TPUMCR TR[0:F] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QSM Interrupt Level Register QSM Interrupt Vector Register QSM Module Configuration Register QSM Test Register RAM Base Address High Register RAM Base Address Low Register RAM Module Configuration Register RAM Test Register ROM Base Address High Register ROM Base Address Low Register QSM Receive RAM ROM Signature High Register ROM Signature Low Register ROM Bootstrap Words [0:3] TouCAN Receive Global Mask High Register TouCAN Receive Global Mask Low Register TouCAN Receive Buffer [14:15] Mask High Registers TouCAN Receive Buffer [14:15] Mask Low Registers QADC Right-Justified Unsigned Result Registers SIM Reset Status Register TouCAN Receive Error Counter Register QSM SCI Control Registers [0:1] QSM SCI Data Register QSM SCI Status Register Service Grant Latch Register SIM Module Configuration Register SIM System Integration Test Register SIM System Integration Test Register (ECLK) QSM QSPI Control Registers [0:3] QSM QSPI Status Register SIM Software Watchdog Service Register SIM Clock Synthesizer Control Register SIM System Protection Control Register TPU Interrupt Configuration Register TouCAN Free Running Timer Register TPU Module Configuration Register QSM Transmit RAM MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-6 TRAMBAR TRAMMCR TRAMTST TSTMSRA TSTMSRB TSTRC TSTSC TTR TXECTR -- -- -- -- -- -- -- -- -- TPURAM Base Address Register TPURAM Module Configuration Register TPURAM Test Register SIM Test Module Master Shift Register A SIM Test Module Master Shift Register B SIM Test Module Repetition Counter Register SIM Test Module Shift Count Register TouCAN Test Register TouCAN Transmit Error Counter Register 2.5 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a bit or bits. Clear refers specifically to establishing logic level zero on a bit or bits. Asserted means that a signal is in active logic state. An active low signal changes from logic level one to logic level zero when asserted. An active high signal changes from logic level zero to logic level one. Negated means that an asserted signal changes logic state. An active low signal changes from logic level zero to logic level one when negated. An active high signal changes from logic level one to logic level zero. A specific mnemonic within a range is referred to by mnemonic and number. A15 is bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0. A range of mnemonics is referred to by mnemonic and the numbers that define the range. VBR[4:0] are bits four to zero of the vector base register; CSOR[0:5] are the first six option registers. Parentheses are used to indicate the content of a register or memory location rather than the register or memory location itself. (A) is the content of accumulator A. (M : M + 1) is the content of the word at address M. LSB means least significant bit. MSB means most significant bit. References to low and high bytes are spelled out. LSW means least significant word. MSW means most significant word. ADDR is the address bus. ADDR[7:0] are the eight LSBs of the address bus. DATA is the data bus. DATA[15:8] are the eight MSBs of the data bus. MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-7 MC68336/376 NOMENCLATURE USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA 2-8