K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9XXG08UXM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Document Title 2G x 8 Bit/ 4G x 8 Bit/ 8G x 8 Bit NAND Flash Memory Revision History History Draft Date 0.0 1. Initial issue April 12th 2006 Advance 0.1 1. Add read status 2 command F1h 2. Add 2-plane read operation 3. Add address map (Table2) 4. Remove adjacent page relationship table 5. Modify figure of 2-plane copy-back program with random data input 6. Modify figure of Rp vs tr ,tf & Rp vs ibusy 7. Data retention 5years -> 10 years 8. Remove K9LBG08U1M 9. Modify figure of 2-plane page program 10. Add nWP timing guide 11. Add 2-plane read for copy-back operation 12. Add 2-plane random data out operation 13. Modify command table and note 14. Modify invalid block definition 15. Add program operation with 2KB data loading timing guide 16. tRLOH is valid when frequency is higher than 20MHz. tRHOH starts to be valid when frequency is lower than 20MHz. -> tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. Sep. 21th 2006 Advance 0.2 1. Add WELP package 2. Chip address is added 3. Chip2 status is added 4. Interleave operation is added 5. Address map is added 6. DSP characteristics are added 7. Endurance is changed (10K->5K) Revision No Remark Dec. 22h 2006 Preliminary 0.3 1. Interleave read to page program timing is added 2. Interleave copy-back program timing is added 3. ID cycle is changed Jan. 4th 2007 Preliminary 0.4 1. WELP package dimension is changed 2. Endurance is changed (5K->TBD) Jan. 12th 2007 Preliminary 1. Standby current is corrected 2. Random data output for copy-back is added 3. Max. Icc is changed (30mA->35mA) Feb. 12th 2007 Preliminary May 18th 2008 Final 0.5 0.6 1. Interleave two plane copy-back program timing is added 2. LGA QDP is added 3. Max. leakage current is corrected (10A -> 20A) 4. tCSD is changed (10ns -> 0ns) The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 2 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Document Title 2G x 8 Bit/ 4G x 8 Bit/ 8G x 8 Bit NAND Flash Memory Revision History History Draft Date Remark 1.0 1. WELP-DSP dimension is changed 2. Max. bad block number is changed. (K9LBG08U0M: max. 200ea -> max. 120ea) Dec. 11th 2007 Final 1.1 1. 14x18 LGA ODP package is added. Mar. 10th 2008 Final 1.2 1. LGA ODP part number is fixed. Apr. 7th 2008 Revision No The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 3 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 4G / 8G / 16G x 8 Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range Organization K9LBG08U0M-P PKG Type TSOPI K9HCG08U1M-P K9HCG08U1M-I 2.7V ~ 3.6V X8 K9MDG08U5M-P 52TLGA TSOP1-DSP K9MDG08U5M-Z WELP-DSP K9PDG08U5M-L 52LLGA(14x18) FEATURES * Voltage Supply : 2.7 V ~ 3.6 V * Organization - Memory Cell Array : (2G + 64M) x 8bit - Data Register : (4K + 128) x 8bit * Automatic Program and Erase - Page Program : (4K + 128)Byte - Block Erase : (512K + 16K)Byte * Page Read Operation - Page Size : (4K + 128)Byte - Random Read : 60s(Max.) - Serial Access : 25ns(Min.) *K9XDG08U5M: 50ns(Min.) * Memory Cell : 2bit / Memory Cell * Fast Write Cycle Time - Program time : 800s(Typ.) - Block Erase Time : 1.5ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : TBD(with 4bit/512byte ECC) - Data Retention : 10 Years * Command Register Operation * Unique ID for Copyright Protection * Package : - K9LBG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9HCG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9HCG08U1M-ICB0/IIB0 52 - Pin TLGA (12 x 17 / 1.0 mm pitch) - K9MDG08U5M-PCB0/PIB0 : Two K9HCG08U1M package stacked 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE - K9MDG08U5M-ZCB0/ZIB0 : Two K9HCG08U1M package stacked 48 - Pin WELP (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE - K9PDG08U5M-LCB0/LIB0 : Pb/Halogen-FREE PACKAGE 52 - Pin LLGA (14 x 18 / 1.00 mm pitch) GENERAL DESCRIPTION Offered in 4Gx8bit, the K9LBG08U0M is a 32G-bit NAND Flash Memory with spare 1G-bit. Its NAND cell provides the most costeffective solution for the solid state mass storage market. A program operation can be performed in typical 800s on the 4,224-byte page and an erase operation can be performed in typical 1.5ms on a (512K+16K)byte block. Data in the data register can be read out at 25ns (K9XDG08U5M: 50ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The K9LBG08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 4 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN CONFIGURATION (TSOP1) K9LBG08U0M-PCB0/PIB0 N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF 0.10 MAX 0.004 Unit :mm/Inch #48 #24 #25 12.40 0.488 MAX 12.00 0.472 +0.003 ( 0.25 ) 0.010 #1 0.008-0.001 0.50 0.0197 0.16 -0.03 +0.075 18.400.10 0.7240.004 0~8 0.45~0.75 0.018~0.030 +0.003 0.005-0.001 0.25 0.010 TYP 1.000.05 0.0390.002 0.125 0.035 +0.07 0.20 -0.03 +0.07 20.000.20 0.7870.008 ( 0.50 ) 0.020 5 1.20 0.047MAX 0.05 0.002 MIN K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN CONFIGURATION (TSOP1) K9HCG08U1M-PCB0/PIB0 N.C N.C N.C N.C N.C R/B2 R/B1 RE CE1 CE2 N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF 0.10 MAX 0.004 Unit :mm/Inch #48 #24 #25 12.40 0.488 MAX 12.00 0.472 +0.003 ( 0.25 ) 0.010 #1 0.008-0.001 0.50 0.0197 0.16 -0.03 +0.075 18.400.10 0.7240.004 0~8 0.45~0.75 0.018~0.030 +0.003 0.005-0.001 0.25 0.010 TYP 1.000.05 0.0390.002 0.125 0.035 +0.07 0.20 -0.03 +0.07 20.000.20 0.7870.008 ( 0.50 ) 0.020 6 1.20 0.047MAX 0.02 0.002 MIN K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN CONFIGURATION (TLGA) K9HCG08U1M - ICB0 / IIB0 A C B NC E D G F H NC NC L K J M N NC NC NC 7 NC 6 /RE1 Vcc R/B2 /RE2 IO7-2 Vss IO6-2 Vcc IO5-1 IO7-1 NC IO5-2 5 4 /CE1 3 2 CLE1 /CE2 R/B1 CLE2 /WE1 ALE2 Vss 1 NC NC ALE1 NC /WP2 IO0-1 /WP1 /WE2 IO4-1 IO6-1 IO0-2 Vss IO2-1 IO1-1 NC IO3-2 Vss IO3-1 IO1-2 NC IO4-2 NC IO2-2 NC NC PACKAGE DIMENSIONS 52-TLGA (measured in millimeters) Bottom View Top View 12.000.10 10.00 1.00 1.00 2.00 7 (Datum A) 6 5 4 3 2 1 B 1.00 1.00 1.30 12.000.10 A #A1 A B C 1.00 2.50 17.000.10 E F 1.00 H 1.00 2.50 G J 2.00 K 0.50 L M N Side View 17.000.10 0.10 C 7 41-0.700.05 0.1 M C AB 1.0(Max.) 12-1.000.05 0.1 M C AB 12.00 17.000.10 D (Datum B) K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN CONFIGURATION (TSOP1-DSP) K9MDG08U5M-PCB0/PIB0 N.C N.C N.C R/B4 R/B3 R/B2 R/B1 RE CE1 CE2 N.C Vcc Vss CE3 CE4 CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Dual Stacked Package 12mm x 20mm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) Unit :mm/Inch 48 - TSOP1 - 1220AF 18.80 MAX REF SEATING PLANE -A#48 n Pi 12.40 MAX REF 0.50 TYP #1 0.13~0.23 #1 #24 #25 2.35 MAX 20.000.20 0.02 MIN (0.249) BASIC GAGE PLANE (0.10) A (0.10) A TYP BOTH SIDES BOTTOM TSOP ONLY 0.399~0.600 8 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN CONFIGURATION (WELP-DSP) K9MDG08U5M-ZCB0/ZIB0 N.C N.C N.C R/B4 R/B3 R/B2 R/B1 RE CE1 CE2 N.C Vcc Vss CE3 CE4 CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin WELP Dual Stacked Package 12mm x 20mm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE STACK TYPE 48 - WELP 1220 0.08 C Unit :mm/Inch B #48 0.20 -0.02 A 1.50 #1 +0.10 #1 19.300.10 1. 00 1.50 -D 0.16 P 05 0. 0.50BSC [0.50.06] 12.000.10 AX +0.10 -0.02 M #25 1.47 MAX C 20.250.10 TOP PACKAGE DETAIL -A1.00+0.05 #24 BTM PACKAGE DETAIL 20.000.10 20.400.10 NOTE: The PAD form of the bottom view can be different by the device 9 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9PDG08U5M-LCB0/LIB0 A C B E D F G H NC NC L K J NC M N Vss NC R/B2-2 7 R/B1-2 6 /RE1 Vcc R/B2-1 /RE2 IO7-2 Vss IO6-2 IO7-1 IO5-2 IO5-1 Vcc Vcc 5 4 /CE1-1 /CE2-1 R/B1-1 /WP2 IO6-1 IO4-1 CLE1 CLE2 /WE1 IO0-1 IO2-1 Vss 3 2 ALE2 Vss 1 /CE1-2 ALE1 NC IO1-1 WP1 /WE2 IO0-2 IO1-2 NC IO3-2 Vss IO3-1 NC IO4-2 Vcc IO2-2 NC NC /CE2-2 PACKAGE DIMENSIONS 52-LLGA (measured in millimeters) Bottom View Top View 14.000.10 10.00 1.00 1.00 2.00 7 (Datum A) 6 5 4 3 2 1 B 1.00 1.00 1.30 14.000.10 A #A1 A B C 1.00 2.50 18.000.10 E F 1.00 H 1.00 2.50 G J 2.00 K 0.50 L M N Side View 18.000.10 0.10 C 10 41-0.700.05 0.1 M C AB 1.47(Max.) 12-1.000.05 0.1 M C AB 12.00 18.000.10 D (Datum B) K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY PIN DESCRIPTION Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE / CE1 CHIP ENABLE The CE / CE 1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE / CE1 control during read operation , refer to 'Page Read' section of Device operation CE2 CHIP ENABLE The CE2 input enables the second K9LBG08U0M RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B / R/B1 READY/BUSY OUTPUT The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. R/B2 READY/BUSY OUTPUT The R/B2 input enables the second K9LBG08U0M Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. There are two CE pins (CE1 & CE2) in the K9HCG08U1M, and four CE pins (CE1 & CE2 & CE3 & CE4) in the K9XDG08U5M. There are two R/B pins (R/B1 & R/B2) in the K9HCG08U1M, and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9XDG08U5M. 11 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Figure 1. K9LBG08U0M Functional Block Diagram VCC VSS A13 - A32 X-Buffers Latches & Decoders 32,768M + 1,024M Bit NAND Flash ARRAY A0 - A12 Y-Buffers Latches & Decoders (4,096 + 128)Byte x 1,048,576 Data Register & S/A Y-Gating Command Command Register CE RE WE VCC VSS I/O Buffers & Latches Control Logic & High Voltage Generator Output Driver Global Buffers I/0 0 I/0 7 CLE ALE WP Figure 2. K9LBG08U0M Array Organization 1 Block = 128 Pages (512K + 16K) Bytes 1 Page = (4K + 128)Bytes 1 Block = (4K + 128)B x 128 Pages = (512K + 16K) Bytes 1 Device = (4K+128)B x 128Pages x 8,192 Blocks = 33,792 Mbits 1,024K Pages (=8,192 Blocks) 8 bit 4K Bytes 128 Bytes I/O 0 ~ I/O 7 Page Register 4K Bytes 128 Bytes I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A8 A9 A10 A11 A12 *L *L *L Column Address Column Address 3rd Cycle A13 A14 A15 A16 A17 A18 A19 A20 Row Address 4th Cycle A21 A22 A23 A24 A25 A26 A27 A28 Row Address 5th Cycle A29 A30 A31 A32 *L *L *L *L Row Address NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. 12 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Product Introduction The K9LBG08U0M is a 33,792Mbit(35,433,480,192 bit) memory organized as 1,048,576 rows(pages) by 4,224x8 columns. Spare 128 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9LBG08U0M. The K9LBG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space requires 33 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9LBG08U0M. Table 1. Command Sets Function 1st Set 2nd Set Read 00h 30h Read for Copy Back 00h 35h Read ID 90h - Reset FFh - Acceptable Command during Busy O Page Program 80h 10h Copy-Back Program 85h 10h Block Erase 60h D0h 85h - Random Data Output(1) 05h E0h Read Status 70h O Chip1 Status F1h O Chip2 Status F2h O Random Data Input (1) 60h----60h Two-Plane Read (3) Two-Plane Read for Copy-Back Two-Plane Random Data Output (1) (3) Two-Plane Page Program(2) Two-Plane Copy-Back Program(2) Two-Plane Block Erase Page Program with 2KB Data (2) Copy-Back Program with 2KB Data (2) 30h 60h----60h 35h 00h----05h E0h 80h----11h 81h----10h 85h----11h 81h----10h 60h----60h D0h 80h----11h 80h----10h 85h----11h 85h----10h NOTE : 1. Random Data Input/Output can be executed in a page. 2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h//F2h and FFh. 3. Two-Plane Random Data msut be used after Two-Plane Read operation 4. Interleave-operation between two chips is allowed. It's prohibited to use F1h and F2h commands for other operations except interleave-operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 13 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Memory Map K9LBG08U0M is arranged in four 8Gb memory planes. Each plane contains 2,048 blocks and 4224 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that two-plane program/erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. For example, two-plane program/erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program/erase operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed Plane 0 (2048 Block) Block 0 Plane 2 (2048 Block) Plane 1 (2048 Block) Block 4096 Block 1 Plane 3 (2048 Block) Block 4097 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Block 2 Block 4098 Block 3 Block 4099 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Block 4092 Block 8188 Block 4093 Block 8189 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Block 4094 Block 8190 Block 4095 Block 8191 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 Page 126 Page 127 4224byte Page Registers 4224byte Page Registers 4224byte Page Registers 4224byte Page Registers 14 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating VCC -0.6 to + 4.6 Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature K9XXG08UXM-XCB0 K9XXG08UXM-XCB0 K9XXG08UXM-XIB0 Short Circuit Current V VIN -0.6 to + 4.6 VI/O -0.6 to Vcc+0.3 (<4.6V) -10 to +125 TBIAS K9XXG08UXM-XIB0 Unit C -40 to +125 TSTG -65 to +150 C Ios 5 mA NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9XXG08UXM-XCB0 :TA=0 to 70C, K9XXG08UXM-XIB0:TA=-40 to 85C) Parameter K9LBG08U0M Symbol Min Typ. Max Unit Supply Voltage VCC 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 V DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Symbol Page Read with Serial Access Operating Current Program ICC1 Erase Test Conditions tRC=25ns, CE=VIL, IOUT=0mA (K9XDG08U5M: tRC=50ns) Min Typ Max - 15 35 ICC2 - - 15 35 ICC3 - - 15 35 Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 20 100 ILI VIN=0 to Vcc(max) - - 20 ILO VOUT=0 to Vcc(max) Input Leakage Current Output Leakage Current Input High Voltage VIH(1) Input Low Voltage, All inputs VIL(1) Output High Voltage Level VOH IOH=-400A - - 20 - 0.8 x Vcc - VCC+0.3 - -0.3 - 0.2 x Vcc 2.4 - - Output Low Voltage Level VOL IOL=2.1mA - - 0.4 Output Low Current(R/B) IOL(R/B) VOL=0.4V 8 10 - NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less. 2. Typical value are measured at Vcc=3.3V, TA=25C. Not 100% tested. 3. The typical value of the K9HCG08U1M's ISB2 is 40A and the maximum value is 200A. 4. The typical value of the K9XDG08U5M's ISB2 is 80A and the maximum value is 400A. 5. The maximum value of K9HCG08U1M-P's ILI and ILO is 40A and the maximum value of K9HCG08U1M-I/L's ILI and ILO is 20A. 6. The maximum value of K9PDG08U5M-L's ILI and ILO is 40A and K9MDG08U5M-P/Z's ILI and ILO is 80A. 15 Unit mA A V mA K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY VALID BLOCK Symbol Min Typ. Max Unit K9LBG08U0M Parameter NVB 8,072 - 8,192 Blocks K9HCG08U1M NVB 16,144 - 16,384 Blocks K9XDG08U5M NVB 32,288 - 32,768 Blocks NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. 3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. * : Each K9LBG08U0M chip in the K9HCG08U1M, K9XDG08U5M has Maximum 120 invalid blocks. AC TEST CONDITION (K9XXG08UXM-XCB0: TA=0 to 70C, K9XXG08UXM-XIB0:TA=-40 to 85C,K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted) Parameter K9XXG08UXM Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 1 TTL GATE and CL=50pF(K9LBG08U0M-P, K9HCG08U1M-I) Output Load (Vcc:3.0V +/-10%) 1 TTL GATE and CL=30pF (K9HCG08U1M-P/Z, K9XDG08U5M-P/Z/L) CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz) Symbol Test Condition Min Input/Output Capacitance CI/O VIL=0V Input Capacitance CIN VIN=0V Item Max K9HCG08U1M K9MDG08U5M - 10 20 40 pF - 10 20 40 pF NOTE : 1. Capacitance is periodically sampled and not 100% tested. 2. K9HCG08U1M-IXB0's capacitance(I/O, Input) is 13pF and K9PDG08U5M-LXB0's capacitance(I/O, Input) is 23pF. MODE SELECTION WE Unit K9LBG08U0M CLE ALE CE RE WP H L L H X Mode L H L H X H L L H H L H L H H L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) Read Mode Write Mode Command Input Address Input(5clock) Command Input Address Input(5clock) X X X X X H During Erase(Busy) X X(1) X X X L Write Protect X X H X X 0V/VCC(2) NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. 16 Stand-by K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Program / Erase Characteristics Symbol Min Typ Max Unit Program Time Parameter tPROG - 0.8 3 ms Dummy Busy Time for Multi Plane Program tDBSY 0.5 1 s Number of Partial Program Cycles in the Same Page Nop - - 1 cycle Block Erase Time tBERS - 1.5 10 ms NOTE 1. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 2. Typical Program time is defined as the time within which more than 50% of the whole pages are programed at 3.3V Vcc and 25C temperature. 3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the page group A and B(Table 5). Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123 Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127 AC Timing Characteristics for Command / Address / Data Input Min Parameter Symbol K9LBG08U0M K9XDG08U5M K9HCG08U1M CLE Setup Time Max K9LBG08U0M K9HCG08U1M K9XDG08U5M Unit CLS(1) 12 25 - - ns CLE Hold Time tCLH 5 10 - - ns CE Setup Time t CS(1) 20 35 - - ns tCH 5 10 - - ns WE Pulse Width tWP 12 25 - - ns ALE Setup Time tALS(1) 12 25 - - ns CE Hold Time t ALE Hold Time tALH 5 10 - - ns Data Setup Time tDS(1) 12 20 - - ns Data Hold Time tDH 5 10 - - ns Write Cycle Time tWC 25 45 - - ns - - ns WE High Hold Time Address to Data Loading Time tWH 10 15 tADL(2) 100(2) 100 NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 17 ns K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY AC Characteristics for Operation Min Parameter Symbol K9LBG08U0M K9HCG08U1M Data Transfer from Cell to Register Max K9XDG08U5M K9LBG08U0M K9HCG08U1M Unit s tR - ALE to RE Delay tAR 10 10 - ns CLE to RE Delay tCLR 10 10 - ns Ready to RE Low tRR 20 20 - ns RE Pulse Width tRP 12 25 - ns WE High to Busy tWB - - 100 100 ns Read Cycle Time tRC 25 50 - - ns RE Access Time tREA - - 20 30 ns CE Access Time tCEA - - 25 45 ns RE High to Output Hi-Z tRHZ - - 100 100 ns CE High to Output Hi-Z tCHZ - - 30 30 ns CE High to ALE or CLE Don't Care 60 K9XDG08U5M 60 tCSD 0 0 - - ns RE High to Output Hold tRHOH 15 15 - - ns RE Low to Output Hold tRLOH 5 - - - ns CE High to Output Hold tCOH 15 15 - - ns RE High Hold Time tREH 10 15 - - ns tIR 0 0 - - ns RE High to WE Low tRHW 100 100 - - ns WE High to RE Low tWHR 60 60 - - Device Resetting Time(Read/Program/Erase) tRST - - Output Hi-Z to RE Low NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s. 18 5/10/500 (1) 5/10/500 ns (1) s K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid block has non-FFh data at the column address of 4,096.The initial invalid block information is also erasable in most cases, and it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address * Create (or update) Initial Invalid Block(s) Table No Check "FFh" at the column address 4,096 of the last page in the block Check "FFh" ? Yes No Last Block ? Yes End Figure 3. Flow chart to create initial invalid block table. 19 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement should be done upon erase or program error. Failure Mode Write Read ECC Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Up to Four Bit Failure Verify ECC -> ECC Correction : Error Correcting Code --> RS Code etc. Example) 4bit correction / 512-byte Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? * Program Error No Yes No I/O 0 = 0 ? Yes Program Completed * 20 : If program operation results in an error, map out the block including the page in error and copy the target data to another block. K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data ECC Generation No I/O 6 = 1 ? or R/B = 1 ? Reclaim the Error Yes * No Erase Error No Verify ECC Yes I/O 0 = 0 ? Page Read Completed Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st (n-1)th nth { Block A 1 an error occurs. (page) 1st (n-1)th nth Buffer memory of the controller. { Block B 2 (page) * Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme. 21 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY NAND Flash Technical Notes (Continued) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. Page 127 (128) Page 127 : Page 31 (32) Page 2 Page 1 Page 0 (3) (2) (1) : Page 31 : (1) : Page 2 Page 1 Page 0 Data register (3) (32) (2) Data register From the LSB page to MSB page DATA IN: Data (1) (128) Ex.) Random page program (Prohibition) Data (128) DATA IN: Data (1) Data (128) Interleave Page Program K9LBG08U0M is composed of two K9GAG08U0Ms. K9LBG08U0M provides interleaving operation between two K9GAG08U0Ms. This interleaving page program improves the system throughput almost twice compared to non-interleaving page program. At first, the host issues page program command to one of the K9GAG08U0M chips, say K9GAG08U0M(chip #1). Due to this K9LBG08U0M goes into busy state. During this time, K9GAG08U0M(chip #2) is in ready state. So it can execute the page program command issued by the host. After the execution of page program by K9GAG08U0M(chip #1), it can execute another page program regardless of the K9GAG08U0M(chip #2). Before that the host needs to check the status of K9GAG08U0M(chip #1) by issuing F1h command. Only when the status of K9GAG08U0M(chip #1) becomes ready status, host can issue another page program command. If the K9GAG08U0M(chip #1) is in busy state, the host has to wait for the K9GAG08U0M(chip #1) to get into ready state. Similarly, K9GAG08U0M(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9GAG08U0M(chip #2) by issuing F2h command. When the K9GAG08U0M(chip #2) shows ready state, host can issue another page program command to K9GAG08U0M(chip #2). This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation. NOTES : During interleave operations, 70h command is prohibited. 22 80h A32 : Low Add & Data 10h 80h Add & Data A 10h busy of Chip #1 A32 : High B busy of Chip #2 F1h or F2h Command C D another page program on Chip #1 23 Chip 1 : Ready, Chip 2 : Busy Chip 1 : Ready, Chip 2 : Ready C D Chip 2 : Busy Chip 1 : Busy, B Chip 2 : Ready Chip 1 : Busy, Operation A Status Cxh Cxh 8xh 8xh F1h Cxh 8xh 8xh Cxh F2h Status Command / Data According to the above process, the system can operate page program on chip #1 and chip #2 alternately. State A : Chip #1 is executing a page program operation and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip #1 and chip #2 are executing page program operation. State C : Page program on chip #1 is terminated, but page program on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If chip #1 is ready, status I/O6 is "1" and the system can issue another page program command to chip #1. State D : Chip #1 and Chip #2 are ready. R/B internal only R/B (#2) internal only R/B (#1) I/OX Interleave Page Program K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 60h A32 : Low Add D0h 60h A D0h busy of Chip #1 A32 : High Add B busy of Chip #2 F1h or F2h Command C D another Block Erase on Chip #1 24 Chip 1 : Ready, Chip 2 : Busy Chip 1 : Ready, Chip 2 : Ready C D Chip 2 : Busy Chip 1 : Busy, B Chip 2 : Ready Chip 1 : Busy, Operation A Status Cxh Cxh 8xh 8xh F1h Cxh 8xh 8xh Cxh F2h Status Command / Data According to the above process, the system can operate block erase on chip #1 and chip #2 alternately. State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip #1 and chip #2 are executing block erase operation. State C : Block erase on chip #1 is terminated, but block erase on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If chip #1 is ready, status I/O6 is "1" and the system can issue another block erase command to chip #1. State D : Chip #1 and Chip #2 are ready. R/B internal only R/B (#2) internal only R/B (#1) I/OX Interleave Block Erase K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 25 R/B 1 F1h or F2h* Command 80h 11h t DBSY C tPROG of Chip #2 A32 : Low Add & Data 81h A32 :Low Add & Data 10h 80h A32: High Add & Data 11h D A t DBSY Add & Data Chip #1 A32 :High t PROG of 81h 10h State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip #1 and chip #2 are executing page program operation. State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1. F2h command is required to check the status of chip #2 to issue the next page program command to chip #2. According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately. internal only R/B (#2) internal only R/B (#1) I/OX R/B internal only R/B (#2) internal only R/B (#1) I/OX tPROG of Chip #2 B Interleave Two-Plane Page Program 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 26 1 Add A32 : Low F1h or F2h* Command 60h 60h Add D0h Chip #2 C tBERS of A32 :Low 60h Add A32 : High A 60h t BERS of D0h Chip #1 A32 :High Add D B t BERS of Chip #2 State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip #1 and chip #2 are executing block erase operation. State C : Block erase on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing block erase operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next block erase command to chip #1. F2h command is required to check the status of chip #2 to issue the next block erase command to chip #2. According to the above process, the system can operate two-plane block erase on chip #1 and chip #2 alternately. R/B internal only R/B (#2) internal only R/B (#1) I/OX R/B internal only R/B (#2) R/B (#1) internal only I/OX Interleave Two-Plane Block Erase 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 27 1 80h Add F1h or F2h* Command A32 : Low Data in C tPROG of 10h chip #1 00h Add A tPROG of chip #1 A32 : High 30h tR of B chip #2 D Data out State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a read command to chip #2. State B : Both chip #1 is executing page program operation and chip #2 is executing read operation. State C : Read operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing page program operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next command to chip #1. F2h command is required to check the status of chip #2 to issue the next command to chip #2. As the above process, the system can operate Interleave read to page porgram on chip #1 and chip #2 alternatively. R/B internal only R/B (#2) internal only R/B (#1) I/OX R/B internal only R/B (#2) internal only R/B (#1) I/OX Interleave Read to Page Program Operation 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 28 1 85h 85h Add D A32 : High Add A32 : Low 10h 10h Add A chip #1 E chip #2 A32 : Low tPROG of 00h Add A32 : High tPROG of 00h 35h 35h tR of tR of F chip #1 B chip #2 Command G F1h or F2h* Command C F1h or F2h* H State A : Chip #1 is executing a copy-back program operation, and chip #2 is in ready state. So the host can issue a read for copy-back command to chip #2. State B : Both chip #1 is executing copy-back program operation and chip #2 is executing read for copy-back operation. State C : Read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing copy-back program operation. State D : Both chip #1 and chip #2 are ready. State E : Chip #2 is executing a copy-back program operation, and chip #1 is in ready state. So the host can issue a read for copy-back command to chip #1. State F : Both chip #2 is executing copy-back program operation and chip #1 is executing read for copy-back operation. State C : Read for copy-back operation on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing copy-back program operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next command to chip #1. F2h command is required to check the status of chip #2 to issue the next command to chip #2. As the above process, the system can operate Interleave copy-back program on chip #1 and chip #2 alternatively. R/B internal only R/B (#2) R/B (#1) internal only I/OX R/B internal only R/B (#2) internal only R/B (#1) I/OX Interleave Copy-Back Program Operation 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 29 R/B internal only R/B (#2) internal only R/B (#1) I/OX R/B 1 internal only R/B (#2) internal only R/B (#1) I/OX Add 85h A20 : Low A32 : Low Add A20 : Low A32 : Low 60h 11h 60h tDBSY 81h A20 : High A32 : Low Add A20 : High A32 : Low Add 35h tR 10h 00h Interleave Two-Plane Copy Back Program Add A20 : Low A32 : High 60h A20 : Low A32 : Low Add 05h 60h Add E0h A20 : High A32 : High Add 35h tR 00h Data Out A20 : Low A32 : High Add 00h Add 05h A E0h Add tPROG of Chip #1 05h A20 : High A32 : Low Add Data Out E0h Data Out 2 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 30 R/B internal only R/B (#2) internal only 3 2 05h tPROG of Chip #1 A20 : High A32 : High Add Add Data Out tPROG of Chip #2 E0h 85h A20 : Low A32 : High Add C 11h tDBSY 81h A20 : High A32 : Hgih Add 10h Command D F1h or F2h* State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip #1 and chip #2 are executing page program operation. State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1. F2h command is required to check the status of chip #2 to issue the next page program command to chip #2. According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately. R/B (#1) I/OX R/B internal only R/B (#2) internal only R/B (#1) 00h I/OX Interleave Two-Plane Copy Back Program B tPROG of Chip #2 3 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY System Interface Using CE don't-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. Figure 4. Program Operation with CE don't-care. CLE CE don't-care CE Data Input Data Input WE ALE I/Ox 80h Address(5Cycles) tCS tCH 10h tCEA CE CE tREA tWP RE WE I/O0~7 out Figure 5. Read Operation with CE don't-care. CLE CE don't-care CE RE ALE tR R/B I/Ox WE 00h Address(5Cycle) Data Output(serial access) 30h 31 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY NOTE Device K9LBG08U0M I/O DATA ADDRESS I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 I/O 0 ~ I/O 7 ~4,224byte A0~A7 A8~A12 A13~A20 A21~A28 A29~A32 Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALS tALH ALE tDH tDS I/Ox Command Address Latch Cycle tCLS CLE CE tWC tCS tWH tALH tALS tWC tWP tWP WE tWC tALS tWP tWP tALH tWH tALS tWC tWH tALH tALS tWH tALH tALS tALH ALE tDS I/Ox tDH Col. Add1 tDS tDH Col. Add2 32 tDS tDH Row Add1 tDS tDH Row Add2 tDS tDH Row Add3 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Input Data Latch Cycle tCLH CLE tCH CE tWC tALS ALE tWP tWH tDH tDS tDH tDS tDH tDS tWP tWP WE I/Ox DIN final DIN 1 DIN 0 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) tRC CE tREA tREA tREH tCHZ(1) tREA tCOH RE tRHZ(1) tRHZ(1) I/Ox Dout Dout tRHOH(2) Dout tRR R/B NOTES : 1. Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRHOH starts to be valid when frequency is lower than 33MHz. 33 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) CE tRC tREH tRP tCHZ(1) tCOH RE tCEA I/Ox t tRHZ(1) tREA tRHOH(2) RLOH(2) tREA Dout Dout tRR R/B NOTES : 1. Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. Status Read Cycle tCLR CLE tCLS tCLH tCS CE tWP tCH WE tCEA tCHZ tCOH tWHR RE tDS I/Ox tDH tIR tREA tRHZ tRHOH Status Output 70h/F1h 34 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Read Operation tCLR CLE CE tWC WE tCSD tWB tAR ALE tR tRHZ tRC RE I/Ox 00h Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 30h Dout N Dout N+1 Row Address tRR Dout M Busy R/B Read Operation(Intercepted by CE) tCLR CLE CE tCSD WE tCHZ tWB tAR tCOH ALE tRC tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Column Address Row Add1 Row Add2 Row Add3 Dout N 30h Row Address Busy R/B 35 Dout N+1 Dout N+2 36 R/B I/Ox RE ALE WE CE CLE 00h Col. Add2 Column Address Col. Add1 Random Data Output In a Page Row Add2 Row Add3 Row Address Row Add1 30h/35h Busy tRR tR tWB tAR Dout N tRC Dout N+1 tRHW 05h Col Add1 Col Add2 Column Address E0h tWHR tCLR Dout M tREA Dout M+1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Page Program Operation CLE CE tWC tWC tWC WE tWB tADL tPROG tWHR ALE I/Ox 80h Co.l Add1 Col. Add2 SerialData Column Address Input Command Row Add1 RE Din Din N M 1 up to m Byte Serial Input Row Add2 Row Add3 Row Address Program Command I/O0=0 Successful Program I/O0=1 Error in Program NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 37 I/O0 Read Status Command R/B 70h 10h 38 R/B I/Ox RE ALE WE Col. Add1 Col. Add2 tADL Row Add2 Row Add3 Row Address Row Add1 tWC Din M Serial Input Din N Col. Add1 Col. Add2 tADL Random Data Column Address Input Command 85h tWC Din K Serial Input Din J NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. Serial Data Column Address Input Command 80h tWC CE CLE 10h Program Command tWB tPROG Page Program Operation with Random Data Input Read Status Command 70h tWHR I/O0 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY R/B I/Ox RE ALE WE CE CLE Column Address Row Address Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 35h tR tWB Busy Data 1 tRC Data N Column Address Row Address Data 1 tADL Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Copy-Back Data Input Command 85h NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 00h tWC 39 Data N 10h tWB 70h I/Ox tWHR Read Status Command tPROG I/O0=0 Successful Program I/O0=1 Error in Program Busy Copy-Back Program Operation with Random Data Input K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Block Erase Operation CLE CE tWC WE tBERS tWB tWHR ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0 Busy R/B Auto Block Erase Setup Command Erase Command Row Address Read Status Command 40 I/O0=0 Successful Erase I/O0=1 Error in Erase 41 R/B I/Ox RE ALE WE CE CLE R/B I/Ox RE ALE WE CE CLE 1 00h A0~A7 A8~A12 A13~A20 A21~A28 A29~A32 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' : Valid A32 Row Address A13~A20 A21~A28 A29~A32 05h 30h tWB : E0h Valid Column Address A8~A12 Dout N Dout N+1 00h A0~A7 A8~A12 A13~A20 A21~A28 A29~A32 05h A0~A7 A8~A12 : Valid Column Address A0 ~ A12 A0 ~ A12 : Fixed 'Low' A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 Column Address Row Address E0h tREA tCLR tREA tRC Busy tWHR tRHW tW tWC tR tWHR tCLR A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 Row Address A13~A20 A21~A28 A29~A32 A0~A7 60h tW tWC A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' A20 : Fixed 'Low' A21 ~ A31: Fixed 'Low' A32 : Must be same as previous A32 Column Address Row Address tW tWC 60h tW tWC Two-Plane Page Read Operation with Two-Plane Random Data Out Dout M tRC Dout M+1 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY R/B I/Ox RE ALE WE Din N Din M 42 A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31: Fixed 'Low' A32 : Valid Address & Data Input tDBSY : 11h typ. 500ns max. 1s tDBSY Note tDBSY 81h 81h Din N 10h tPROG Program Confirm Command (True) 10h Din M tWB tPROG A0 ~ A12 : Valid A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 Address & Data Input A0~A7 A8~A12 A13~A20 A21~A28A29~A32 Note: Any command between 11h and 81h is prohibited except 70h/F1h/F2 and FFh. I/O0~7 80h Ex.) Two-Plane Page Program R/B tWB 11h Program Page Row Address 1 up to 2112 Byte Data Command (Dummy) Serial Input A0~A7 A8~A12 A13~A20 A21~A28A29~A32 Serial Data Column Address Input Command 80h tWC CE CLE Two-Plane Page Program Operation I/O 0 70h I/O0=0 Successful Program I/O0=1 Error in Program Read Status Command 70h K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 43 Row Address 60h tWC I/O0~7 R/B 60h A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid Row Add1,2,3 Address 60h D0h A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 Row Add1,2,3 D0h ~ A25 A9Address D0h tWB tBERS Erase Confirm Command Row Address Row Add1 Row Add2 Row Add3 Block Erase Setup Command2 Row Add1 Row Add2 RowD0h Add3 Block Erase Setup Command1 60h tWC Ex.) Address Restriction for Two-Plane Block Erase Operation R/B I/OX RE ALE WE CE CLE Two-Plane Block Erase Operation 70h Busy tBERS I/O 0 I/O 0 = 0 Successful Erase I/O 0 = 1 Error in Erase Read Status Command 70h tWHR K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Read ID Operation CLE CE WE tAR ALE RE tREA I/Ox 00h 90h Read ID Command Address. 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Maker Code Device Code Device Device Code(2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle K9LBG08U0M D7h 55h B6h 78h K9HCG08U1M Same as each K9LBG08U0M in it. K9XDG08U5M 44 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY ID Definition Table 90 ID : Access command = 90H Description 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, etc Page Size, Block Size, Spare Size, Organization, Serial Access Minimum Plane Number, Plane Size 3rd ID Data Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 Internal Chip Number 1 2 4 8 Cell Type 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell Number of Simultaneously Programmed Pages 1 2 4 8 Interleave Program Between multiple chips Not Support Support Cache Program Not Support Support 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4th ID Data Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB Block Size (w/o redundant area ) 64KB 128KB 256KB 512KB Redundant Area Size ( byte/512byte) 8 16 Organization x8 x16 Serial Access Minimum 50ns/30ns 25ns Reserved Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 45 0 0 1 1 0 1 0 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 5th ID Data Description Plane Number 1 2 4 8 Plane Size (w/o redundant Area) 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 0 0 1 1 0 0 0 0 1 1 1 1 Reserved 0 46 0 0 1 1 0 0 1 1 I/O1 I/O0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes of data within the selected page are transferred to the data registers in less than 60s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns(K9XDG08U5M : 50ns) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Figure 6. Read Operation CLE CE WE ALE tR R/B RE I/Ox 00h Address(5Cycle) Data Output(Serial Access) 30h Col Add1,2 & Row Add1,2,3 Data Field Spare Field 47 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Figure 7. Random Data Output In a Page tR R/B RE I/Ox Address 5Cycles 00h Data Output 30h/35h 05h Address 2Cycles E0h Data Output Col Add1,2 & Row Add1,2,3 Data Field Data Field Spare Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 4,224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 8. Program & Read Status Operation tPROG R/B "0" I/Ox 80h Address & Data Input 10h 70h Pass I/O0 Col Add1,2 & Row Add1,2,3 "1" Data Fail 48 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Figure 9. Random Data Input In a Page tPROG R/B "0" I/Ox 80h Address & Data Input Address & Data Input 85h 10h Col Add1,2 Data Col Add1,2 & Row Add1,2,3 Data Pass I/O0 70h "1" Fail COPY-BACK PROGRAM Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,224-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. Figure 10. Page Copy-Back Program Operation tR tPROG R/B 00h Add.(5Cycles) Data Output 35h I/Ox Col. Add.1,2 & Row Add.1,2,3 Source Address 85h Add.(5Cycles) 10h 70h I/O0 Col. Add.1,2 & Row Add.1,2,3 Destination Address "0" Pass "1" Note: 1. Copy-Back Program operation is allowed only within the same memory plane. Fail Figure 11. Page Copy-Back Program Operation with Random Data Input 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address Data Output I/Ox tPROG tR R/B 85h Add.(5Cycles) Data Col. Add.1,2 & Row Add.1,2,3 Destination Address 49 85h Add.(2Cycles) Data 10h Col. Add.1,2 There is no limitation for the number of repetition. 70h K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A20 to A32 is valid while A13 to A19 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence. Figure 13. Block Erase Operation tBERS R/B "0" I/Ox 60h Address Input(3Cycle) Pass I/O0 70h D0h "1" Row Add. : A13 ~ A32 Fail TWO-PLANE PAGE READ Two-Plane Page Read is an extension of Page Read, for a single plane with 4,224 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of two pages. Two-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected from each plane. After Read Confirm command(30h) the 8,448 bytes of data within the selected two page are transferred to the data registers in less than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin. Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences. The restrictions for Two-Plane Page Program are shown in Figure 14. Two-Plane Read must be used in the block which has been programmed with Two-Plane Page Program. Figure 14. Two-Plane Page Read Operation with Two-Plane Random Data Out tR R/B I/OX 60h Address (3 Cycle) 60h Row Add.1,2,3 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' : Valid A32 30h Address (3 Cycle) Row Add.1,2,3 A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 :Valid A32 : Must be same as previous A32 1 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 Address (2 Cycle) Data Output Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' A20 : Fixed 'Low' A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 1 E0h : Valid 2 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 2 Address (2 Cycle) Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' A20 : Fixed 'High' A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 50 : Valid E0h Data Output K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY TWO-PLANE PAGE PROGRAM Two-Plane Page Program is an extension of Page Program, for a single plane with 4,224 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a simultaneous programming of two pages. After writing the first set of data up to 4,224 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h/F1h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane Page Program is shown in Figure15. Figure 15. Two-Plane Page Program tDBSY R/B I/O0 ~ 7 80h Address & Data Input 11h tPROG 81h Address & Data Input Note*2 A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid A0 ~ A12 : Valid A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 NOTE : 1. It is noticeable that physically same row address is applied to two planes . 2. Any command between 11h and 81h is prohibited except 70h/F1h/F2 and FFh. Data Input 80h 11h 10h 81h 10h Plane 0 (2048 Block) Plane 1 (2048 Block) Block 0 Block 1 Block 2 Block 3 Block 4092 Block 4094 Block 4093 Block 4095 51 70h K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY TWO-PLANE BLOCK ERASE Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/ Busy status bit (I/O 6). Figure 16. Two-Plane Erase Operation tBERS R/B I/OX 60h Address (3 Cycle) A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid 60h Address (3 Cycle) D0h A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 52 70h I/O0 "1" Fail "0" Pass K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY TWO-PLANE COPY-BACK PROGRAM Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4224 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 4224 byte page registers enables a simultaneous programming of two pages. Figure 17. Two-Plane Copy-Back Program Operation tR R/B I/OX 60h Address (3 Cycle) 60h 35h Address (3 Cycle) Row Add.1,2,3 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid Row Add.1,2,3 A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 1 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 Address (2 Cycle) Data Output Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 1 E0h : Valid 2 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 Address (2 Cycle) Data Output Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 2 E0h : 3 Valid tPROG tDBSY R/B I/Ox 85h 3 Add.(5Cycles) Col. Add.1,2 & Row Add.1,2,3 Destination Address 11h 81h Note3 Add.(5Cycles) 10h Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A12 : Fixed 'Low' A13 ~ A19 : Fixed 'Low' A20 : Fixed 'Low' A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 A0 ~ A12 : Fixed 'Low' A13 ~ A19 : Valid A20 : Fixed 'High' A21 ~ A31 : Valid A32 : Must be same as previous A32 53 70h K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Plane0 Plane1 Source page Source page Target page Target page (1) : Two-Plane Read for Copy Back (2) : Two-Plane Random Data Out (1) (2) (3) Data Field (1) Spare Field (2) (3) Data Field (3) : Two-Plane Copy-Back Program Spare Field Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh. 54 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Figure 18. Two-Plane Copy-Back Program Operation with Random Data Input tR R/B I/OX 60h Address (3 Cycle) 60h Row Add.1,2,3 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid 35h Address (3 Cycle) Row Add.1,2,3 A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 1 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 Address (2 Cycle) Data Output Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 1 E0h : Valid 2 R/B I/Ox 00h Address (5 Cycle) 05h Col. Add. 1,2 & Row Add.1,2,3 Address (2 Cycle) Data Output Col. Add.1,2 A0 ~ A12 : Fixed 'Low' A0 ~ A12 A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 2 E0h : 3 Valid tDBSY R/B I/Ox 85h Add.(5Cycles) Data 85h Col. Add.1,2 & Row Add.1,2,3 3 Add.(2Cycles) Data 11h Note3 Col. Add.1,2 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' A20 : Fixed 'Low' A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 tPROG R/B I/Ox 81h 4 Add.(5Cycles) Data 85h Col. Add.1,2 & Row Add.1,2,3 Add.(2Cycles) Data Col. Add.1,2 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Valid : Fixed 'High' A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh. 55 10h 4 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h or F1h/F2h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific 70h Status Register definitions and table 3 for specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. Table 2. 70h Read Status Register Definition I/O No. Page Program Block Erase Read Definition I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" I/O 1 Not use Not use Not use Don't -cared I/O 2 Not use Not use Not use Don't -cared I/O 3 Not Use Not Use Not Use Don't -cared I/O 4 Not Use Not Use Not Use Don't -cared I/O 5 Not Use Not Use Not Use Don't -cared I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" I/O 7 Write Protect Write Protect Write Protect Protected : "0" Fail : "1" Ready : "1" Not Protected : "1" NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. Table 3. F1h/F2h Read Status Register Definition I/O No. Page Program Block Erase Read I/O 0 Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Definition Fail : "1" I/O 1 Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1" I/O 2 Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1" I/O 3 Not Use Not Use Not Use Don't -cared I/O 4 Not Use Not Use Not Use Don't -cared I/O 5 Not Use Not Use Not Use Don't -cared I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" I/O 7 Write Protect Write Protect Write Protect Protected : "0" NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. 56 Ready : "1" Not Protected : "1" K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence. Figure 19. Read ID Operation tCLR CLE tCEA CE WE tAR ALE RE tWHR I/OX 90h 00h tREA Address. 1cycle ECh Maker code Device Code 3rd Cyc. 4th Cyc. 5th Cyc. Device code Device Device Code(2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle K9LBG08U0M D7h 55h B6h 78h K9HCG08U1M Same as each K9LBG08U0M in it. K9XDG08U5M RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 20 below. Figure 20. RESET Operation tRST R/B I/OX FFh Table 4. Device Status Operation mode After Power-up After Reset 00h Command is latched Waiting for next command 57 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Table 5. Paired Page Address Information Paired Page Address Paired Page Address 00h 04h 01h 05h 02h 08h 03h 09h 06h 0Ch 07h 0Dh 0Ah 10h 0Bh 11h 0Eh 14h 0Fh 15h 12h 18h 13h 19h 16h 1Ch 17h 1Dh 1Ah 20h 1Bh 21h 1Eh 24h 1Fh 25h 22h 28h 23h 29h 26h 2Ch 27h 2Dh 2Ah 30h 2Bh 31h 2Eh 34h 2Fh 35h 32h 38h 33h 39h 36h 3Ch 37h 3Dh 3Ah 40h 3Bh 41h 3Eh 44h 3Fh 45h 42h 48h 43h 49h 46h 4Ch 47h 4Dh 4Ah 50h 4Bh 51h 4Eh 54h 4Fh 55h 52h 58h 53h 59h 56h 5Ch 57h 5Dh 5Ah 60h 5Bh 61h 5Eh 64h 5Fh 65h 62h 68h 63h 69h 66h 6Ch 67h 6Dh 6Ah 70h 6Bh 71h 6Eh 74h 6Fh 75h 72h 78h 73h 79h 76h 7Ch 77h 7Dh 7Ah 7Eh 7Bh 7Fh Note: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged(Table 5). 58 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 21). Its value can be determined by the following guidance. Rp VCC ibusy Ready Vcc R/B open drain output VOH VOL : 0.4V, VOH : 2.4V CL VOL Busy tf tr GND Device Figure 21. Rp vs tr ,tf & Rp vs ibusy @ Vcc = 3.3V, Ta = 25C , CL = 50pF 2.4 tr,tf [s] 2m Ibusy [A] 200 Ibusy 200n 150 1.2 100 100n 0.6 50 3.6 tf 1K 1m 0.8 tr 3.6 3.6 2K 3K Rp(ohm) 4K 3.6 Rp value guidance Rp(min, 3.3V part) = 3.2V VCC(Max.) - VOL(Max.) IOL + IL = 8mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr 59 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY DATA PROTECTION & POWER UP SEQUENCE The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10s is required before internal circuit gets ready for any command sequences as shown in Figure 22. The two step command sequence for program/erase provides additional software protection. Figure 22. AC Waveforms for Power Transition ~ 2.5V High VCC WE 10s WP 60 ~ 2.5V K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 2KB PROGRAM OPERATION TIMING GUIDE K9GAG08X0M is designed also to support the program operation with 2KByte data to offer the backward compatibility to the controller which uses the NAND with 2KByte page. The command sequences are as follows. Figure A-1. (2KB X 2) Program Operation I/O0~7 tPROG tDBSY R/B 80h Address & Data Input 80h 11h Note Col Add1,2 & Row Add 1,2,3 2112 Byte Data Address & Data Input 10h 70h Col Add1,2 & Row Add 1,2,3 2112 Byte Data A0 ~ A12 : Valid A13 ~ A19 : Vaild : Must be same as previous A20 A20 A21 ~ A31 : Valid : Must be same as previous A32 A32 A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' : Valid A20 A21 ~ A31 : Fixed 'Low' A32 : Valid Note: Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh. Figure A-2. (2KB X 2) Copy-Back Program Operation tR R/B Add.(5Cycles) 00h Data Output 35h Col. Add.1,2 & Row Add.1,2,3 Source Address I/Ox 1 tPROG tDBSY R/B I/Ox 85h 1 Add.(5Cycles) Data 11h 85h Add.(5Cycles) Data 10h Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Destination Address Destination Address A0 ~ A12 : Valid A13 ~ A19 : Valid A20 : Must be same as previous A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' A20 : Valid A21 ~ A31 : Fixed 'Low' A32 : Valid Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 85h is prohibited except 70h/F1h/F2h and FFh. 61 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY Figure A-3. (2KB X 2) Copy-Back Program Operation with Random Data Input tR R/B 00h Add.(5Cycles) Data Output 35h Col. Add.1,2 & Row Add.1,2,3 Source Address I/Ox 1 tDBSY R/B I/Ox 85h Add.(5Cycles) Data 85h Col. Add.1,2 & Row Add.1,2,3 1 Add.(2Cycles) Data 11h Note3 Col. Add.1,2 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' A20 : Valid A21 ~ A31 : Fixed 'Low' A32 : Valid tPROG R/B I/Ox 85h 2 Add.(5Cycles) Data 85h Col. Add.1,2 & Row Add.1,2,3 Add.(2Cycles) Data Col. Add.1,2 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Valid A20 : Must be same as previous A20 A21 ~ A31 : Valid A32 : Must be same as previous A32 Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 85h is prohibited except 70h/F1h/F2h and FFh. 62 10h 2 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY 2-PLANE PAGE PROGRAM OPERATION USING 4KB BUFFER RAM K9GAG08X0M consists of 4KB pages and can support Two-Plane program operation. The internal RAM requirement for a controller is 8KB, but for those controllers which support less than 8KB RAM, the following sequence can be used for Two-Plane program operation. Plane0 Plane1 (1) : Two-Plane Read for Copy Back Source page (2) : Random Data Out On Plane 0 (Up to 4224Byte) Source page (3) : Random Data In On Plane 0 (Up to 4224Byte) (4) : Random Data Out On Plane 1 (Up to 4224Byte) Target page (1) Target page (6) (1) 4KByte (5) : Random Data In On Plane 1 (Up to 4224Byte) (6): Two-Plane Program for Copy Back (6) 4KByte Data Field Spare Field (2) (3) Data Field (4) Spare Field (5) Figure A-4. 2-Plane Copy-Back Program Operation with Ramdon Data Input tR R/B I/OX 60h Add(3 Cycle) 60h Row Add.1,2,3 A13 ~ A19 : Fixed 'Low' : Fixed 'Low' A20 A21 ~ A31 : Fixed 'Low' A32 : Valid R/B I/Ox Add(5 Cycle) 85h DIN Add(3 Cycle) 00h Add(5 Cycle) 85h Add(2 Cycle) DIN 11h Col. Add.1,2 00h Add(5 Cycle) Add(5 Cycle) DIN Col. Add.1,2 & Row Add.1,2,3 2 Add(2 Cycle) 85h Add(2 Cycle) Add(2 Cycle) Col. Add.1,2 A0 ~ A12 : Valid A0 ~ A12 : Fixed 'Low' A13 ~ A19 : Fixed 'Low' : Fixed 'High' A20 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 tPROG 81h 05h Col. Add. 1,2 & Row Add.1,2,3 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed 'Low' A20 : Fixed 'Low' A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 R/B I/Ox 05h Row Add.1,2,3 Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2 A13 ~ A19 : Valid A0 ~ A12 : Valid A0 ~ A12 : Fixed 'Low' : Fixed 'High' A20 A13 ~ A19 : Fixed 'Low' A21 ~ A31 : Valid : Fixed 'Low' A20 A32 : Must be same as previous A32 A21 ~ A31 : Fixed 'Low' A32 : Must be same as previous A32 tDBSY Col. Add.1,2 & Row Add.1,2,3 1 35h DIN 10h 70h/F1h Col. Add.1,2 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Valid A20 : Fixed 'High' A21 ~ A31 : Valid A32 : Must be same as previous A32 Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 63 E0h DOUT Up to 4224Byte 1 E0h DOUT Up to 4224Byte 2 K9MDG08U5M K9LBG08U0M K9HCG08U1M FLASH MEMORY WP AC TIMING GUIDE Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Figure B-1. Program Operation 1. Enable Mode WE I/O 80h 10h WP R/B tww(min.100ns) 2. Disable Mode WE I/O 80h 10h WP R/B tww(min.100ns) Figure B-2. Erase Operation 1. Enable Mode WE I/O 60h D0h WP R/B tww(min.100ns) 2. Disable Mode WE I/O 60h D0h WP R/B tww(min.100ns) 64