FLASH MEMORY
1
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
K9XXG08UXM
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
FLASH MEMORY
2
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Document Title
2G x 8 Bit/ 4G x 8 Bit/ 8G x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Remark
Advance
Advance
Preliminary
Preliminary
Preliminary
Preliminary
Final
History
1. Initial issue
1. Add read status 2 command F1h
2. Add 2-plane read operation
3. Add address map (Table2)
4. Remove adjacent page relationship table
5. Modify figure of 2-plane copy-back program with random data input
6. Modify figure of Rp vs tr ,tf & Rp vs ibusy
7. Data retention 5years -> 10 years
8. Remove K9LBG08U1M
9. Modify figure of 2-plane page program
10. Add nWP timing guide
11. Add 2-plane read for copy-back operation
12. Add 2-plane random data out operation
13. Modify command table and note
14. Modify invalid block definition
15. Add program operation with 2KB data loading timing guide
16. tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
-> tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
1. Add WELP package
2. Chip address is added
3. Chip2 status is added
4. Interleave operation is added
5. Address map is added
6. DSP characteristics are added
7. Endurance is changed (10K->5K)
1. Interleave read to page program timing is added
2. Interleave copy-back program timing is added
3. ID cycle is changed
1. WELP package dimension is changed
2. Endurance is changed (5K->TBD)
1. Standby current is corrected
2. Random data output for copy-back is added
3. Max. Icc is changed (30mA->35mA)
1. Interleave two plane copy-back program timing is added
2. LGA QDP is added
3. Max. leakage current is corrected (10µA -> 20µA)
4. tCSD is changed (10ns -> 0ns)
Draft Date
April 12th 2006
Sep. 21th 2006
Dec. 22h 2006
Jan. 4th 2007
Jan. 12th 2007
Feb. 12th 2007
May 18th 2008
FLASH MEMORY
3
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Document Title
2G x 8 Bit/ 4G x 8 Bit/ 8G x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Revision No
1.0
1.1
1.2
Remark
Final
Final
History
1. WELP-DSP dimension is changed
2. Max. bad block number is changed.
(K9LBG08U0M: max. 200ea -> max. 120ea)
1. 14x18 LGA ODP package is added.
1. LGA ODP part number is fixed.
Draft Date
Dec. 11th 2007
Mar. 10th 2008
Apr. 7th 2008
FLASH MEMORY
4
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
GENERAL DESCRIPTION
FEATURES
• Voltage Supply : 2.7 V ~ 3.6 V
• Organization
- Memory Cell Array : (2G + 64M) x 8bit
- Data Register : (4K + 128) x 8bit
• Automatic Program and Erase
- Page Program : (4K + 128)Byte
- Block Erase : (512K + 16K)Byte
• Page Read Operation
- Page Size : (4K + 128)Byte
- Random Read : 60µs(Max.)
- Serial Access : 25ns(Min.)
*K9XDG08U5M: 50ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
- Program time : 800µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
4G / 8G / 16G x 8 Bit NAND Flash Memory
• Reliable CMOS Floating-Gate Technology
- Endurance : TBD(with 4bit/512byte ECC)
- Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
- K9LBG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9HCG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9HCG08U1M-ICB0/IIB0
52 - Pin TLGA (12 x 17 / 1.0 mm pitch)
- K9MDG08U5M-PCB0/PIB0 : Two K9HCG08U1M package stacked
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE
- K9MDG08U5M-ZCB0/ZIB0 : Two K9HCG08U1M package stacked
48 - Pin WELP (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE
- K9PDG08U5M-LCB0/LIB0 : Pb/Halogen-FREE PACKAGE
52 - Pin LLGA (14 x 18 / 1.00 mm pitch)
Offered in 4Gx8bit, the K9LBG08U0M is a 32G-bit NAND Flash Memory with spare 1G-bit. Its NAND cell provides the most cost-
effective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 4,224-byte
page and an erase operation can be performed in typical 1.5ms on a (512K+16K)byte block. Data in the data register can be read out
at 25ns (K9XDG08U5M: 50ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as com-
mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and
internal verification and margining of data. The K9LBG08U0M is an optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization PKG Type
K9LBG08U0M-P
2.7V ~ 3.6V X8
TSOPI
K9HCG08U1M-P
K9HCG08U1M-I 52TLGA
K9MDG08U5M-P TSOP1-DSP
K9MDG08U5M-Z WELP-DSP
K9PDG08U5M-L 52LLGA(14x18)
FLASH MEMORY
5
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
PIN CONFIGURATION (TSOP1)
K9LBG08U0M-PCB0/PIB0
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.16 +0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40 MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
()
0.039±0.002
1.00±0.05
0.002
0.05 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8°
0.010
0.25 TYP
0.125 +0.075
0.035
0.005+0.003
-0.001
0.50
0.020
()
0.20 +0.07
-0.03
FLASH MEMORY
6
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
PIN CONFIGURATION (TSOP1)
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.16 +0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40 MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
()
0.039±0.002
1.00±0.05
0.002
0.02 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8°
0.010
0.25 TYP
0.125 +0.075
0.035
0.005+0.003
-0.001
0.50
0.020
()
0.20 +0.07
-0.03
K9HCG08U1M-PCB0/PIB0
FLASH MEMORY
7
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
1.00
1.00
1.00
1.00
2.00
7 6 5 4 3 2 1
1.00
1.00
1.00
12.00±0.10
#A1
17.00±0.10
17.00±0.10
B
A
12.00±0.10
(Datum B)
(Datum A)
12.00
10.00
2.50
2.50
2.00
0.50 1.30
A
B
C
D
E
F
G
H
J
K
L
M
N
12-
∅
1.00
±
0.05
41-
∅
0.70
±
0.05
Side View
1.0
(
Max
.)
0.10 C
17.00
±
0.10
Top View Bottom View
AB CDEFGHJKLMN
7
6
5
4
3
2
1
K9HCG08U1M - ICB0 / IIB0
52-TLGA (measured in millimeters)
NC NC NC NC
NC
NC
NC NC NC
NC
NC
NC
NC
NC
NC
NC
Vcc
Vcc
Vss
Vss
Vss
/RE1
/RE2
/CE1 /CE2
CLE1 CLE2
ALE1
ALE2
/WE1
/WE2
/WP1
/WP2
R/B1
R/B2
Vss
IO0-1
IO0-2
IO1-1
IO1-2
IO2-1
IO3-1
IO2-2
IO3-2
IO4-1 IO4-2
IO5-1
IO5-2
IO6-1
IO6-2
IO7-1
IO7-2
∅
ABCM
0.1
∅
ABCM
0.1
PACKAGE DIMENSIONS
PIN CONFIGURATION (TLGA)
FLASH MEMORY
8
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
18.80 MAX REF
12.40 MAX REF
0.13~0.23
Pin #1
#1
#24
#48
0.50 TYP
#25
(0.10) A
(0.249) BASIC
GAGE PLANE
0.399~0.600
20.00±0.20
0.02 MIN
2.35 MAX
TYP BOTH SIDES
BOTTOM TSOP ONLY
(0.10) A
-A-
SEATING
PIN CONFIGURATION (TSOP1-DSP)
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF Unit :mm/Inch
PLANE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Dual Stacked Package
12mm x 20mm
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
R/B4
R/B3
CE3
CE4
K9MDG08U5M-PCB0/PIB0
FLASH MEMORY
9
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
PIN CONFIGURATION (WELP-DSP)
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE STACK TYPE
48 - WELP 1220 Unit :mm/Inch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin WELP
Dual Stacked Package
12mm x 20mm
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
R/B4
R/B3
CE3
CE4
K9MDG08U5M-ZCB0/ZIB0
∅
1.00 -DP 0.05MAX
1.50
1.50
A
19.30±0.10
0.08 C
#48
#25
C
1.47 MAX
12.00
±
0.10
0.20 +0.10
-0.02
0.50BSC
[0.5
±
0.06]
0.16 +0.10
-0.02
#1
#24
B
#1
- A -
1.00+0.05
TOP PACKAGE DETAIL
20.00±0.10
20.40±0.10
20.25±0.10
BTM PACKAGE DETAIL
NOTE: The PAD form of the bottom view can be different by the device
FLASH MEMORY
10
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
AB CDEFGHJKLMN
7
6
5
4
3
2
1
NC NC NC NC
NC NC NC
NC
NC
Vcc
Vcc
/CE1-2
R/B1-2
Vcc
Vcc
Vss
Vss
Vss
/RE1
/RE2
/CE1-1 /CE2-1
CLE1 CLE2
ALE1
ALE2
/WE1
/WE2
WP1
/WP2R/B1-1
R/B2-1
Vss
IO0-1
IO0-2
IO1-1
IO1-2
IO2-1
IO3-1
IO2-2
IO3-2
IO4-1 IO4-2
IO5-1
IO5-2
IO6-1
IO6-2
IO7-1
IO7-2
Vss
R/B2-2
/CE2-2
K9PDG08U5M-LCB0/LIB0
1.00
1.00
1.00
1.00
2.00
7 6 5 4 3 2 1
1.00
1.00
1.00
14.00±0.10
#A1
18.00±0.10
18.00±0.10
B
A
14.00±0.10
(Datum B)
(Datum A)
12.00
10.00
2.50
2.50
2.00
0.50 1.30
A
B
C
D
E
F
G
H
J
K
L
M
N
12-
∅
1.00
±
0.05
41-
∅
0.70
±
0.05
Side View
0.10 C
18.00
±
0.10
Top View Bottom View
52-LLGA (measured in millimeters)
∅
ABCM
0.1
∅
ABCM
0.1
PACKAGE DIMENSIONS
1.47
(
Max
.)
FLASH MEMORY
11
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
PIN DESCRIPTION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
There are two CE pins (CE1 & CE2) in the K9HCG08U1M, and four CE pins (CE1 & CE2 & CE3 & CE4) in the K9XDG08U5M.
There are two R/B pins (R/B1 & R/B2) in the K9HCG08U1M, and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9XDG08U5M.
Pin Name Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE / CE1
CHIP ENABLE
The CE / CE 1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation.
Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation
CE2 CHIP ENABLE
The CE2 input enables the second K9LBG08U0M
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.
R/B / R/B1
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B2READY/BUSY OUTPUT
The R/B2 input enables the second K9LBG08U0M
Vcc POWER
VCC is the power supply for device.
Vss GROUND
N.C NO CONNECTION
Lead is not internally connected.
FLASH MEMORY
12
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
4K Bytes 128 Bytes
Figure 1. K9LBG08U0M Functional Block Diagram
Figure 2. K9LBG08U0M Array Organization
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A0A1A2A3A4A5A6A7
2nd Cycle A8A9A10 A11 A12 *L *L *L
3rd Cycle A13 A14 A15 A16 A17 A18 A19 A20
4th Cycle A21 A22 A23 A24 A25 A26 A27 A28
5th Cycle A29 A30 A31 A32 *L *L *L *L
VCC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A13 - A32
A0 - A12
Command
CE
RE
WE
CLE WP
I/0 0
I/0 7
VCC
VSS
1,024K Pages
(=8,192 Blocks)
4K Bytes
8 bit
128 Bytes
1 Block = 128 Pages
(512K + 16K) Bytes
I/O 0 ~ I/O 7
1 Page = (4K + 128)Bytes
1 Block = (4K + 128)B x 128 Pages
= (512K + 16K) Bytes
1 Device = (4K+128)B x 128Pages x 8,192 Blocks
= 33,792 Mbits
Row Address
Page Register
ALE
NAND Flash
ARRAY
Y-Gating
Row Address
Column Address
Column Address
Data Register & S/A
Row Address
32,768M + 1,024M Bit
(4,096 + 128)Byte x 1,048,576
FLASH MEMORY
13
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Product Introduction
The K9LBG08U0M is a 33,792Mbit(35,433,480,192 bit) memory organized as 1,048,576 rows(pages) by 4,224x8 columns. Spare
128 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for
accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The mem-
ory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page.
A block consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND
cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a
block basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation
is prohibited on the K9LBG08U0M.
The K9LBG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space
requires 33 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-
mand register. Table 1 defines the specific commands of the K9LBG08U0M.
Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h//F2h and FFh.
3. Two-Plane Random Data msut be used after Two-Plane Read operation
4. Interleave-operation between two chips is allowed.
It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function 1st Set 2nd Set Acceptable Command during Busy
Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h -
Reset FFh - O
Page Program 80h 10h
Copy-Back Program 85h 10h
Block Erase 60h D0h
Random Data Input(1) 85h -
Random Data Output(1) 05h E0h
Read Status 70h O
Chip1 Status F1h O
Chip2 Status F2h O
Two-Plane Read (3) 60h----60h 30h
Two-Plane Read for Copy-Back 60h----60h 35h
Two-Plane Random Data Output (1) (3) 00h----05h E0h
Two-Plane Page Program(2) 80h----11h 81h----10h
Two-Plane Copy-Back Program(2) 85h----11h 81h----10h
Two-Plane Block Erase 60h----60h D0h
Page Program with 2KB Data (2) 80h----11h 80h----10h
Copy-Back Program with 2KB Data (2) 85h----11h 85h----10h
FLASH MEMORY
14
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
K9LBG08U0M is arranged in four 8Gb memory planes. Each plane contains 2,048 blocks and 4224 byte page registers. This allows it
to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that two-plane program/erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3
separately.
For example, two-plane program/erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program/erase oper-
ation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed
Memory Map
Plane 0 Plane 1 Plane 2 Plane 3
(2048 Block) (2048 Block) (2048 Block) (2048 Block)
Page 0
Page 1
Page 127
Page 126
Block 0
Page 0
Page 1
Block 1
Page 0
Page 1
Block 4096
Page 0
Page 1
Block 4097
Page 0
Page 1
Block 4094
Page 0
Page 1
Block 4095
Page 0
Page 1
Block 8190
Page 0
Page 1
Block 8191
4224byte Page Registers 4224byte Page Registers 4224byte Page Registers 4224byte Page Registers
Page 0
Page 1
Block 2
Page 0
Page 1
Block 3
Page 0
Page 1
Block 4098
Page 0
Page 1
Block 4099
Page 0
Page 1
Block 4092
Page 0
Page 1
Block 4093
Page 0
Page 1
Block 8188
Page 0
Page 1
Block 8189
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
Page 127
Page 126
FLASH MEMORY
15
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
NOTE :
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less.
2. Typical value are measured at Vcc=3.3V, TA=25°C. Not 100% tested.
3. The typical value of the K9HCG08U1M’s ISB2 is 40µA and the maximum value is 200µA.
4. The typical value of the K9XDG08U5M’s ISB2 is 80µA and the maximum value is 400µA.
5. The maximum value of K9HCG08U1M-P’s ILI and ILO is ±40µA and the maximum value of K9HCG08U1M-I/L’s ILI and ILO is ±20µA.
6. The maximum value of K9PDG08U5M-L’s ILI and ILO is ±40µA and K9MDG08U5M-P/Z’s ILI and ILO is ±80µA.
Parameter Symbol Test Conditions Min Typ Max Unit
Operating
Current
Page Read with Serial Access ICC1tRC=25ns, CE=VIL, IOUT=0mA
(K9XDG08U5M: tRC=50ns) -1535
mA
Program ICC2- -1535
Erase ICC3- -1535
Stand-by Current(TTL) ISB1CE=VIH, WP=0V/VCC --1
Stand-by Current(CMOS) ISB2CE=VCC-0.2, WP=0V/VCC - 20 100
µA
Input Leakage Current ILI VIN=0 to Vcc(max) - - ±20
Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±20
Input High Voltage VIH(1) - 0.8 x Vcc - VCC+0.3
V
Input Low Voltage, All inputs VIL(1) - -0.3 - 0.2 x Vcc
Output High Voltage Level VOH IOH=-400µA2.4--
Output Low Voltage Level VOL IOL=2.1mA - - 0.4
Output Low Current(R/B)IOL(R/B)VOL=0.4V 8 10 - mA
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08UXM-XCB0 :TA=0 to 70°C, K9XXG08UXM-XIB0:TA=-40 to 85°C)
Parameter Symbol K9LBG08U0M Unit
Min Typ. Max
Supply Voltage VCC 2.7 3.3 3.6 V
Supply Voltage VSS 000V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on any pin relative to VSS
VCC -0.6 to + 4.6
V
VIN -0.6 to + 4.6
VI/O -0.6 to Vcc+0.3 (<4.6V)
Temperature Under Bias K9XXG08UXM-XCB0 TBIAS
-10 to +125 °C
K9XXG08UXM-XIB0 -40 to +125
Storage Temperature K9XXG08UXM-XCB0 TSTG -65 to +150 °C
K9XXG08UXM-XIB0
Short Circuit Current Ios 5 mA
FLASH MEMORY
16
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
NOTE : 1. Capacitance is periodically sampled and not 100% tested.
2. K9HCG08U1M-IXB0’s capacitance(I/O, Input) is 13pF and K9PDG08U5M-LXB0’s capacitance(I/O, Input) is 23pF.
Item Symbol Test
Condition Min Max Unit
K9LBG08U0M K9HCG08U1M K9MDG08U5M
Input/Output Capacitance CI/O VIL=0V - 10 20 40 pF
Input Capacitance CIN VIN=0V - 10 20 40 pF
VALID BLOCK
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status fail-
ure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate
management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9LBG08U0M chip in the K9HCG08U1M, K9XDG08U5M has Maximum 120 invalid blocks.
Parameter Symbol Min Typ. Max Unit
K9LBG08U0M NVB 8,072 - 8,192 Blocks
K9HCG08U1M NVB 16,144 - 16,384 Blocks
K9XDG08U5M NVB 32,288 - 32,768 Blocks
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE ALE CE WE RE WP Mode
HLL HX
Read Mode Command Input
L H L H X Address Input(5clock)
HLL HH
Write Mode Command Input
L H L H H Address Input(5clock)
L L L H H Data Input
L L L H X Data Output
XXXXHX During Read(Busy)
XXXXXH During Program(Busy)
XXXXXH During Erase(Busy)
XX(1) X X X L Write Protect
XXHXX
0V/VCC(2) Stand-by
AC TEST CONDITION
(K9XXG08UXM-XCB0: TA=0 to 70°C, K9XXG08UXM-XIB0:TA=-40 to 85°C,K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted)
Parameter K9XXG08UXM
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc/2
Output Load (Vcc:3.0V +/-10%) 1 TTL GATE and CL=50pF(K9LBG08U0M-P, K9HCG08U1M-I)
1 TTL GATE and CL=30pF (K9HCG08U1M-P/Z, K9XDG08U5M-P/Z/L)
FLASH MEMORY
17
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Program / Erase Characteristics
NOTE
1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical Program time is defined as the time within which more than 50% of the whole pages are programed at 3.3V Vcc and 25°C temperature.
3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the
page group A and B(Table 5).
Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123
Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127
Parameter Symbol Min Typ Max Unit
Program Time tPROG -0.83 ms
Dummy Busy Time for Multi Plane Program tDBSY 0.5 1 µs
Number of Partial Program Cycles in the Same Page Nop - - 1 cycle
Block Erase Time tBERS -1.510ms
AC Timing Characteristics for Command / Address / Data Input
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Parameter Symbol
Min Max
UnitK9LBG08U0M K9XDG08U5M K9LBG08U0M K9XDG08U5M
K9HCG08U1M K9HCG08U1M
CLE Setup Time tCLS(1) 12 25 - - ns
CLE Hold Time tCLH 510- -ns
CE Setup Time tCS(1) 20 35 - - ns
CE Hold Time tCH 510- -ns
WE Pulse Width tWP 12 25 - - ns
ALE Setup Time tALS(1) 12 25 - - ns
ALE Hold Time tALH 510 - -
ns
Data Setup Time tDS(1) 12 20 - - ns
Data Hold Time tDH 510 - -ns
Write Cycle Time tWC 25 45 - - ns
WE High Hold Time tWH 10 15 - - ns
Address to Data Loading Time tADL(2) 100(2) 100 ns
FLASH MEMORY
18
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
AC Characteristics for Operation
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.
Parameter Symbol
Min Max
Unit
K9LBG08U0M K9XDG08U5M K9LBG08U0M K9XDG08U5M
K9HCG08U1M K9HCG08U1M
Data Transfer from Cell to Register tR-6060µs
ALE to RE Delay tAR 10 10 - ns
CLE to RE Delay tCLR 10 10 - ns
Ready to RE Low tRR 20 20 - ns
RE Pulse Width tRP 12 25 - ns
WE High to Busy tWB - - 100 100 ns
Read Cycle Time tRC 25 50 - - ns
RE Access Time tREA - - 20 30 ns
CE Access Time tCEA - - 25 45 ns
RE High to Output Hi-Z tRHZ - - 100 100 ns
CE High to Output Hi-Z tCHZ - - 30 30 ns
CE High to ALE or CLE Don’t Care tCSD 00 - -ns
RE High to Output Hold tRHOH 15 15 - - ns
RE Low to Output Hold tRLOH 5---ns
CE High to Output Hold tCOH 15 15 - - ns
RE High Hold Time tREH 10 15 - - ns
Output Hi-Z to RE Low tIR 00- -ns
RE High to WE Low tRHW 100 100 - - ns
WE High to RE Low tWHR 60 60 - - ns
Device Resetting Time(Read/Program/Erase) tRST --
5/10/500(1) 5/10/500(1) µs
FLASH MEMORY
19
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
NAND Flash Technical Notes
Identifying Initial Invalid Block(s)
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-
sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block at the time of shipment.
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid
block has non-FFh data at the column address of 4,096.The initial invalid block information is also erasable in most cases, and it is
impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid
block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
*Check "FFh" at the column address
Figure 3. Flow chart to create initial invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update) No
Initial
4,096 of the last page in the block
Invalid Block(s) Table
FLASH MEMORY
20
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data. Block replacement should be done upon erase or program error.
Failure Mode Detection and Countermeasure sequence
Write Erase Failure Status Read after Erase --> Block Replacement
Program Failure Status Read after Program --> Block Replacement
Read Up to Four Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> RS Code etc.
Example) 4bit correction / 512-byte
: If program operation results in an error, map out
the block including the page in error and copy the
*
target data to another block.
FLASH MEMORY
21
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Write 30h
Block Replacement
Buffer memory of the controller.
1st
Block A
Block B
(n-1)th
nth
(page)
{
∼
1st
(n-1)th
nth
(page)
{
∼
an error occurs.
1
2
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
FLASH MEMORY
22
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB doesn't need to be page 0.
From the LSB page to MSB page
DATA IN: Data (1) Data (128)
(1)
(2)
(3)
(32)
(128)
Data register
Page 0
Page 1
Page 2
Page 31
Page 127
Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (128)
(2)
(32)
(3)
(1)
(128)
Data register
Page 0
Page 1
Page 2
Page 31
Page 127
NAND Flash Technical Notes (Continued)
Addressing for program operation
:
:
:
:
Interleave Page Program
K9LBG08U0M is composed of two K9GAG08U0Ms. K9LBG08U0M provides interleaving operation between two K9GAG08U0Ms.
This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.
At first, the host issues page program command to one of the K9GAG08U0M chips, say K9GAG08U0M(chip #1). Due to this
K9LBG08U0M goes into busy state. During this time, K9GAG08U0M(chip #2) is in ready state. So it can execute the page program
command issued by the host.
After the execution of page program by K9GAG08U0M(chip #1), it can execute another page program regardless of the
K9GAG08U0M(chip #2). Before that the host needs to check the status of K9GAG08U0M(chip #1) by issuing F1h command. Only
when the status of K9GAG08U0M(chip #1) becomes ready status, host can issue another page program command. If the
K9GAG08U0M(chip #1) is in busy state, the host has to wait for the K9GAG08U0M(chip #1) to get into ready state.
Similarly, K9GAG08U0M(chip #2) can execute another page program after the completion of the previous program. The host can
monitor the status of K9GAG08U0M(chip #2) by issuing F2h command. When the K9GAG08U0M(chip #2) shows ready state, host
can issue another page program command to K9GAG08U0M(chip #2).
This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip
individually. This reduces the time lag for the completion of operation.
NOTES : During interleave operations, 70h command is prohibited.
FLASH MEMORY
23
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1) busy of Chip #1
I/OX
80h 10h Command
A32
: Low
Add & Data 80h 10h
A32
: High
Add & Data
busy of Chip #2
internal only
internal only
R/B
Interleave Page Program
≈≈≈
F1h or F2h
AB
C
D
another page program on Chip #1
State A : Chip #1 is executing a page program operation and chip #2 is in ready state. So the host can issue a page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is terminated, but page program on chip #2 is still operating. And the system should issue F1h command to detect the status of chip
#1. If chip #1 is ready, status I/O6 is "1" and the system can issue another page program command to chip #1.
State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate page program on chip #1 and chip #2 alternately.
Status Operation Status Command / Data
F1h F2h
A Chip 1 : Busy, Chip 2 : Ready 8xh Cxh
B Chip 1 : Busy, Chip 2 : Busy 8xh 8xh
C Chip 1 : Ready, Chip 2 : Busy Cxh 8xh
D Chip 1 : Ready, Chip 2 : Ready Cxh Cxh
R/B (#2)
FLASH MEMORY
24
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1) busy of Chip #1
I/OX
60h D0h Command
A32
: Low
Add 60h D0h
A32
: High
Add
busy of Chip #2
internal only
R/B (#2)
internal only
Interleave Block Erase
≈≈≈
F1h or F2h
AB
C
D
another Block Erase on Chip #1
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2.
State B : Both chip #1 and chip #2 are executing block erase operation.
State C : Block erase on chip #1 is terminated, but block erase on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If
chip #1 is ready, status I/O6 is "1" and the system can issue another block erase command to chip #1.
State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate block erase on chip #1 and chip #2 alternately.
Status Operation Status Command / Data
F1h F2h
A Chip 1 : Busy, Chip 2 : Ready 8xh Cxh
B Chip 1 : Busy, Chip 2 : Busy 8xh 8xh
C Chip 1 : Ready, Chip 2 : Busy Cxh 8xh
D Chip 1 : Ready, Chip 2 : Ready Cxh Cxh
R/B
FLASH MEMORY
25
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1) t DBSY
I/OX
Command
t PROG of Chip #1
internal only
R/B (#2)
internal only
R/B
81h 10h
A32
:Low
Add & Data
80h 11h
A32
: Low
Add & Data
F1h or F2h*
81h 10h
A32
:High
Add & Data
80h 11h
A
32
: High
Add & Data
t DBSY tPROG of Chip #2
≈
R/B (#1)
I/OX
internal only
R/B (#2)
internal only
R/B
tPROG of Chip #2
1
1
Interleave Two-Plane Page Program
≈≈ ≈
≈≈
State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1.
F2h command is required to check the status of chip #2 to issue the next page program command to chip #2.
According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately.
AB
CD
FLASH MEMORY
26
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1)
I/OX
Command
t BERS of Chip #1
internal only
R/B (#2)
internal only
R/B
60h D0h
A32
:Low
Add
60h
A32
: Low
Add
F1h or F2h*
60h D0h
A32
:High
Add
60h
A32
: High
Add
t BERS of Chip #2
tBERS of Chip #2
1
1
Interleave Two-Plane Block Erase
R/B (#1)
I/OX
internal only
R/B (#2)
internal only
R/B
≈ ≈≈
AB
C
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2.
State B : Both chip #1 and chip #2 are executing block erase operation.
State C : Block erase on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing block erase operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next block erase command to chip #1.
F2h command is required to check the status of chip #2 to issue the next block erase command to chip #2.
According to the above process, the system can operate two-plane block erase on chip #1 and chip #2 alternately.
D
FLASH MEMORY
27
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1)
I/OX
Command
internal only
R/B (#2)
internal only
R/B
F1h or F2h*
1
1
Interleave Read to Page Program Operation
R/B (#1)
I/OX
internal only
R/B (#2)
internal only
R/B
AB
C
State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a read command to chip #2.
State B : Both chip #1 is executing page program operation and chip #2 is executing read operation.
State C : Read operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing page program operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next command to chip #1.
F2h command is required to check the status of chip #2 to issue the next command to chip #2.
As the above process, the system can operate Interleave read to page porgram on chip #1 and chip #2 alternatively.
D
10h
80h
A32
: Low
Add Data in
tPROG of chip #1
30h
00h
A32
: High
Add Data out
tR of chip #2
tPROG of chip #1
FLASH MEMORY
28
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1)
I/OX
internal only
R/B (#2)
internal only
R/B
1
Interleave Copy-Back Program Operation
AB
State A : Chip #1 is executing a copy-back program operation, and chip #2 is in ready state. So the host can issue a read for copy-back command to chip #2.
State B : Both chip #1 is executing copy-back program operation and chip #2 is executing read for copy-back operation.
State C : Read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. Chip #1 is still executing copy-back program operation.
State D : Both chip #1 and chip #2 are ready.
State E : Chip #2 is executing a copy-back program operation, and chip #1 is in ready state. So the host can issue a read for copy-back command to chip #1.
State F : Both chip #2 is executing copy-back program operation and chip #1 is executing read for copy-back operation.
State C : Read for copy-back operation on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing copy-back program operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next command to chip #1.
F2h command is required to check the status of chip #2 to issue the next command to chip #2.
As the above process, the system can operate Interleave copy-back program on chip #1 and chip #2 alternatively.
10h
85h
A32
: Low
Add
tPROG of chip #1
35h
00h
A32
: High
Add
tR of chip #2
Command
F1h or F2h*
C
R/B (#1)
I/OX
internal only
R/B (#2)
internal only
R/B
1
DF
10h
85h
A32
: High
Add 35h
00h
A32
: Low
Add
Command
F1h or F2h*
G
tPROG of chip #2
tR of chip #1
E H
FLASH MEMORY
29
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1)
I/OX
tR
internal only
R/B (#2)
internal only
R/B
60h
A32
: Low
Add
1
1
Interleave Two-Plane Copy Back Program
R/B (#1)
I/OX
internal
R/B (#2)
internal
R/B
A
A20
: Low
A32
: Low
A20
: High
A32
: Low
A20
: Low
A32
: Low
A20
: High
tPROG of Chip #1
only
only
A32
: Low
A20
: Low
A32
: Low
A20
: High
60h
Add
35h 00h
Add
05h
Add
E0h
Data Out
00h
Add
05h
Add
E0h
Data Out
85h
Add
11h
tDBSY
81h
Add
10h 60h
A32
: High
Add
A20
: Low
A
32
: High
A20
: High
60h
Add
35h
A32
: High
A20
: Low
00h
Add
05h
Add
E0h
Data Out
2
tR
FLASH MEMORY
30
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B (#1)
I/OX
Command
internal
R/B (#2)
internal
R/B
F1h or F2h*
3
2
Interleave Two-Plane Copy Back Program
R/B (#1)
I/OX
internal
R/B (#2)
internal
R/B
B
C
State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2.
State B : Both chip #1 and chip #2 are executing page program operation.
State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation.
State D : Both chip #1 and chip #2 are ready.
Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1.
F2h command is required to check the status of chip #2 to issue the next page program command to chip #2.
According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately.
tPROG of Chip #2
only
only
A32
: High
A20
: High
00h
Add
05h
Add
E0h
Data Out
A32
: High
A20
: Low
A32
: Hgih
A20
: High
85h
Add
11h 81h
Add
10h
only
only
tPROG of Chip #1
tPROG of Chip #2
≈
≈
3D
tDBSY
FLASH MEMORY
31
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CE
WE
tWP
tCH
tCS
Address(5Cycles)
80h Data Input
CE
CLE
ALE
WE
Data Input
CE don’t-care
10h
tCEA
out
tREA
CE
RE
I/O0~7
Figure 5. Read Operation with CE don’t-care.
I/Ox
≈
≈
Address(5Cycle)00h
CE
CLE
ALE
WE
Data Output(serial access)
CE don’t-care
R/B tR
RE
30h
I/Ox
≈
≈≈≈
≈
FLASH MEMORY
32
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Command Latch Cycle
CE
WE
CLE
ALE
Command
Address Latch Cycle
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
NOTE
Device I/O DATA ADDRESS
I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
K9LBG08U0M I/O 0 ~ I/O 7 ~4,224byte A0~A7 A8~A12 A13~A20 A21~A28 A29~A32
I/Ox
CE
WE
CLE
ALE
Col. Add1
t
CLS
tCS tWC
tWP
tALS
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH
tDS tDH
tWP
I/Ox
Col. Add2 Row Add1 Row Add2
tWC
tWH
tALH tALS
tDS tDH
Row Add3
tALH
FLASH MEMORY
33
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Input Data Latch Cycle
CE
CLE
WE
DIN 0 DIN 1 DIN final
ALE tALS
tCLH
tWC
tCH
tDS tDH tDS tDH tDS tDH
tWP
tWH
tWP tWP
≈
≈
≈
I/Ox
≈
≈
≈
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
RE
CE
R/B
Dout Dout Dout
tRC
tREA
tRR
tRHOH(2)
tREA
tREH
tREA tCOH
tRHZ(1)
≈≈≈≈
I/Ox
tCHZ(1)
tRHZ(1)
NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRHOH starts to be valid when frequency is lower than 33MHz.
FLASH MEMORY
34
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Status Read Cycle
CE
WE
CLE
RE
70h/F1h Status Output
tCLR
tCLH
tWP
tCH
tDS tDH tREA
tIR tRHOH
tCOH
tWHR
tCEA
tCLS
I/Ox
tCHZ
tRHZ
tCS
RE
CE
R/B
I/Ox
≈
tRR
tCEA
tREA
tRP tREH
tRC
≈
tRHZ(1)
tCHZ(1)
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
tRHOH(2)
tCOH
tRLOH(2)
≈
≈
Dout Dout
tREA
≈
NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
FLASH MEMORY
35
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Read Operation(Intercepted by CE)
CE
CLE
R/B
WE
ALE
RE
Busy
00h
Dout N Dout N+1 Dout N+2
Row Address
Column Address
tWB
tAR
tCHZ
tR
tRR
tRC
30h
Read Operation
CE
CLE
R/B
WE
ALE
RE
Busy
00h
Col. Add1 Col. Add2 Row Add1
Dout N Dout N+1
Column Address Row Address
tWB
tAR
tRtRC tRHZ
tRR
Dout M
tWC
≈≈ ≈
Row Add2
30h
tCLR
I/Ox
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2
Row Add3
Row Add3
tCLR
tCSD
tCSD
tCOH
FLASH MEMORY
36
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Random Data Output In a Page
CE
CLE
R/B
WE
ALE
RE
Busy
00h Dout N Dout N+1
Row Address
Column Address
tWB
tAR
tR
tRR
t
RC
30h/35h 05h
Column Address
Dout M Dout M+1
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Col Add1 Col Add2
Row Add3
tCLR
E0h
tWHR
tREA
tRHW
FLASH MEMORY
37
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Page Program Operation
CE
CLE
R/B
WE
ALE
RE
80h 70h I/O
0
Din
N
Din 10h
M
SerialData
Input Command Column Address Row Address 1 up to m Byte
Serial Input
Program
Command
Read Status
Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
tPROG
tWB
tWC tWC tWC
≈≈
≈
≈
I/Ox Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
tADL tWHR
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
38
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Page Program Operation with Random Data Input
CE
CLE
R/B
WE
ALE
RE
80h 70h I/O
0
Din
N
Din 10h
M
Serial Data
Input Command Column Address Row Address Serial Input Program
Command
Read Status
Command
tPROG
tWB
tWC tWC
≈≈
≈
≈
85h
Random Data
Input Command Column Address
tWC
Din
J
Din
K
Serial Input
≈
≈
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Col. Add1 Col. Add2
Row Add3
≈
tADL
tADL tWHR
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
39
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
00h I/O
x
85h
Column Address Row Address
Read Status Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
tPROG
tWB
tWC
≈
Busy
tWB
tR
Busy
≈
10h
Copy-Back Data
Input Command
35h
Column Address Row Address
Data 1 Data N
≈ ≈
Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Row Add3
70h
NOTES :
1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
tADL
tWHR
Data 1 Data N
≈ ≈
tRC
Copy-Back Program Operation with Random Data Input
CE
CLE
R/B
WE
ALE
RE
I/Ox
FLASH MEMORY
40
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Block Erase Operation
CE
CLE
R/B
WE
ALE
RE
60h
Erase Command
Read Status
Command
I/O
0
=1 Error in Erase
D0h 70h I/O 0
Busy
tWB tBERS
I/O
0
=0 Successful Erase
Row Address
tWC
≈
Auto Block Erase
Setup Command
I/Ox
Row Add1 Row Add2 Row Add3
tWHR
FLASH MEMORY
41
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
00h
Column Address
tW
Row Address
A13~A20 A21~A28 A29~A32
A8~A12
A0~A7
tWC
Column Address
A8~A12
A0~A7
05h
Dout
N 00h
Column Address
tW
Row Address
A13~A20 A21~A28 A29~A32
A8~A12
A0~A7
tWC
Column Address
A8~A12
A0~A7
05h E0h
Dout
M
60h
tW
Row Address
A13~A20 A21~A28 A29~A32
tWC
60h
tW
Row Address
A13~A20 A21~A28 A29~A32
tWC
30h
1
1
CE
CLE
R/B
WE
ALE
RE
I/Ox
CE
CLE
R/B
WE
ALE
RE
I/Ox
Busy
tWB
tR
tREA
tWHR
tCLR
tWHR
tCLR
tREA
E0h
tRC
tRC
Dout
N+1
tRHW
Dout
M+1
Two-Plane Page Read Operation with Two-Plane Random Data Out
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31: Fixed ’Low’
A0 ~ A12 : Valid
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
A32 : Valid A32 : Must be same as previous A32
A32 : Must be same as previous A32 A32 : Must be same as previous A32
FLASH MEMORY
42
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
80h
I/O0~7
R/B
11h
Ex.) Two-Plane Page Program
tDBSY
Address & Data Input 81h 10h
Address & Data Input 70h
tPROG
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31: Fixed ’Low’
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
Note: Any command between 11h and 81h is prohibited except 70h/F1h/F2 and FFh.
Note
Two-Plane Page Program Operation
CE
CLE
R/B
WE
ALE
RE
80h Din
NDin 11h
M
Serial Data
Input Command
Column Address
Program
tDBSY
tWB
tWC
≈≈
≈
≈
Command
(Dummy)
Din
N10h
tPROG
tWB
≈≈
≈
I/O 0
Program Confirm
Command
(True)
81h 70h
Page Row Address
I/Ox
≈
A0~A7A8~A12 A13~A20 A21~A28A29~A32 A0~A7A8~A12 A13~A20 A21~A28A29~A32
1 up to 2112 Byte Data
Serial Input
Din
M
Read Status Command
t
DBSY :
typ. 500ns
max. 1
µ
s
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
A32 : Valid A32 : Must be same as previous A32
FLASH MEMORY
43
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
60h
Row Add1,2,3
I/O0~7
R/B
60h A9 ~ A25
D0h
tBERS
Ex.) Address Restriction for Two-Plane Block Erase Operation
D0h 70hAddress Address
Row Add1,2,3
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Valid
A32 : Valid A32 : Must be same as previous A32
Two-Plane Block Erase Operation
Block Erase Setup Command1 Erase Confirm Command
Read Status Command
CE
CLE
R/B
I/OX
WE
ALE
RE
60h Row Add1 D0h 70h I/O 0
Busy
tWB tBERS
tWC
I/O 0 = 0 Successful Erase
I/O 0 = 1 Error in Erase
Row Add2 Row Add3
60h Row Add1 D0h
Row Add2 Row Add3
Row Address
tWC
Block Erase Setup Command2
Row Address
tWHR
FLASH MEMORY
44
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Read ID Operation
CE
CLE
WE
ALE
RE
90h
Read ID Command Maker Code Device Code
00h ECh
tREA
Address. 1cycle
I/Ox
tAR
Device Device Code(2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9LBG08U0M D7h 55h B6h 78h
K9HCG08U1M Same as each K9LBG08U0M in it.
K9XDG08U5M
Device 4th cyc.
Code 3rd cyc. 5th cyc.
FLASH MEMORY
45
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
4th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Page Size
(w/o redundant area )
1KB
2KB
4KB
8KB
0 0
0 1
1 0
1 1
Block Size
(w/o redundant area )
64KB
128KB
256KB
512KB
0 0
0 1
1 0
1 1
Redundant Area Size
( byte/512byte)
8
16
0
1
Organization x8
x16
0
1
Serial Access Minimum
50ns/30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
3rd ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Internal Chip Number
1
2
4
8
0 0
0 1
1 0
1 1
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0 0
0 1
1 0
1 1
Number of
Simultaneously
Programmed Pages
1
2
4
8
0 0
0 1
1 0
1 1
Interleave Program
Between multiple chips
Not Support
Support
0
1
Cache Program Not Support
Support
0
1
ID Definition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, etc
Page Size, Block Size, Spare Size, Organization, Serial Access Minimum
Plane Number, Plane Size
FLASH MEMORY
46
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
5th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Plane Number
1
2
4
8
0 0
0 1
1 0
1 1
Plane Size
(w/o redundant Area)
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Reserved 0 0 0
FLASH MEMORY
47
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes of data
within the selected page are transferred to the data registers in less than 60µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 25ns(K9XDG08U5M : 50ns) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make
the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
Address(5Cycle)00h
Col Add1,2 & Row Add1,2,3
Data Output(Serial Access)
Data Field Spare Field
CE
CLE
ALE
R/B
WE
RE
tR
30h
I/Ox
FLASH MEMORY
48
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Figure 7. Random Data Output In a Page
Address
00h Data Output
R/B
RE
tR
30h/35h Address
05h E0h
5Cycles 2Cycles Data Output
Data Field Spare Field Data Field Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the
same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential
order in a block. A page program cycle consists of a serial data loading period in which up to 4,224bytes of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
80h
R/B
Address & Data Input I/O0Pass
Data
10h 70h
Fail
tPROG
I/Ox
I/Ox
Col Add1,2 & Row Add1,2,3
"0"
"1"
Col Add1,2 & Row Add1,2,3
FLASH MEMORY
49
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Figure 9. Random Data Input In a Page
80h
R/B
Address & Data Input I/O0Pass
10h 70h
Fail
tPROG
85h Address & Data Input
I/Ox
Col Add1,2 & Row Add1,2,3 Col Add1,2
Data Data
"0"
"1"
COPY-BACK PROGRAM
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-
loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to
the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with
the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,224-byte
data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,
the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command
(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once
the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system control-
ler can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When
the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register
remains in Read Status command mode until another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11.
"0"
"1"
Figure 10. Page Copy-Back Program Operation
00h
R/B
Add.(5Cycles) I/O0 Pass
Fail
tPROG
tR
Source Address
Destination Address
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2 & Row Add.1,2,3
35h Data Output 85h Add.(5Cycles) 10h 70h
≈
≈
Figure 11. Page Copy-Back Program Operation with Random Data Input
R/B
Source Address
Destination Address
There is no limitation for the number of repetition.
I/Ox
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
00h Add.(5Cycles) 35h
tR
Data Output
85h
Add.(5Cycles) Data
≈
≈
85h Add.(2Cycles) Data
10h
tPROG
70h
FLASH MEMORY
50
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Figure 13. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A20 to A32 is valid while A13 to A19 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
60h
Row Add. : A13 ~ A32
R/B
Address Input(3Cycle) I/O0Pass
D0h 70h
Fail
tBERS
I/Ox
"0"
"1"
TWO-PLANE PAGE READ
Two-Plane Page Read is an extension of Page Read, for a single plane with 4,224 byte page registers. Since the device is equipped
with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of two pages. Two-Plane Page
Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can
be selected from each plane.
After Read Confirm command(30h) the 8,448 bytes of data within the selected two page are transferred to the data registers in less
than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five
Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the
identical command sequences. The restrictions for Two-Plane Page Program are shown in Figure 14. Two-Plane Read must be
used in the block which has been programmed with Two-Plane Page Program.
Figure 14. Two-Plane Page Read Operation with Two-Plane Random Data Out
60h
I/OX
R/B
60h 30h
tR
Address (3 Cycle) Address (3 Cycle)
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 :Valid
1
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
1
Row Add.1,2,3 Row Add.1,2,3
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
2
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
2
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
A32 : Valid A32 : Must be same as previous A32
A32 : Must be same as previous A32
A32 : Must be same as previous A32
FLASH MEMORY
51
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
TWO-PLANE PAGE PROGRAM
Two-Plane Page Program is an extension of Page Program, for a single plane with 4,224 byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a simultaneous programming of two
pages.
After writing the first set of data up to 4,224 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B
remains in Busy state for a short period of time(tDBSY). Read Status command (70h/F1h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy
Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the
same as that of Page Program. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane
Page Program is shown in Figure15.
Figure 15. Two-Plane Page Program
80h 11h
Data
Input
Plane 0
(2048 Block)
Block 0
Block 2
Block 4094
Block 4092
80h
A0 ~ A12 : Valid
I/O0 ~ 7
R/B
Address & Data Input 11h 81h 10h
tDBSY tPROG
70h
Address & Data Input
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
NOTE : 1. It is noticeable that physically same row address is applied to two planes .
81h 10h
Plane 1
(2048 Block)
Block 1
Block 3
Block 4095
Block 4093
Note*2
2. Any command between 11h and 81h is prohibited except 70h/F1h/F2 and FFh.
A32 : Must be same as previous A32
A32 : Valid
FLASH MEMORY
52
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
TWO-PLANE BLOCK ERASE
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
Figure 16. Two-Plane Erase Operation
60h
I/OX
R/B
60h D0h I/O0 Pass
Fail
tBERS
Address (3 Cycle) Address (3 Cycle) 70h
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
"0"
"1"
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Valid
A32 : Valid A32 : Must be same as previous A32
FLASH MEMORY
53
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Figure 17. Two-Plane Copy-Back Program Operation
R/B
85h 70h
tPROG
Add.(5Cycles)
Destination Address
10h
I/Ox
Col. Add.1,2 & Row Add.1,2,3
81h Add.(5Cycles)
Destination Address
Col. Add.1,2 & Row Add.1,2,3
11h
tDBSY
TWO-PLANE COPY-BACK PROGRAM
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4224 byte page registers. Since the
device is equipped with two memory planes, activating the two sets of 4224 byte page registers enables a simultaneous program-
ming of two pages.
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A32 : Must be same as previous A32
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
A32 : Must be same as previous A32
3
Note3
60h
I/OX
R/B
60h 35h
tR
Address (3 Cycle) Address (3 Cycle)
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
1
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
1
Row Add.1,2,3 Row Add.1,2,3
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
2
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
2
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
3
A32 : Valid A32 : Must be same as previous A32
A32 : Must be same as previous A32
A32 : Must be same as previous A32
FLASH MEMORY
54
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Data Field Spare Field
(1) (3)
Plane0
Source page
Target page (1) : Two-Plane Read for Copy Back
(2) : Two-Plane Random Data Out
(3) : Two-Plane Copy-Back Program
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh.
(2) Data Field Spare Field
(1) (3)
Plane1
Source page
Target page
(2)
FLASH MEMORY
55
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B
85h 11h
tDBSY
Add.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Add.(2Cycles)
R/B
81h 10h
tPROG
Add.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Add.(2Cycles)
34
4
Destination Address
Destination Address
Figure 18. Two-Plane Copy-Back Program Operation with Random Data Input
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh.
Note3
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A32 : Must be same as previous A32
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
A32 : Must be same as previous A32
60h
I/OX
R/B
60h 35h
tR
Address (3 Cycle) Address (3 Cycle)
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
1
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
1
Row Add.1,2,3 Row Add.1,2,3
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
2
R/B
Data Output
I/Ox 00h 05h
Address (5 Cycle) E0h
Address (2 Cycle)
2
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
3
A32 : Valid A32 : Must be same as previous A32
A32 : Must be same as previous A32
A32 : Must be same as previous A32
FLASH MEMORY
56
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h or F1h/F2h command to the command register, a read
cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line
control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE or CE does not need to be toggled for updated status. Refer to table 2 for specific 70h Status Register definitions and table 3 for
specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it.
Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read
cycles.
Table 2. 70h Read Status Register Definition
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/O No. Page Program Block Erase Read Definition
I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Fail : "1"
I/O 1 Not use Not use Not use Don’t -cared
I/O 2 Not use Not use Not use Don’t -cared
I/O 3 Not Use Not Use Not Use Don’t -cared
I/O 4 Not Use Not Use Not Use Don’t -cared
I/O 5 Not Use Not Use Not Use Don’t -cared
I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1"
Table 3. F1h/F2h Read Status Register Definition
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/O No. Page Program Block Erase Read Definition
I/O 0 Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Fail : "1"
I/O 1 Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1"
I/O 2 Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1"
I/O 3 Not Use Not Use Not Use Don’t -cared
I/O 4 Not Use Not Use Not Use Don’t -cared
I/O 5 Not Use Not Use Not Use Don’t -cared
I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1"
FLASH MEMORY
57
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Figure 19. Read ID Operation
CE
CLE
I/OX
ALE
RE
WE
90h 00h
Address. 1cycle Maker code Device code
tCEA
tAR
tREA
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle
respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation
sequence.
Device 3rd Cyc. 4th Cyc.
ECh
tWHR
tCLR
Code
Device Device Code(2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9LBG08U0M D7h 55h B6h 78h
K9HCG08U1M Same as each K9LBG08U0M in it.
K9XDG08U5M
5th Cyc.
Figure 20. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 20 below.
FFh
I/OX
R/B tRST
Table 4. Device Status
After Power-up After Reset
Operation mode 00h Command is latched Waiting for next command
FLASH MEMORY
58
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
Table 5. Paired Page Address Information
Paired Page Address Paired Page Address
00h 04h 01h 05h
02h 08h 03h 09h
06h 0Ch 07h 0Dh
0Ah 10h 0Bh 11h
0Eh 14h 0Fh 15h
12h 18h 13h 19h
16h 1Ch 17h 1Dh
1Ah 20h 1Bh 21h
1Eh 24h 1Fh 25h
22h 28h 23h 29h
26h 2Ch 27h 2Dh
2Ah 30h 2Bh 31h
2Eh 34h 2Fh 35h
32h 38h 33h 39h
36h 3Ch 37h 3Dh
3Ah 40h 3Bh 41h
3Eh 44h 3Fh 45h
42h 48h 43h 49h
46h 4Ch 47h 4Dh
4Ah 50h 4Bh 51h
4Eh 54h 4Fh 55h
52h 58h 53h 59h
56h 5Ch 57h 5Dh
5Ah 60h 5Bh 61h
5Eh 64h 5Fh 65h
62h 68h 63h 69h
66h 6Ch 67h 6Dh
6Ah 70h 6Bh 71h
6Eh 74h 6Fh 75h
72h 78h 73h 79h
76h 7Ch 77h 7Dh
7Ah 7Eh 7Bh 7Fh
Note: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also
paired page data may be damaged(Table 5).
FLASH MEMORY
59
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 21). Its value can be
determined by the following guidance.
VCC
R/B
open drain output
Device
GND
Rp
Figure 21. Rp vs tr ,tf & Rp vs ibusy
ibusy
Busy
Ready Vcc
VOH
tf tr
VOL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
3.2V
8mA + ΣIL
VOL : 0.4V, VOH : 2.4V
CL
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
1K 2K 3K 4K
100n
200n 2m
1m
50
tf
100
150
200
3.6 3.6 3.6 3.6
2.4
1.2
0.8
0.6
FLASH MEMORY
60
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
DATA PROTECTION & POWER UP SEQUENCE
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 22. The two step command sequence for program/erase provides additional software protection.
Figure 22. AC Waveforms for Power Transition
VCC
WP
High
≈
≈
WE
~ 2.5V ~ 2.5V
10µs
≈≈
FLASH MEMORY
61
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
80h
I/O0~7
R/B
11h
Figure A-1. (2KB X 2) Program Operation
tDBSY
Address & Data Input
Address & Data Input
tPROG
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
Note: Any command between 11h and 81h is prohibited except 70h/F1h/F2h and FFh.
Note
Col Add1,2 & Row Add 1,2,3
2112 Byte Data
Col Add1,2 & Row Add 1,2,3
2112 Byte Data
A21 ~ A31 : Fixed ’Low’
A20 : Valid
A0 ~ A12 : Valid
A13 ~ A19 : Vaild
A21 ~ A31 : Valid
A20 : Must be same as previous A20
80h 10h 70h
85h 10hAdd.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Add.(5Cycles)
00h
R/B
Add.(5Cycles)
tR
Source Address
35h
I/Ox
Col. Add.1,2 & Row Add.1,2,3
1
Col. Add.1,2 & Row Add.1,2,3
1
Destination Address Destination Address
Data Output
≈
≈
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
A20 : Valid
A21 ~ A31 : Fixed ’Low’
A32 : Valid
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Must be same as previous A20
A21 ~ A31 : Valid
A32 : Must be same as previous A32
11h
Figure A-2. (2KB X 2) Copy-Back Program Operation
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h/F1h/F2h and FFh.
2KB PROGRAM OPERATION TIMING GUIDE
K9GAG08X0M is designed also to support the program operation with 2KByte data to offer the backward compatibility to the control-
ler which uses the NAND with 2KByte page. The command sequences are as follows.
A32 : Valid A32 : Must be same as previous A32
R/B tDBSY tPROG
FLASH MEMORY
62
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
R/B
85h 11h
tDBSY
Add.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Add.(2Cycles)
00h
R/B
Add.(5Cycles)
tR
Source Address
35h
I/Ox
Col. Add.1,2 & Row Add.1,2,3
1
R/B
85h 10h
tPROG
Add.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Add.(2Cycles)
12
2
Destination Address
Destination Address
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h/F1h/F2h and FFh.
Note3
Data Output
≈
≈
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
A20 : Valid
A21 ~ A31 : Fixed ’Low’
A32 : Valid
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Must be same as previous A20
A21 ~ A31 : Valid
A32 : Must be same as previous A32
Figure A-3. (2KB X 2) Copy-Back Program Operation with Random Data Input
FLASH MEMORY
63
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
2-PLANE PAGE PROGRAM OPERATION USING 4KB BUFFER RAM
K9GAG08X0M consists of 4KB pages and can support Two-Plane program operation. The internal RAM requirement for a controller
is 8KB, but for those controllers which support less than 8KB RAM, the following sequence can be used for Two-Plane program oper-
ation.
Data Field Spare Field
(1) (6)
Plane0
Source page
Target page
(1) : Two-Plane Read for Copy Back
(2) : Random Data Out On Plane 0 (Up to 4224Byte)
(3) : Random Data In On Plane 0 (Up to 4224Byte)
(4) : Random Data Out On Plane 1 (Up to 4224Byte)
(5) : Random Data In On Plane 1 (Up to 4224Byte)
(6): Two-Plane Program for Copy Back
(2)
(1) (6)
Plane1
Source page
Target page
(4)
4KByte 4KByte
(3) (5)
Data Field Spare Field
Col. Add.1,2
60h
I/OX
R/B
tPROG
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
1
R/B
I/Ox
1
Row Add.1,2,3 Row Add.1,2,3 Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
2
R/B
I/Ox
Add(3 Cycle) 60h
Add(3 Cycle) 35h 00h
Add(5 Cycle) 05h
Add(2 Cycle) DOUT
E0h
Up to 4224Byte
85h
Add(5 Cycle) DIN
Add(2 Cycle) 11h
85h DIN
Col. Add. 1,2 & Row Add.1,2,3 Col. Add.1,2
A0 ~ A12 : Fixed ’Low’
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’High’
A21 ~ A31 : Fixed ’Low’
A0 ~ A12 : Valid
00h
Add(5 Cycle) 05h
Add(2 Cycle) DOUT
E0h
Up to 4224Byte
tDBSY
Col. Add.1,2 & Row Add.1,2,3
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Fixed ’Low’
A20 : Fixed ’Low’
A21 ~ A31 : Fixed ’Low’
A32 : Must be same as previous A32
Col. Add.1,2
81h
Add(5 Cycle) DIN
Add(2 Cycle) 10h85h DIN
Col. Add.1,2 & Row Add.1,2,3
Destination Address
A0 ~ A12 : Valid
A13 ~ A19 : Valid
A20 : Fixed ’High’
A21 ~ A31 : Valid
A32 : Must be same as previous A32
2
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
tR
70h/F1h
Figure A-4. 2-Plane Copy-Back Program Operation with Ramdon Data Input
A32 : Valid A32 : Must be same as previous A32
A32 : Must be same as previous A32
A32 : Must be same as previous A32
FLASH MEMORY
64
K9LBG08U0M
K9MDG08U5M
K9HCG08U1M
WP AC TIMING GUIDE
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:
Figure B-1. Program Operation
1. Enable Mode
≈
80h 10h
WE
I/O
WP
R/B tww(min.100ns)
2. Disable Mode
≈
80h 10h
WE
I/O
WP
R/B tww(min.100ns)
1. Enable Mode
≈
60h D0h
tww(min.100ns)
2. Disable Mode
≈
60h D0h
tww(min.100ns)
Figure B-2. Erase Operation
WE
I/O
WP
R/B
WE
I/O
WP
R/B
