FALC®56
PEF 2256 H/E
List of Figures Page
Data Sheet 11 Rev. 1.1, 2005-06-13
Figure 1 Bipolar Violation Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2 GSM Base Station Aplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4 Pin Configuration P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5 Pin Configuration P-LBGA-81-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 7 FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 8 FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 10 Block Diagram of Test Access Port and Boundary Scan. . . . . . . . . . . 64
Figure 11 JTAG TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 12 Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 13 Single Voltage Power Supply Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 14 Dual Voltage Power Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 15 Decoupling Capacitor Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 16 Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 17 Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 18 Receive Line Monitoring (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19 Short Haul Protection Switching Application (E1) . . . . . . . . . . . . . . . . 76
Figure 20 Long Haul Protection Switching Application (E1). . . . . . . . . . . . . . . . . 77
Figure 21 Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22 Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23 The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 84
Figure 24 Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . . 87
Figure 25 2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 89
Figure 26 CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . 100
Figure 27 Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 28 Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 29 Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . 110
Figure 30 2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . 112
Figure 31 System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 32 Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . 116
Figure 33 SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 118
Figure 34 SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 118
Figure 35 RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . . 119
Figure 36 RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . . 119
Figure 37 Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . 120
Figure 38 Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . 121
Figure 39 SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 123
Figure 40 SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 123
Figure 41 Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 42 Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126