M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 256-Kbit serial IC bus EEPROM Datasheet - production data Features Compatible with all I2C bus modes: - 1 MHz - 400 kHz - 100 kHz Memory array: - 256 Kbit (32 Kbytes) of EEPROM - Page size: 64 bytes - Additional Write lockable page (M24256-D order codes) Single supply voltage and high speed: - 1 MHz clock from 1.7 V to 5.5 V Write: - Byte Write within 5 ms - Page Write within 5 ms Operating temperature range: from -40 C up to +85 C Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-year data retention Packages: - RoHS compliant and halogen-free (ECOPACK(R)) December 2012 This is information on a product in full production. TSSOP8 (DW) 169 mil width SO8 (MN) 150 mil width UFDFPN8 (MC) WLCSP (CS) Doc ID 6757 Rev 30 1/40 www.st.com 1 Contents M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 2.6.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Write Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 Lock Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 2/40 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 6757 Rev 30 3/40 List of tables M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/40 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (M24256-BW, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (M24256-BR, M24256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (M24256-BF, M24256-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 27 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 SO8N - 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 33 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 36 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections for the M24256-DFCS6TP/K (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . 34 M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 35 Doc ID 6757 Rev 30 5/40 Description 1 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Description The M24256 is a 256-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 32 K x 8 bits. The M24256-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24256-BR and M24256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24256-BF and M24256-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of -40 C / +85 C. The M24256-Dx offers an additional page, named the Identification Page (64 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1. Logic diagram 6## % % 3$! -XXX 3#, 7# 633 Table 1. Signal names Signal name 6/40 !)F Function Direction E2, E1, E0 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Figure 2. Description 8-pin package connections % % % 633 6## 7# 3#, 3$! !)F 1. DU: Don't Use (if connected, must be connected to VSS) 2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1. Figure 3. WLCSP connections for the M24256-DFCS6TP/K (top view, marking side, with balls on the underside) % 7# % 633 6## 3$! 3#, % -36 Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light. Doc ID 6757 Rev 30 7/40 Signal description M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, as shown in Table 2. When not connected (left floating), these inputs are read as low (0). Figure 4. Device select code VCC VCC M24xxx M24xxx Ei Ei VSS VSS Ai12806 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. 8/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Signal description Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters) and the rise time must not vary faster than 1 V/s. 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). Doc ID 6757 Rev 30 9/40 Memory organization 3 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Memory organization The memory is organized as shown below. Figure 5. Block diagram 7# % % % (IGH VOLTAGE GENERATOR #ONTROL LOGIC 3#, 3$! )/ SHIFT REGISTER $ATA REGISTER 9 DECODER !DDRESS REGISTER AND COUNTER PAGE )DENTIFICATION PAGE 8 DECODER -36 10/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. Figure 6. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition AI00792B Doc ID 6757 Rev 30 11/40 Device operation 4.1 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 4.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 12/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E2, E1, E0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Doc ID 6757 Rev 30 13/40 Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. A15 Table 4. A7 Most significant address byte A14 A13 A12 A11 A10 A9 A8 A3 A2 A1 A0 Least significant address byte A6 A5 A4 When the bus master generates a Stop condition immediately after a data byte Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition and the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 8. 14/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC = 0 (data write enabled) WC ACK ACK ACK Byte addr Byte addr ACK Data in Stop Dev sel Start Byte Write R/W WC ACK Page Write Dev sel Start ACK Byte addr ACK Byte addr ACK Data in 1 Data in 2 R/W WC (cont'd) ACK Page Write (cont'd) ACK Data in N Stop 5.1.1 Instructions Doc ID 6757 Rev 30 AI01106d 15/40 Instructions 5.1.2 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a "roll-over" occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 8. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte addr ACK Byte addr NO ACK Data in Stop Dev sel Start Byte Write ACK R/W WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr NO ACK Data in 1 Data in 2 R/W WC (cont'd) NO ACK Data in N Stop Page Write (cont'd) NO ACK 16/40 Doc ID 6757 Rev 30 AI01120d M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 5.1.3 Instructions Write Identification Page (M24256-D only) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: Device type identifier = 1011b MSB address bits A15/A6 are don't care except for address bit A10 which must be `0'. LSB address bits A5/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 5.1.4 Lock Identification Page (M24256-D only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: 5.1.5 Device type identifier = 1011b Address bit A10 must be `1'; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care ECC (Error Correction Code) and Write cycling The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(1). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(1). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 11: Cycling performance by groups of four bytes. 1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. Doc ID 6757 Rev 30 17/40 Instructions 5.1.6 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 9. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK returned YES NO Next Operation is addressing the memory YES Send Address and Receive ACK ReStart Stop NO StartCondition YES Data for the Write cperation Device select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847e AI01847d 1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling instruction in the figure). 18/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its Standby mode. Figure 10. Read mode sequences ACK Data out Stop Start Dev sel NO ACK R/W ACK Random Address Read Byte addr Dev sel * ACK ACK Data out 1 Data out R/W NO ACK Data out N R/W ACK ACK Byte addr ACK Byte addr R/W ACK Dev sel * Start Dev sel * ACK Data out1 R/W NO ACK Data out N Stop ACK NO ACK Stop Start Dev sel Sequention Random Read ACK Byte addr R/W ACK Sequential Current Read ACK Start Start Dev sel * ACK Stop Current Address Read Start 5.2 Instructions Doc ID 6757 Rev 30 AI01105d 19/40 Instructions 5.2.1 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.2 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the Identification page, therefore the next Current Address Read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1) instead of the Current Address Read instruction. 5.2.3 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter "rolls-over", and the device continues to output data from memory address 00h. 5.3 Read Identification Page (M24256-D only) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A6 are don't care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes). 20/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 5.4 Initial delivery state Read the lock status (M24256-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that: 6 Start: the truncated command is not executed because the Start condition resets the device internal logic, Stop: the device is then set back into Standby mode by the Stop condition. Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). Doc ID 6757 Rev 30 21/40 Maximum rating 7 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max. Unit Ambient operating temperature -40 130 C Storage temperature -65 150 C (1) C - 5 mA -0.50 6.5 V -0.50 6.5 V - 4000(3) V Lead temperature during soldering IOL DC output current (SDA = 0) VIO Input or output range VCC Supply voltage VESD Electrostatic pulse (Human Body model)(2) see note 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 ). 3. 3000 V for previous devices (process letters KA). 22/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 8 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature -40 85 C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature -40 85 C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.7 5.5 V TA Ambient operating temperature -40 85 C fC Operating clock frequency - 1 MHz Min. Max. Unit VCC Table 7. Parameter Operating conditions (voltage range R) Symbol VCC Table 8. Parameter Operating conditions (voltage range F) Symbol VCC Table 9. Parameter AC measurement conditions Symbol Cbus Parameter Load capacitance 100 SCL input rise/fall time, SDA input fall time - pF 50 ns Input levels 0.2 VCC to 0.8 VCC V Input and output timing reference levels 0.3 VCC to 0.7 VCC V Figure 11. AC measurement I/O waveform )NPUT VOLTAGE LEVELS 6## )NPUT AND OUTPUT 4IMING REFERENCE LEVELS 6## 6## 6## -36 Doc ID 6757 Rev 30 23/40 DC and AC parameters Table 10. M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - k VIN > 0.7 VCC 500 - k ZL ZH Input impedance (E2, E1, E0, WC)(2) 1. Characterized only, not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). Table 11. Symbol Ncycle Cycling performance by groups of four bytes Parameter Write cycle endurance(2) Test condition(1) Max. TA 25 C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(3) 1. Cycling performance for products identified by process letter KB. 2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification. 3. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling. Table 12. Memory cell data retention Parameter Data retention(1) Test condition TA = 55 C Min. Unit 200 Year 1. For products identified by process letter K. The data retention behavior is checked in production. The 200year limit is defined from characterization and qualification results. 24/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Table 13. DC characteristics (M24256-BW, device grade 6) Symbol Parameter ILI Input leakage current (SCL, SDA, E2, E1, E0) ILO Output leakage current ICC ICC0 ICC1 VIL VIH VOL DC and AC parameters Test conditions (in addition to those in Table 6) Min. Max. Unit VIN = VSS or VCC, device in Standby mode - 2 A SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - 2 A VCC = 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 1 mA VCC = 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 2 mA 2.5 V < VCC < 5.5 V, fc = 1 MHz(1) (rise/fall time < 50 ns) - 2.5 mA - 2(2) mA Device not selected(3), VIN = VSS or VCC, VCC = 2.5 V - 2 A Device not selected(3), VIN = VSS or VCC, VCC = 5.5 V - 3 A Input low voltage (SCL, SDA, WC) -0.45 0.3 VCC V Input high voltage (SCL, SDA) 0.7 VCC 6.5 V Input high voltage (WC, E2, E1, E0) 0.7 VCC VCC+0.6 Supply current (Read) Supply current (Write) During tW, 2.5 V < VCC < 5.5 V Standby supply current Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V - 0.4 V V 1. Only for devices operating at fC max = 1 MHz (see Table 17). 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). Doc ID 6757 Rev 30 25/40 DC and AC parameters Table 14. Symbol M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC characteristics (M24256-BR, M24256-DR, device grade 6) Test conditions(1) (in addition to those in Table 7) Parameter Min. Max. Unit ILI Input leakage current (E1,E2, SCL, SDA) VIN = VSS or VCC, device in Standby mode - 2 A ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - 2 A VCC = 1.8 V, fc= 400 kHz - 0.8 mA fc= 1 MHz(2) - 2.5 mA During tW, VCC = 1.8 V - 2(3) mA - 1 A ICC ICC0 Supply current (Read) Supply current (Write) (4), ICC1 Standby supply current Device not selected VIN = VSS or VCC, VCC = 1.8 V VIL Input low voltage (SCL, SDA, WC) 1.8 V VCC < 2.5 V -0.45 0.25 VCC V Input high voltage (SCL, SDA) 1.8 V VCC < 2.5 V 0.75 VCC 6.5 V Input high voltage (WC, E2, E1, E0) 1.8 V VCC < 2.5 V 0.75 VCC VCC+0.6 Output low voltage IOL = 1 mA, VCC = 1.8 V VIH VOL - 0.2 1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 C < TA < +85 C, please refer to Table 13 instead of this table. 2. Only for devices identified with process letter K. 3. Characterized value, not tested in production. 4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 26/40 Doc ID 6757 Rev 30 V V M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Table 15. Symbol DC and AC parameters DC characteristics (M24256-BF, M24256-DF, device grade 6) Test conditions(1) (in addition to those in Table 8) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - 2 A ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - 2 A VCC = 1.7 V, fc= 400 kHz - 0.8 mA fc= 1 MHz(2) - 2.5 mA VCC = 1.6 V, fc= 400 kHz 0.8 mA mA ICC ICC Supply current (Read) Supply current (Read) ICC0 Supply current (Write) During tW 1.7 V < VCC < 2.5 V - 2(3) ICC1 Standby supply current Device not selected(4), VIN = VSS or VCC, VCC = 1.7 V - 1 A VIL Input low voltage (SCL, SDA, WC) 1.7 V VCC < 2.5 V -0.45 0.25 VCC V Input high voltage (SCL, SDA) 1.7 V VCC < 2.5 V 0.75 VCC 6.5 V Input high voltage (WC, E2, E1, E0) 1.7 V VCC < 2.5 V 0.75 VCC VCC+0.6 Output low voltage IOL = 1 mA, VCC = 1.7 V VIH VOL - 0.2 V V 1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 13 instead of this table. 2. Only for devices identified by process letter K (see Table 17). 3. Characterized value, not tested in production. 4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). Doc ID 6757 Rev 30 27/40 DC and AC parameters Table 16. M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max. Unit - 400 kHz Clock pulse width high 600 - ns Clock pulse width low 1300 - ns SDA (out) fall time 20(2) 300 ns Input signal rise time (3) (3) ns (3) ns tXL1XL2 tF Input signal fall time (3) tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns 100 - ns - 900 ns tCLQX (4) tDH Data out hold time tCLQV (5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL(6)(1) tSU:WC WC set up time (before the Start condition) 0 - s tDHWH(7)(1) tHD:WC WC hold time (after the Stop condition) 1 - s tW tWR Internal Write cycle duration - 5 ms Pulse width ignored (input filter on SCL and SDA) - single glitch - 80 ns tNS(1) 1. Characterized only, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus x Cbus time constant is within the values specified in Figure 12. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. 28/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Table 17. 1 MHz AC characteristics Parameter(1) Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tXH1XH2 tXL1XL2 tQL1QL2 (3) DC and AC parameters Min. Max. Unit 0 1 MHz Clock pulse width high 260 - ns tLOW Clock pulse width low 500 - ns tR Input signal rise time (2) (2) ns Input signal fall time (2) (2) ns 120 ns tF tF SDA (out) fall time 20 (4) tDXCX tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns 100 - ns - 450(7) ns tCLQX(5) tCLQV(6) tDH tAA Data out hold time Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns 500 - ns tSU:WC WC set up time (before the Start condition) 0 - s tHD:WC WC hold time (after the Stop condition) 1 - s Write time - 5 ms Pulse width ignored (input filter on SCL and SDA) - 80(10) ns tDHDL tWLDL(8)(3) tDHWH (9)(3) tW tBUF tWR tNS(3) Time between Stop condition and next Start condition 1. Only for M24256 devices identified by the process letter K. 2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 3. Characterized only, not tested in production. 4. With CL = 10 pF. 5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus x Cbus time constant is within the values specified in Figure 12. 7. 500 ns for the previous products. 8. WC=0 set up time condition to enable the execution of a WRITE command. 9. WC=0 hold time condition to enable the execution of a WRITE command. 10. 50 ns for previous products. Doc ID 6757 Rev 30 29/40 DC and AC parameters M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz "US LINE PULL UP RESISTOR K K1/2 4HE 2 BUS X #BUS TIME CONSTANT MUST BE BELOW THE NS TIME CONSTANT LINE REPRESENTED ON THE LEFT 2 BU S # BU S (ERE 2BUS #BUS NS 6## 2BUS N S )# BUS MASTER 3#, -XXX 3$! P& "US LINE CAPACITOR P& #BUS AIB Figure 13. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz "US LINE PULL UP RESISTOR K 6## 4HE 2BUS #BUS TIME CONSTANT MUST BE BELOW THE NS TIME CONSTANT LINE REPRESENTED ON THE LEFT 2 BUS # BUS NS 2BUS )# BUS MASTER 3#, -XXX 3$! (ERE 2 BUS #BUS NS #BUS "US LINE CAPACITOR P& -36 30/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Figure 14. AC waveforms 3TART CONDITION 3TART 3TOP CONDITION CONDITION T8,8, T8(8( T#(#, T#,#( 3#, T$,#, T8,8, 3$! )N T#($, T8(8( 3$! )NPUT T#,$8 3$! T$8#( #HANGE T#($( T$($, 7# T$(7( T7,$, 3TOP CONDITION 3TART CONDITION 3#, 3$! )N T7 T#($( T#($, 7RITE CYCLE 3#, T#,16 3$! /UT T#,18 $ATA VALID T1,1, $ATA VALID !)G Doc ID 6757 Rev 30 31/40 Package mechanical data 9 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 15. TSSOP8 - 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 18. TSSOP8 - 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP 0.0472 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 2.900 3.000 3.100 e 0.650 E 6.400 6.200 6.600 E1 4.400 4.300 L 0.600 0.450 L1 1.000 0.0039 0.1181 0.1142 0.1220 0.2520 0.2441 0.2598 4.500 0.1732 0.1693 0.1772 0.750 0.0236 0.0177 0.0295 0 8 0.0256 0.0394 0 8 1. Values in inches are converted from mm and rounded to four decimal digits. 32/40 Max. 0.0020 D Min. 1.200 A1 A2 Typ. Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Package mechanical data Figure 16. SO8N - 8-lead plastic small outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8N - 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min A Max Typ Min 1.750 Max 0.0689 A1 0.100 A2 1.250 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.250 0.0039 0.0098 0.0492 0.100 0.0039 D 4.900 4.800 5.000 0.1929 0.1890 0.1969 E 6.000 5.800 6.200 0.2362 0.2283 0.2441 E1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 k 0 8 0 8 L 0.400 1.270 0.0157 0.0500 L1 1.040 0.0409 1. Values in inches are converted from mm and rounded to four decimal digits. Doc ID 6757 Rev 30 33/40 Package mechanical data M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Figure 17. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline E $ , , 0IN % B % + , ! $ EEE ! :7?-%E6 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.550 0.450 0.600 0.0217 0.0177 0.0236 A1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 D 2.000 1.900 2.100 0.0787 0.0748 0.0827 1.200 1.600 0.0472 0.0630 2.900 3.100 0.1142 0.1220 1.200 1.600 0.0472 0.0630 D2 (rev MC) E 3.000 E2 (rev MC) e 0.500 0.1181 0.0197 K (rev MC) 0.300 L 0.300 L1 0.0118 0.500 0.0118 0.150 0.0197 0.0059 L3 0.300 0.0118 eee(2) 0.080 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 34/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Package mechanical data Figure 18. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline BBB : $ 8 ( 9 2EFERENCE E & E AAA ! ! 8 7AFER BACK SIDE E & $ETAIL ! % E ' /RIENTATION "UMPS SIDE 3IDE VIEW "UMP ! EEE : B CCC DDD : 3EATING PLANE - : 89 - : $ETAIL ! 2OTATED #G?-%?6 1. Drawing is not to scale Doc ID 6757 Rev 30 35/40 Package mechanical data Table 21. M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 0.0075 A2 0.350 0.0138 b 0.270 0.0106 D 1.271 1.291 0.0500 0.0508 E 1.358 1.378 0.0535 0.0543 e 0.800 0.0315 e1 0.693 0.0273 e2 0.400 0.0157 e3 0.400 0.0157 F 0.333 0.0131 G 0.235 0.0093 H 0.236 0.0093 8 8 aaa 0.110 0.0043 bbb 0.110 0.0043 ccc 0.110 0.0043 ddd 0.060 0.0024 eee 0.060 0.0024 N (number of terminals) 1. Values in inches are converted from mm and rounded to four decimal digits. 36/40 Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF 10 Part numbering Part numbering Table 22. Ordering information scheme Example: M24256 - D W MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function 256 = 256 Kbit (32 K x 8) Device family B = Without Identification page D = With additional Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package MN = SO8 (150 mil width)(1) DW = TSSOP8 (169 mil width)(1) MC = UFDFPN8 (MLP8)(1) CS = 8-bump thin WLCSP(1) Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 C Option blank = standard packing T = Tape and reel packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process(2) /K = Manufacturing technology code 1. RoHS-compliant and halogen-free (ECOPACK2(R)) 2. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. Doc ID 6757 Rev 30 37/40 Revision history 11 Revision history Table 23. Document revision history Date Revision 19-Jan-2010 20 Revision number corrected at bottom of pages. 04-Mar-2010 21 Process description corrected in Table 23: Ordering information scheme. 22 Updated text in: Features, Section 1: Description, Section 3.1: Start condition, Section 3.6: Write operations, Section 3.9: Write Identification Page (M24256-D only), Section 3.10: Lock Identification Page (M24256-D only), Section 3.11: ECC (error correction code) and write cycling, Section 3.17: Reading the Identification Page (M24256-D only), Section 3.18: Reading the lock status (M24256-D only), Table 10: AC test measurement conditions, Section 8: Part numbering. Updated the following according to the IC_bus specification: Table 17: 400 kHz AC characteristics, Table 18: 1 MHz AC characteristics, Figure 13: AC waveforms. 23 Added caution under Figure 3: WLCSP connections (top view, marking side, with balls on the underside). Updated: - Description - Section 3.5: Addressing the memory array - Section 3.17: Reading the Identification Page (M24256-D only) - Section 3.18: Reading the lock status (M24256-D only) - Table 2: Most significant address byte - Table 6: Absolute maximum ratings - Table 17: 400 kHz AC characteristics - Table 18: 1 MHz AC characteristics Moved: - Table 2: Most significant address byte from Section 2.6.4 to Section 3.5 Deleted: - Table 3: Device select code to access the Identification page (M24256DR only) - Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) - Table 26: Available M24256-DR products (package, voltage range, temperature grade) 24 Added Table 12: Memory cell characteristics. Updated: - Section 1: Description - Table 6: Absolute maximum ratings - ICC0 maximum value in Table 14: DC characteristics (voltage range W, device grade 6), Table 15: DC characteristics (voltage range R) and Table 16: DC characteristics (voltage range F) Deleted all references to package SO8 (MW) 208 mils width. 21-Dec-2010 14-Feb-2011 05-Jul-2011 38/40 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Changes Doc ID 6757 Rev 30 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Table 23. Date Revision history Document revision history (continued) Revision Changes 25 Updated UFDFPN8 silhouette on cover page, Figure 16: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline and Table 21: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data to add MC version. 22-Jun-2012 26 Datasheet revision 25 split into: - M24256-125 datasheet for automotive products (range 3), - M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF (this datasheet) for standard products (range 6). Added: - Reference M24256-DF - Table 1: Signal names, Table 12: Memory cell data retention Updated: - Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC characteristics: added set up and hold timing conditiions on WC (tWLDL and tDHWH) - Figure 18: M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline and Table 21: M24256-DFCS6TP/K, WLCSP 8bump wafer-level chip scale package mechanical data - Cycling and data retention limits Deleted: - UFDFPN8, package revision MB 01-Aug-2012 27 Updated Figure 3: WLCSP connections for the M24256-DFCS6TP/K (top view, marking side, with balls on the underside) and Figure 18: M24256DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline. 18-Sep-2012 28 Changed title of Figure 3: WLCSP connections for the M24256DFCS6TP/K (top view, marking side, with balls on the underside). Updated Section 5.2.2: Current Address Read. 20-Nov-2012 29 Corrected "Device family" data in Table 22: Ordering information scheme. 30 Deleted note (3) under Table 2: Device select code. Modified ICCO condition in Table 14: DC characteristics (M24256-BR, M24256-DR, device grade 6). Deleted incorrect table (Table 15. DC characteristics (M24256-R, device grade 6)). Updated package list in Table 22: Ordering information scheme. 16-Nov-2011 17-Dec-2012 Doc ID 6757 Rev 30 39/40 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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