This is information on a product in full production.
December 2012 Doc ID 6757 Rev 30 1/40
1
M24256-BW M24256-BR M24256-BF
M24256-DR M24256-DF
256-Kbit serial I²C bus EEPROM
Datasheet production data
Features
Compatible with all I2C bus modes:
–1 MHz
400 kHz
100 kHz
Memory array:
256 Kbit (32 Kbytes) of EEPROM
Page size: 64 bytes
Additional Write lockable page
(M24256-D order codes)
Single supply voltage and high speed:
1 MHz clock from 1.7 V to 5.5 V
Write:
Byte Write within 5 ms
Page Write within 5 ms
Operating temperature range: from -40 °C up
to +85 °C
Random and sequential Read modes
Write protect of the whole memory array
Enhanced ESD/Latch-Up protection
More than 4 million Write cycles
More than 200-year data retention
Packages:
RoHS compliant and halogen-free
(ECOPACK®)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8
(MC)
WLCSP (CS)
www.st.com
Contents M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
2/40 Doc ID 6757 Rev 30
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Write Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . 17
5.1.4 Lock Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17
5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Read Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Read the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of tables M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
4/40 Doc ID 6757 Rev 30
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. DC characteristics (M24256-BW, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. DC characteristics (M24256-BR, M24256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . 26
Table 15. DC characteristics (M24256-BF, M24256-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 27
Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 33
Table 20. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 36
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF List of figures
Doc ID 6757 Rev 30 5/40
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections for the M24256-DFCS6TP/K
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33
Figure 17. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . 34
Figure 18. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 35
Description M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
6/40 Doc ID 6757 Rev 30
1 Description
The M24256 is a 256-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 32 K × 8 bits.
The M24256-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24256-BR and
M24256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24256-BF and
M24256-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate
with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C /
+85 °C.
The M24256-Dx offers an additional page, named the Identification Page (64 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
E2, E1, E0 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage
VSS Ground
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6##
-XXX
7#
3#,
633
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Description
Doc ID 6757 Rev 30 7/40
Figure 2. 8-pin package connections
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Figure 3. WLCSP connections for the M24256-DFCS6TP/K
(top view, marking side, with balls on the underside)
Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
3$!633
3#,
7#%
% 6##
%
!)F
-36
%
%
%
7#
6##
3#,
3$!
633
Signal description M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
8/40 Doc ID 6757 Rev 30
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12
indicates how to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, as shown in Ta bl e 2 . When not connected (left floating), these inputs are read as low
(0).
Figure 4. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
2.5 VSS (ground)
VSS is the reference for the VCC supply voltage.
Ai12806
VCC
M24xxx
VSS
Ei
VCC
M24xxx
VSS
Ei
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2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Memory organization M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
10/40 Doc ID 6757 Rev 30
3 Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
-36
7#
#ONTROLLOGIC (IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
)DENTIFICATIONPAGE
%
%
3#,
3$!
%
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Doc ID 6757 Rev 30 11/40
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 6. I2C bus protocol
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
123 789
MSB ACK
START
Condition
SCL 123 789
MSB ACK
STOP
Condition
Device operation M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
12/40 Doc ID 6757 Rev 30
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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4.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta b l e 2 (on Serial Data (SDA), most significant bit first).
When the device select code is received, the device only responds if the Chip Enable
Address is the same as the value on the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)
2. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code
when addressing the
memory array
1010E2E1E0RW
Device select code
when accessing the
Identification page
1011E2E1E0RW
Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
14/40 Doc ID 6757 Rev 30
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
Table 3. Most significant address byte
A15 A14 A13 A12 A11 A10 A9 A8
Table 4. Least significant address byte
A7 A6 A5 A4 A3 A2 A1 A0
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions
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5.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
Figure 7. Write mode sequences with WC = 0 (data write enabled)
Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
16/40 Doc ID 6757 Rev 30
5.1.2 Page Write
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
Stop
Start
Byte Write Dev sel Byte addr Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01120d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions
Doc ID 6757 Rev 30 17/40
5.1.3 Write Identification Page (M24256-D only)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
Device type identifier = 1011b
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A5/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4 Lock Identification Page (M24256-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
5.1.5 ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the
I2C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(1). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(1). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 11: Cycling performance by groups of four bytes.
1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an
integer.
Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
18/40 Doc ID 6757 Rev 30
5.1.6 Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
Write cycle
in progress
AI
01847
d
AI01847e
Next
Operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write cperation
Device select
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO StartCondition
Continue the
Write operation
Continue the
Random Read operation
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions
Doc ID 6757 Rev 30 19/40
5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 10. Read mode sequences
Start
Dev sel * Byte addr Byte addr
Start
Dev sel Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev sel Data out
Random
Address
Read
Stop
Start
Dev sel * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev sel * Byte addr Byte addr
Sequention
Random
Read
Start
Dev sel * Data out1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
Instructions M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
20/40 Doc ID 6757 Rev 30
5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the byte location in the Identification page, therefore the next Current
Address Read in the memory uses this new address counter value. When accessing the
memory, it is safer to always use the Random Address Read instruction (this instruction
loads the address counter with the byte location to read in the memory, see Section 5.2.1)
instead of the Current Address Read instruction.
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.3 Read Identification Page (M24256-D only)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A6 are don't
care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the number of bytes should be less than
or equal to 54, as the ID page boundary is 64 bytes).
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Initial delivery state
Doc ID 6757 Rev 30 21/40
5.4 Read the lock status (M24256-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
Stop: the device is then set back into Standby mode by the Stop condition.
6 Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
Maximum rating M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
22/40 Doc ID 6757 Rev 30
7 Maximum rating
Stressing the device outside the ratings listed in Ta b le 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
IOL DC output current (SDA = 0) - 5 mA
VIO Input or output range –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (Human Body model)(2)
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω).
- 4000(3)
3. 3000 V for previous devices (process letters KA).
V
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters
Doc ID 6757 Rev 30 23/40
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Figure 11. AC measurement I/O waveform
Table 6. Operating conditions (voltage range W)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1 MHz
Table 7. Operating conditions (voltage range R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1 MHz
Table 8. Operating conditions (voltage range F)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1 MHz
Table 9. AC measurement conditions
Symbol Parameter Min. Max. Unit
Cbus Load capacitance 100 pF
SCL input rise/fall time, SDA input fall time - 50 ns
Input levels 0.2 VCC to 0.8 VCC V
Input and output timing reference levels 0.3 VCC to 0.7 VCC V
-36
6##
6##
6##
6##
)NPUTANDOUTPUT
4IMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
DC and AC parameters M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
24/40 Doc ID 6757 Rev 30
Table 10. Input parameters
Symbol Parameter(1)
1. Characterized only, not tested in production.
Test condition Min. Max. Unit
CIN Input capacitance (SDA) - - 8 pF
CIN Input capacitance (other pins) - - 6 pF
ZLInput impedance (E2, E1, E0, WC)(2)
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
VIN < 0.3 VCC 30 - kΩ
ZHVIN > 0.7 VCC 500 - kΩ
Table 11. Cycling performance by groups of four bytes
Symbol Parameter Test condition(1)
1. Cycling performance for products identified by process letter KB.
Max. Unit
Ncycle Write cycle
endurance(2)
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
TA 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 Write cycle(3)
3. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling.
TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000
Table 12. Memory cell data retention
Parameter Test condition Min. Unit
Data retention(1)
1. For products identified by process letter K. The data retention behavior is checked in production. The 200-
year limit is defined from characterization and qualification results.
TA = 55 °C 200 Year
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters
Doc ID 6757 Rev 30 25/40
Table 13. DC characteristics (M24256-BW, device grade 6)
Symbol Parameter Test conditions (in addition to those
in Tabl e 6)Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
VIN = VSS or VCC, device in Standby
mode 2µA
ILO
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
2µA
ICC Supply current (Read)
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns) -1mA
VCC = 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns) -2mA
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
1. Only for devices operating at fC max = 1 MHz (see Table 17).
-2.5mA
ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V - 2(2)
2. Characterized value, not tested in production.
mA
ICC1
Standby supply
current
Device not selected(3), VIN = VSS or
VCC, VCC = 2.5 V
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-2µA
Device not selected(3), VIN = VSS or
VCC, VCC = 5.5 V -3µA
VIL
Input low voltage
(SCL, SDA, WC)–0.45 0.3 VCC V
VIH
Input high voltage
(SCL, SDA) 0.7 VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 0.7 VCC VCC+0.6 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V -0.4V
DC and AC parameters M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
26/40 Doc ID 6757 Rev 30
Table 14. DC characteristics (M24256-BR, M24256-DR, device grade 6)
Symbol Parameter Test conditions(1) (in addition
to those in Tabl e 7)
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E1,E2, SCL, SDA)
VIN = VSS or VCC, device in
Standby mode 2µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
2µA
ICC Supply current (Read)
VCC = 1.8 V, fc= 400 kHz - 0.8 mA
fc= 1 MHz(2)
2. Only for devices identified with process letter K.
-2.5mA
ICC0 Supply current (Write) During tW, VCC = 1.8 V - 2(3)
3. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(4),
VIN = VSS or VCC, VCC = 1.8 V
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-1µA
VIL
Input low voltage
(SCL, SDA, WC)1.8 V V
CC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) 1.8 V V
CC < 2.5 V 0.75 VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 1.8 V V
CC < 2.5 V 0.75 VCC VCC+0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V - 0.2 V
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters
Doc ID 6757 Rev 30 27/40
Table 15. DC characteristics (M24256-BF, M24256-DF, device grade 6)
Symbol Parameter Test conditions(1) (in addition
to those in Tab l e 8 )
1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode 2µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
2µA
ICC Supply current (Read)
VCC = 1.7 V, fc= 400 kHz - 0.8 mA
fc= 1 MHz(2)
2. Only for devices identified by process letter K (see Table 17).
-2.5mA
ICC Supply current (Read) VCC = 1.6 V, fc= 400 kHz 0.8 mA
ICC0 Supply current (Write) During tW 1.7 V < VCC < 2.5 V - 2(3)
3. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(4),
VIN = VSS or VCC, VCC = 1.7 V
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-1µA
VIL
Input low voltage
(SCL, SDA, WC) 1.7 V V
CC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) 1.7 V V
CC < 2.5 V 0.75 VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 1.7 V V
CC < 2.5 V 0.75 VCC VCC+0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.7 V - 0.2 V
DC and AC parameters M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
28/40 Doc ID 6757 Rev 30
Table 16. 400 kHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock frequency - 400 kHz
tCHCL tHIGH Clock pulse width high 600 - ns
tCLCH tLOW Clock pulse width low 1300 - ns
tQL1QL2(1)
1. Characterized only, not tested in production.
tFSDA (out) fall time 20(2)
2. With CL = 10 pF.
300 ns
tXH1XH2 tRInput signal rise time (3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz.
(3) ns
tXL1XL2 tFInput signal fall time (3) (3) ns
tDXCH tSU:DAT Data in set up time 100 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(4)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 100 - ns
tCLQV(5)
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
tAA Clock low to next data valid (access time) - 900 ns
tCHDL tSU:STA Start condition setup time 600 - ns
tDLCL tHD:STA Start condition hold time 600 - ns
tCHDH tSU:STO Stop condition set up time 600 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 - ns
tWLDL(6)(1)
6. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(7)(1)
7. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Internal Write cycle duration - 5 ms
tNS(1) Pulse width ignored (input filter on SCL and
SDA) - single glitch -80ns
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters
Doc ID 6757 Rev 30 29/40
Table 17. 1 MHz AC characteristics
Symbol Alt. Parameter(1)
1. Only for M24256 devices identified by the process letter K.
Min. Max. Unit
fCfSCL Clock frequency 0 1 MHz
tCHCL tHIGH Clock pulse width high 260 - ns
tCLCH tLOW Clock pulse width low 500 - ns
tXH1XH2 tRInput signal rise time (2)
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC<1MHz.
(2) ns
tXL1XL2 tFInput signal fall time (2) (2) ns
tQL1QL2(3)
3. Characterized only, not tested in production.
tFSDA (out) fall time 20(4)
4. With CL = 10 pF.
120 ns
tDXCX tSU:DAT Data in setup time 50 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 100 - ns
tCLQV(6)
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 12.
tAA Clock low to next data valid (access time) - 450(7)
7. 500 ns for the previous products.
ns
tCHDL tSU:STA Start condition setup time 250 - ns
tDLCL tHD:STA Start condition hold time 250 - ns
tCHDH tSU:STO Stop condition setup time 250 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 500 - ns
tWLDL(8)(3)
8. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(9)(3)
9. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 5 ms
tNS(3) Pulse width ignored (input filter on SCL and
SDA) -80
(10)
10. 50 ns for previous products.
ns