Digital 2.5 W, 5.1 V, Boost Class-D Audio Amplifier with Output Sensing SSM4567 Data Sheet FEATURES Output noise: 21.7 V rms, A-weighted THD + N: 0.025% at 1 kHz, 500 mW output power PSSR: 90 dB at 217 Hz, with dither input 72 dB signal-to-noise ratio (SNR) on output current sensing and 77 dB SNR on voltage sensing Quiescent power consumption: 19.8 mW Pop-and-click suppression Flexible battery monitoring AGC Short-circuit protection for boost and Class-D outputs and thermal protection with automatic recovery Smart power-down when PDM stop condition or no clock input detected DC blocking high-pass filter and static input DC protection for PDM input Selectable ultralow EMI emissions and low latency modes Filterless Class-D amplifier with spread-spectrum - modulation with integrated boost regulator (5.1 V) Digitized output of output voltage, output current, and VBAT supply voltage Integrated boost regulator Multiple serial data formats PDM input/output TDM slave with support for up to 8 chips on a single bus I2S or left justified slave Multichip I2S with support for up to 4 chips on one I2S bus 8 kHz to 192 kHz PCM sample rates 2.048 to 6.14 MHz PDM input sample rates Configurable via I2C control, TDM control, or PDM patterns Standalone control modes 2.5 W into 4 load and 1.42 W into 8 load at 3.6 V supply with <1% total harmonic distortion plus noise (THD + N) Available in 19-ball, 1.74 mm x 2.1 mm, 0.4 mm pitch WLCSP 89.7% system efficiency into 8 at 1 W, VBAT = 3.6 V APPLICATIONS Mobile handsets Tablets Portable media players FUNCTIONAL BLOCK DIAGRAM LR_SEL/ ADDR SEL BSTSW SSM4567 BSTSW VBST VBST SCL BOOST (5V) DAC_PDM_DAT/ DAC_SDATAI FILTERING MODULATION DAC - CLASS-D MOD H-BRIDGE (5V) DAC_PDM_CLK/ BCLK OUTN R OUTP I2S/TDM/ PDM INTERFACE SNS_PDM_CLK/ FSYNC IOVDD ADC V SENSE ADC I SENSE AGND VBAT PGND 12278-001 SNS_PDM_DAT/ SNS_SDATAO SDA Figure 1. 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Technical Support www.analog.com SSM4567 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Integrated Boost Converter....................................................... 25 Applications ....................................................................................... 1 Applications Information .............................................................. 26 Functional Block Diagram .............................................................. 1 Component Selection for Boost Regulators ............................... 26 Table of Contents .............................................................................. 2 Layout .......................................................................................... 26 Revision History ............................................................................... 3 Power Supply Decoupling ......................................................... 27 General Description ......................................................................... 4 Typical Application Circuits ......................................................... 28 Specifications..................................................................................... 5 Software Control Mode, I2S/TDM Interface........................... 28 Digital Input/Output .................................................................... 6 Software Control Mode, PDM Interface ................................. 29 Absolute Maximum Ratings ............................................................ 7 Standalone Mode, I2S/TDM Interface ..................................... 30 Thermal Resistance ...................................................................... 7 Pattern Control Mode, PDM Interface .................................... 31 ESD Caution .................................................................................. 7 Register Summary .......................................................................... 32 Pin Configuration and Function Descriptions ............................. 8 Register Details ............................................................................... 33 Typical Performance Characteristics ............................................. 9 Power Control Register.............................................................. 33 Theory of Operation ...................................................................... 15 Amp and Sense Control Register ............................................. 34 Modes of Operation ................................................................... 15 DAC Control Register................................................................ 35 Clocking ....................................................................................... 15 DAC Volume Control Register ................................................. 36 Power Supplies ............................................................................ 15 Serial Audio Interface Control 1 Register ............................... 37 Power Control ............................................................................. 15 Serial Audio Interface Control 2 Register ............................... 38 Power-On Reset/Voltage Supervisor ....................................... 15 Serial Audio Interface Placement 1 Control Register ............ 39 PDM Mode Setup and Control ................................................. 15 Serial Audio Interface Placement 2 Control Register ............ 40 PDM Pattern Control ................................................................. 16 Serial Audio Interface Placement 3 Control Register ............ 41 PDM Channel Selection ............................................................ 17 Serial Audio Interface Placement 4 Control Register ............ 42 PCM Mode Pin Setup and Control .......................................... 17 Serial Audio Interface Placement 5 Control Register ............ 43 PCM Digital Audio Serial interface ......................................... 17 Serial Audio Interface Placement 6 Control Register ............ 43 Serial Data Placement ................................................................ 17 Battery Voltage Output Register ............................................... 44 Stereo (I S/Left Justified) Operating Mode ............................. 19 Limiter Control 1 Register ........................................................ 44 Right Justified Data .................................................................... 19 Limiter Control 2 Register ........................................................ 45 TDM Operating Mode ............................................................... 19 Limiter Control 3 Register ........................................................ 46 Multichip I2S Operating Mode ................................................. 20 Status 1 Register .......................................................................... 47 System Gain ................................................................................. 20 Status 2 Register .......................................................................... 47 Output Current Sensing ............................................................ 21 Fault Control Register................................................................ 48 Output Voltage Sensing ............................................................. 21 PDM Control Register ............................................................... 49 VBAT Sensing ............................................................................. 21 MCLK Ratio Setting Register ................................................... 49 Limiter and Battery Tracking Threshold Control .................. 21 Boost Control 1 Register ........................................................... 50 I C Control .................................................................................. 22 Boost Control 2 Register ........................................................... 51 TDM Control Interface.............................................................. 24 Soft Reset Register ...................................................................... 51 Standalone Mode Control ......................................................... 24 Outline Dimensions ....................................................................... 52 EMI Noise .................................................................................... 24 Ordering Guide .......................................................................... 52 2 2 Output Modulation Description .............................................. 24 Rev. 0| Page 2 of 52 SSM4567 Data Sheet REVISION HISTORY 4/14--Revision 0: Initial Version Rev. 0 | Page 3 of 52 SSM4567 Data Sheet GENERAL DESCRIPTION The SSM4567 is a digital input Class-D power amplifier that includes an integrated boost converter, allowing higher output power than with a normal battery supply. This means that maximum output power is constant across the battery voltage range. The SSM4567 is ideal for power sensitive applications where system noise can corrupt the small analog signal sent to the amplifier, such as mobile phones, tablets, and portable media players. The SSM4567 combines an audio digital-to-analog converter (DAC), a power amplifier, and PDM or PCM (I2S/TDM) digital audio interfaces on a single chip. Using the SSM4567, audio can be transmitted digitally to the audio amplifier, significantly reducing the effect of noise sources on the transmitted audio and eliminate the need for input coupling capacitors. The SSM4567 is capable of delivering 2.5 W of continuous output power with <1% THD + N driving a 4 load from a 3.6 V supply. The SSM4567 can be controlled by I2C, PDM pattern control, or TDM control. It can also operate in standalone mode without a control interface. The SSM4567 includes circuitry to sense output current, output voltage, and the VBAT supply voltage. Current sensing is performed using an on-chip sense resistor that is connected between an output pin and the load. Output current and voltage are sent to an ADC. The outputs of these ADCs are available on the digital serial output port. The VBAT supply voltage can be used with an automatic gain control circuit that is fully configurable. This AGC can limit the maximum output at low battery voltages to avoid drawing too much current from the battery, thereby extending battery life. The SSM4567 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The closed-loop, five-level modulator design retains the benefits of an all digital amplifier, yet enables very good PSRR and audio performance. The modulation continues to provide high efficiency even at low output power and has an SNR of 104 dB, A-weighted. Spread spectrum pulse density modulation is used to provide lower EMI radiated emissions compared with other Class-D architectures. The SSM4567 has a micropower shutdown mode with a typical shutdown current of 0.2 A for the VBAT power supply. Shutdown is enabled automatically by gating input clock and data signals. The SSM4567 is specified over the industrial temperature range of -40C to +85C. It has a built-in thermal shutdown and amplifier and boost output short-circuit protection. It is available in a 19-ball, 1.74 mm x 2.1 mm wafer level chip scale package (WLCSP). Rev. 0| Page 4 of 52 SSM4567 Data Sheet SPECIFICATIONS VBAT = 3.6 V, IOVDD = 1.8 V, TA = 25C, RL = 8 + 33 H, VBST = 5.1 V, 20 Hz to 20 kHz bandwidth (BW), unless otherwise noted. In PDM operation, PDM clock = 3.072 MHz; for PCM operation, fS = 48 kHz. Table 1. Parameter AMPLIFIER CHARACTERISTICS Output Power/Channel System Efficiency Total Harmonic Distortion + Noise Output Voltage Noise Signal-to-Noise Ratio Average Switching Frequency Full-Scale Output Voltage Differential Output Offset Voltage POWER SUPPLIES Supply Voltage Range Power Supply Rejection Ratio Quiescent Supply Current VBAT IOVDD Shutdown Current VBAT IOVDD SHUTDOWN CONTROL Turn-On Time Turn-Off Time Output Impedance CLOCKING AND SAMPLE RATES Input and Output Sampling Rate, PCM BCLK Frequency, PCM Input Sampling Rate, PDM Output Sampling Rate, PDM OUTPUT SENSING Voltage Sense Signal-toNoise Ratio Voltage Sense Full Scale Voltage Sense Absolute Accuracy Voltage Sense Gain Drift Current Sense Signal-to-Noise Ratio Current Sense Input Full-Scale Voltage Symbol Conditions POUT RL = 8 , THD = 1%, f = 1 kHz, RL = 8 , THD = 10%, f = 1 kHz RL = 4 , THD = 1%, f = 1 kHz RL = 4 , THD = 10%, f = 1 kHz PO = 1 W, VBAT = 3.6 V, RL = 8 f = 1 kHz, PO = 1 W, RL = 8 1.43 1.81 2.49 3.17 89.7 0.031 W W W W % % f = 1 kHz, PO = 0.5 W, RL = 8 VBST = 5.1 V, 20 kHz BW, dither input, A-weighted A-weighted, referred to output at 1% THD 0.025 21.7 104 300 5.17 1.1 % V rms dB kHz V peak mV THD + N en SNR fSW Min 0 dBFS PCM or -6 dBFS PDM input VOOS 2.5 1.62 Typ VBAT IOVDD DC PSRR PSRRGSM Dither input Dither input, VRIPPLE = 100 mV on VBAT at 217 Hz 3.6 1.8 70 90 IVBAT IVDD VBAT = 3.6 V IOVDD = 1.8 V, PDM clock = 3.072 MHz 4.86 1.28 IVBAT IVDD VBAT = 3.6 V, no input clocks IOVDD = 1.8 V, no input clocks 0.2 2.8 tWU tSD ZOUT fS Max 5.2 1.98 fBCLK fDAC_PDM_CLK fSNS_PDM_CLK V V dB dB mA mA 1 3 10 86 LRCLK rate Unit A A ms s k 8 192 kHz 2.048 2.048 1.024 24.576 6.144 6.144 MHz MHz MHz SNRV A-weighted 77 dB VFS Output voltage at 0 dBFS PCM/-6 dBFS PDM output from ADC 6 V peak 1.5 % Temperature, TA = 10C to 60C A-weighted 1 72 % dB Voltage across sense resistor with 0 dBFS PCM/ -6 dBFS PDM output from ADC 1.78 A peak SNRI IFS Rev. 0 | Page 5 of 52 SSM4567 Parameter Current Sense Absolute Accuracy Current Sense Gain Drift VBAT Sense Full-Scale Range VBAT Sense Absolute Accuracy Current and Voltage Sense Linearity BOOST CONVERTER Output Voltage Input Current Limit Soft Start Current Limit Line Regulation Load Regulation Inductor Input Capacitor Output Capacitor PMOS Switch Resistance NMOS Switch Resistance Switching Frequency Efficiency AUTOMATIC GAIN CONTROL AGC Gain Attack Time AGC Gain Release Time Battery Inflection Point VBAT vs. Limiter Slope AGC Gain Step Size Data Sheet Symbol Conditions Min TA = 10C to 60C Typ 1.5 Max 1.5 2 6 % V % 1 dB 3 From -80 dBr to 0 dBr VOUT IMAX 1 10 10 RONP RONN fBOOSTSW BOOST VBAT = 3.6 V, VBST = 5.1 V VBAT = 3.6 V, VBST = 5.1 V 200 mA output VBAT supply when threshold reduction starts 20 0.8 3.2 1 5.1 2.2 0.25 0.20 0.15 2.2 V A A %/V %/A H F F m m MHz % 22 80 55 1.536 91 1.6 3.5 3 0.1875 Unit % 120 3.2 3.9 4 s/dB sec/dB V V/V dB DIGITAL INPUT/OUTPUT Table 2. Parameter INPUT VOLTAGE High Low ADDR INPUT LEAKAGE High Low INPUT CAPACITANCE OUTPUT DRIVE STRENGTH Symbol Min VIH VIL 0.7 x IOVDD -0.3 -0.3 Typ IIH IIL 4.5 Rev. 0| Page 6 of 52 Max Unit 3.6 +0.3 x IOVDD IOVDD + 0.3 V V V 1 1 5 A A pF mA Data Sheet SSM4567 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. JA (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. JA is determined according to JESD51-9 on a 4-layer printed circuit board (PCB) with natural convection cooling. For more information, see the AN-617 Application Note, Wafer Level Chip Scale Package at www.analog.com. Parameter VBAT Supply Voltage IOVDD Supply Voltage Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Soldering Conditions Rating -0.3 V to +6 V -0.3 V to +2 V -0.3 V to +6 V -65C to +150C -40C to +85C -65C to +165C JEDEC J-STD-020 Table 4. Thermal Resistance Package Type 19-Ball, 1.74 mm x 2.1 mm WLCSP Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0| Page 7 of 52 JA 57.73 Unit C/W SSM4567 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 A IOVDD AGND PGND BSTSW B LR_SEL/ ADDR SEL SNS_PDM_CLK/ FSYNC BSTSW C DAC_PDM_CLK/ BCLK SNS_PDM_DAT/ SNS_SDATAO VBST VBST D DAC_PDM_D AT/ DAC_SDATAI PGND OUTN E SCL VBAT SDA OUTP 12278-002 BALL A1 INDICATOR Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D3 D4 E1 E2 E3 E4 Mnemonic IOVDD AGND PGND BSTSW LR_SEL/ADDR SEL SNS_PDM_CLK/FSYNC BSTSW DAC_PDM_CLK/BCLK SNS_PDM_DAT/SNS_SDATAO VBST VBST DAC_PDM_DAT/DAC_SDATAI PGND OUTN SCL OUTP VBAT SDA Description I/O and Digital Power Analog Ground Power Amplifier Ground Boost Switch Left or Right Selection for PDM Input/I2C Address PDM or I2S/TDM Interface Mode Select PDM Output Clock for Sense Data in PDM Mode/Frame Synchronization Clock in I2S/TDM Mode Boost Switch PDM Input Clock in PDM Mode/Bit Clock in I2S/TDM Mode Sense Data Output for PDM Mode/Sense Data Output for I2S/TDM Mode Boost Converter Output Boost Converter Output PDM Data Input for DAC in PDM Mode/Serial Data Input for DAC in I2S/TDM Mode Power Amplifier Ground Inverting Class-D Amplifier Output I2C Clock Signal Noninverting Class-D Amplifier Output External Battery Power Supply I2C Data Signal Rev. 0| Page 8 of 52 Data Sheet SSM4567 TYPICAL PERFORMANCE CHARACTERISTICS 100 VDD VDD VDD VDD VDD 10 10 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W THD + N (%) THD + N (%) 1 1 0.1 0.1 0.01 0.0001 0.001 0.01 0.1 1 0.001 10 12278-103 0.001 0.00001 10 OUTPUT POWER (W) 10 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 100k POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W 1 THD + N (%) THD + N (%) 10k Figure 6. THD + N vs. Frequency at VBAT = 4.2 V, RL = 8 and 33 H 100 10 1k FREQUENCY (Hz) Figure 3. THD + N vs. Output Power at RL = 8 and 33 H VDD VDD VDD VDD VDD 100 12278-106 0.01 1 0.1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 10 12278-104 100k 10 POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W 1 THD + N (%) THD + N (%) 10k Figure 7. THD + N vs. Frequency at VBAT = 3.6 V, RL = 8 and 33 H 1 0.1 0.01 0.1 0.01 100 1k 10k 100k FREQUENCY (Hz) 12278-105 0.001 10 1k FREQUENCY (Hz) Figure 4. THD + N vs. Output Power at RL = 4 and 15 H 10 100 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 5. THD + N vs. Frequency at VBAT = 5 V, RL = 8 and 33 H Figure 8. THD + N vs. Frequency at VBAT = 2.5 V, RL = 8 and 33 H Rev. 0| Page 9 of 52 12278-108 0.001 0.00001 12278-107 0.01 SSM4567 10 POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W 1 THD + N (%) THD + N (%) 1 0.1 1k 10k 100k 0.001 10 12278-109 100 FREQUENCY (Hz) 1k 10k 100k Figure 12. THD + N vs. Frequency at VBAT = 2.5 V, RL = 4 and 15 H 8 POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W 8 + 33mH NO LOAD QUIESCENT CURRENT (mA) 7 1 THD + N (%) 100 FREQUENCY (Hz) Figure 9. THD + N vs. Frequency at VBAT = 5 V, RL = 4 and 15 H 10 0.1 0.01 0.01 0.001 10 POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W 12278-112 10 Data Sheet 0.1 0.01 6 5 4 3 2 100 1k 10k 100k FREQUENCY (Hz) 0 2.5 12278-110 0.001 10 2.5 2.0 OUTPUT POWER (W) 1 THD + N (%) 4.0 4.5 5.0 5.5 Figure 13. Quiescent Current vs. VBAT Supply Voltage POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W 0.1 3.5 VBAT (V) Figure 10. THD + N vs. Frequency at VBAT = 4.2 V, RL = 4 and 15 H 10 3.0 12278-113 1 2.5V 3.0V 3.6V 4.2V 5.0V 1.5 1.0 0.01 100 1k FREQUENCY (Hz) 10k 100k Figure 11. THD + N vs. Frequency at VBAT = 3.6 V, RL = 4 and 15 H Rev. 0| Page 10 of 52 0 200 2000 20000 FREQUENCY (Hz) Figure 14. Output Power vs. Frequency at RL = 8 , THD + N = 1% 12278-114 0.001 10 12278-111 0.5 Data Sheet SSM4567 100 4.5 2.5V 3.0V 3.6V 4.2V 5.0V 4.0 80 70 3.0 EFFICIENCY (%) 2.5 2.0 1.5 60 50 40 30 1.0 VBAT VBAT VBAT VBAT VBAT 20 0.5 10 2k 20k FREQUENCY (Hz) 0 12278-115 0 200 0 200 400 600 800 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 1000 1200 LOAD CURRENT (mA) Figure 15. Output Power vs. Frequency at RL = 4 , THD + N = 1% 12278-118 POWER OUTPUT (W) 3.5 90 Figure 18. Boost Efficiency vs. Output Current, Boost Inductor = 2.2 H at 3.072 MHz 4.0 100 90 3.5 60 50 40 30 10 0 0 0.5 1.0 1.5 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 2.0 OUTPUT POWER ( W) 2.5 2.0 1.5 Figure 16. Efficiency vs. Output Power, Boost Inductor = 2.2 H, RL = 8 and 33 H 0 2.5 = 3.7V = 3.5V = 3.3V = 3.7V = 3.5V = 3.3V 4.5 5.0 Figure 19. Output Voltage vs. VBAT Supply Voltage, Limiter Threshold = 5.4 V 4 90 OUTPUT VOLTAGE (V rms) 80 70 60 50 40 30 VBAT VBAT VBAT VBAT VBAT 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 3.5 OUTPUT POWER (W) 12278-117 EFFICIENCY (%) 4.0 3.5 3.0 VBAT_INF VBAT_INF VBAT_INF VBAT_INF VBAT_INF VBAT_INF VBAT (V) 100 0 SLOPE = 2V/V, SLOPE = 2V/V, SLOPE = 2V/V, SLOPE = 3V/V, SLOPE = 3V/V, SLOPE = 3V/V, 1.0 0.5 12278-116 VBAT VBAT VBAT VBAT VBAT 20 3.0 Figure 17. Efficiency vs. Output Power, Boost Inductor = 2.2 H, RL = 4 and 15 H 2 2.5V 2.7V 2.9V 3.1V 3.3V 3.5V 3.7V 3.9V 4.1V 1 0.5 -20 -15 -10 INPUT AMPLITUDE (dBFS) Figure 20. Output Voltage vs. Input Amplitude Rev. 0| Page 11 of 52 -5 12278-120 EFFICIENCY (%) 70 12278-119 OUTPUT VOLTAGE (V rms) 80 SSM4567 -10 -20 0.7 2.5V 3.0V 3.6V 4.2V 5.0V 0.5 LINEARITY (dB) -30 PSRR (dB) VBAT VBAT VBAT VBAT VBAT 0.6 -40 -50 -60 -70 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 0.4 0.3 0.2 0.1 0 -80 -0.1 -90 1k 10k FREQUENCY (Hz) -0.2 -60 12278-121 -100 100 -50 -40 -30 -20 -10 0 INPUT (dBFS) Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency, RL = 8 12278-124 0 Data Sheet Figure 24. Linearity of the Current Sense vs. Input Level, RL = 8 and 33 H 5.0 0 2.5V 3.6V 5.0V -20 VBAT SENSE OUTPUT (V) OUPUT SPECTRUM (dBV) 4.5 -40 -60 -80 -100 4.0 3.5 3.0 20 200 2000 20000 FREQUENCY (Hz) 2.5 2.5 12278-122 -140 Figure 22. Output Spectrum vs. Frequency (FFT), Output Power = 100 mW, RL = 8 , 1 kHz input 4.5 4.0 5.0 VBAT (V) Figure 25. VBAT ADC Sense Level Output vs. VBAT Supply Voltage, RL = 8 100 0.08 VBAT VBAT VBAT VBAT VBAT 0.06 0.04 VBAT VBAT VBAT VBAT VBAT = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 10 0.02 THD + N (%) LINEARITY (dB) 3.5 3.0 12278-125 -120 0 -0.02 1 -0.04 0.1 -0.06 -50 -40 -30 INPUT (dBFS ) -20 -10 0 0.01 0.00001 12278-123 -0.10 -60 Figure 23. Linearity of the Voltage Sense vs. Input Level, RL = 8 and 33 H 0.0001 0.001 0.01 0.1 OUTPUT POWER (W) 1 10 12278-126 -0.08 Figure 26. Current Sense THD + N vs. Output Power, RL = 8 and 33 H Rev. 0| Page 12 of 52 Data Sheet SSM4567 10 100 VBAT VBAT VBAT VBAT VBAT = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 1 THD + N (%) 1 0.1 0.0001 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 10 12278-127 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 1 THD + N (%) THD + N (%) 0.001 0.01 0.1 1 10 0.1 0.001 10 12278-128 0.0001 OUTPUT POWER (W) VBAT VBAT VBAT VBAT VBAT 100 1k 10k 100k FREQUENCY (Hz) Figure 28. Current Sense THD + N vs. Output Power, RL = 4 and 15 H Figure 31. Current Sense THD + N vs. Frequency, VBAT = 3.6 V, RL = 8 and 33 H 10 = 2.5V = 3.0V = 3.6V = 4.2V = 5.0V 10 1 THD + N (%) THD + N (%) POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W 0.01 0.1 1 0.1 POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W 0.1 0.01 0.0001 0.001 0.01 0.1 OUTPUT POWER (W) 1 10 0.001 10 12278-129 0.01 0.00001 100k 10 VBAT VBAT VBAT VBAT VBAT 1 100 10k Figure 30. Voltage Sense THD + N vs. Frequency, VBAT = 3.6 V, RL = 8 and 33 H 10 0.01 0.00001 1k FREQUENCY (Hz) Figure 27. Voltage Sense THD + N vs. Output Power, RL = 8 and 33 H 100 100 12278-131 0.01 0.00001 12278-130 0.01 0.1 100 1k 10k 100k FREQUENCY (Hz) Figure 29. Voltage Sense THD + N vs. Output Power, RL = 4 and 15 H Rev. 0| Page 13 of 52 Figure 32. Voltage Sense THD + N vs. Frequency, VBAT = 3.6 V, RL = 4 and 15 H 12278-132 THD + N (%) 10 POUT = 50mW POUT = 250mW POUT = 500mW POUT = 1W SSM4567 Data Sheet 0 10 ISENSE VSENSE OUTPUT SPECTRUM (dBV) -20 0.1 0.01 -40 -60 -80 -100 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 33. Current Sense THD + N vs. Frequency, VBAT = 3. 6 V, RL = 4 and 15 H -140 20 200 2k FREQUENCY (Hz) Figure 34. Output Spectrum of Sense ADC vs. Frequency Output Power = 100 mW, RL = 8 Rev. 0| Page 14 of 52 20k 12278-134 -120 12278-133 THD + N (%) 1 POUT = 250mW POUT = 500mW POUT = 1W POUT = 1.4W Data Sheet SSM4567 THEORY OF OPERATION MODES OF OPERATION The SSM4567 has several modes of control and audio I/O operation. Audio and sense data can be sent to and from the SSM4567 in 1-bit PDM format by tying the SEL pin to AGND or multibit PCM format by tying the SEL pin to IOVDD. With PCM data, the serial audio interface can be configured for I2S, left justified, or TDM formatting. The SSM4567 can be controlled using I2C, PDM pattern control, TDM control, or standalone operation. See Table 10 for more details. CLOCKING The SSM4567 requires a clock present at the DAC_PDM_CLK/ BCLK input pin to operate. This clock must be fully synchronous with the incoming digital data. The clock frequencies must fall in the range of 2.048 MHz to 24.576 MHz for PCM mode, or 2.048 MHz to 6.144 MHz for PDM mode. In standalone I2S mode, the required clock must be present on the SNS_PDM_CLK/FSYNC pin. POWER SUPPLIES The SSM4567 requires two power supplies: VBAT and IOVDD. VBAT VBAT supplies power to the boost converter and its associated drive, control, and protection circuitry. VBAT can operate from 2.5 V to 5.2 V and must be present to obtain audio output. IOVDD IOVDD provides power to the digital logic circuitry and the I/O drive circuitry. IOVDD can operate from 1.62 V to 1.98 V and must be present to obtain audio output. Power Sequencing On device power-up, VBAT must be applied to the device first. The timing of the IOVDD following VBAT is not important. See the Power-On Reset/Voltage Supervisor section for more details. POWER CONTROL The SSM4567 can be powered down by several methods. If using I2C or TDM control, a software power-down control SPWDN fully powers down the device. PDM pattern control has a standby pattern that powers down all blocks except the PDM interface. For lowest power shutdown, the SSM4567 also contains a clock loss detection circuit that looks at the DAC_PDM_CLK/BCLK input clock. When DAC_PDM_CLK/BCLK is absent, the device automatically powers down all internal circuitry to its lowest power state. When DAC_PDM_CLK/BCLK returns, the device automatically powers up following its usual power sequence. There is an optional automatic power-down feature in which the device enters a lower power state after 2048 consecutive zero input samples have been received when in PCM operation. Only the I2C and digital audio input blocks remain active. The output current, output voltage, and VBAT sensing can be turned off independently via the ISNS_PWDN, VSNS_PWDN, and BSNS_PWDN control bits. This can save power if the amplifier operation is needed but not the output sensing. The amplifier and boost converter can be powered down independently via the AMP_PWDN and BOOST_PWDN control bits. When the boost is powered down and the amplifier is still active, the amplifier runs directly from the VBAT supply. This same VBAT only operation can be entered with the boost still active with the VBAT_ONLY bit. The amplifier can be powered down with the boost still enabled so the boost output can be used for other functions. POWER-ON RESET/VOLTAGE SUPERVISOR The SSM4567 includes an internal power-on reset and voltage supervisor circuit. This circuit provides an internal reset to all circuitry whenever VBAT or IOVDD is substantially below the nominal operating threshold. This simplifies supply sequencing during initial power-on. The circuit also monitors the power supplies to the IC. If the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. This ensures that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. PDM MODE SETUP AND CONTROL The SSM4567 can operate using 1-bit PDM data for both its input and for the sense outputs. In PDM mode, control can be done either by PDM control patterns or with I2C. If the SEL pin is tied to AGND, the SSM4567 starts up and operate in PDM pattern control mode. The SSM4567 can also operate in PDM via I2C control mode. A regular I2C operating address can be set on the LR_SEL/ADDR pin. Then, using I2C, the device can be set into PDM mode by writing a 1 to the PDM_MODE control bit. The PDM_LR_SEL bit selects which input channel is used. In PDM operating mode mode, the 1-bit PDM input to the DAC is received on the DAC_PDM_DAT/DAC_SDATAI pin. The DAC_PDM_CLK/BCLK pin provides the system clock and is used for clocking in the input data. Output voltage and current sense are output on the SNS_PDM_DAT/SNS_SDATAO pin. The output can be sent at a different rate from the input, and the SNS_PDM_CLK/FSYNC pin determines the sense output rate. Alternatively, the output rate can be sent at the same rate as the input and only one clock pin, DAC_PDM_CLK/BCLK, is needed to operate the device. To use only one clock, set the SHARED_CLOCK register to 1. Full-scale voltage for both the input and output is mapped to -6 dBFS on the PDM stream. The PDM data input is registered directly on each clock edge. The data transition on the PDM data output is delayed relative to the clock edge. Rev. 0| Page 15 of 52 SSM4567 Data Sheet Table 6. PDM Timing Parameters Parameter tFALL tRISE tSETUP tHOLD Limit tMIN tMAX 10 10 10 7 Unit ns ns ns ns Any pattern must be repeated a minimum of 128 times. The device is automatically muted when a pattern is detected so that a pattern can be set while the device is operational without a pop/click due to pattern transition. After this minimum repetition is complete, the pattern can be removed at any time and the device resumes normal operation. Description Clock fall time Clock rise time Data setup time Data hold time All patterns except mute and power-down are sticky, in that after the pattern is sent the functionality of the pattern remains after the pattern is removed. Mute and power-down are active only when their respective patterns are being continuously written. BCLK tHOLD tSETUP L DATA R DATA L DATA 12278-008 DAC_SDATAI R DATA Figure 35. PDM Input Data Format The PDM data is output on both edges of the clock. The current sense ADC data is output when SNS_PDM_CLK/FSYNC is high and should be read on the falling edge. The voltage sense ADC data is output when SNS_PDM_CLK/FSYNC is low and should be read on the rising edge. BCLK SDATA I V I V I V I V I V I V 12278-009 FSYNC I Figure 36. SDATA (DAC_SDATAI/SNS_SDATAO) Output in PDM Mode By default in PDM mode, PDM pattern control is used for control information. I2C control can be used instead, but do not use both at the same time. If PDM pattern control is engaged, then registers associated with the PDM pattern control do not function using I2C. Writes to those registers are ignored and reads do not reflect the current state of the device. For I2C control, it is best to tie the SEL pin to IOVDD and then set the PAT_CTRL_EN bit to 0 to disable PDM pattern control before any other I2C writes or reads are performed. By default, the I2C device address in PDM mode is 0x34. By setting the I2C_ADDR_SET bit, the device address can be either 0x34 or 0x35, depending on the state of the LR_SEL/ADDR pin. All functionality set via patterns return to its default values after a clock loss power-down or after the device reset pattern is sent. Table 7. PDM Watermarking Pattern Control Descriptions Pattern 0xD2 0xD4 0xD8 0xE1 0xE2 0xE4 0xAA 0x66 0xAC 0xF1 0xF2 0xF4 0xC1 PDM PATTERN CONTROL PDM mode operation has a simple control mechanism that can set the device for low power states and control functionality. This is accomplished by sending a repeating 8-bit pattern to the device. Different patterns set different functionalities. 0xC2 Rev. 0| Page 16 of 52 Control Description Limiter: enable. Lower gain mode (3.6 V) with -6 dBFS). Shared clock operation. Only DAC_PDM_CLK is needed. Ultralow EMI mode. Low latency mode with pattern delay (~15 s latency). Set DAC to low power mode = off. PDM_CLK = 128 x fS mode. Device reset: place the device into default configuration Mute. Power-down: all blocks off except for PDM interface. Normal start-up time. Limiter: 3.7 V battery inflection point. Limiter: 3.3 V battery inflection point. Limiter: 2 V/V VBAT vs. the limiter slope. Sense power-up/power-down toggle. Limiter: threshold value set to 5.4 V peak. Register Setting LIM_EN = 01 ANA_GAIN = 0 SHARED_CLOCK = 1 Edges = 1 LOW_LATENCY = 01 DAC_LPM = 0 DAC_MUTE = 1 SPWDN = 1 VBAT_INF = 010 VBAT_INF = 110 Slope = 01 Toggle value of BSNS_PWDN, ISNS_PWDN, and VSNS_PTWN LIM_THRES = 0110 Data Sheet SSM4567 PDM CHANNEL SELECTION The SSM4567 includes a left/right input select pin, LR_SEL/ADDR (see Table 24) that determines which of the time-multiplexed input streams is routed to the amplifier when using PDM pattern control mode. To select the left input channel, connect LR_SEL/ADDR pin to AGND. To select right channel data, connect LR_SEL/ADDR pin to IOVDD. At any point during amplifier operation, the logic level applied to LR_SEL/ADDR pin can be changed and the output switches between input streams without audible artifacts. Aside from logic level selection from the user, no muting, watermarking pattern, or synchronizing is necessary to achieve a click/pop free LR_SEL/ADDR transition. Table 8. LR_SEL/ADDR Function Descriptions Device Setting Right Channel Select LR_SEL/ADDR Pin Configuration IOVDD Left Channel Select GND PCM MODE PIN SETUP AND CONTROL When the SEL pin is tied to IOVDD, the SSM4567 is set for PCM mode operation. In this mode, the SSM4567 supports standalone operation, I2C control, or can be controlled using commands sent over the input serial audio/TDM interface. When the LR_SEL/ADDR pin is pulled up via a 47 k resistor, the IC operates in standalone mode with most registers set to their default states. The state of the several pins can change the functionality of other pins. The LR_SEL/ADDR pin determines the I2C device address. In standalone and TDM control modes, the SCL and SDA pins are used to determine the TDM slot used. See Table 10 for details. PCM DIGITAL AUDIO SERIAL INTERFACE The SSM4567 includes a standard serial audio interface that is slave only. The interface is capable of receiving and transmitting I2S, left justified, PCM, or TDM formatted data. There is an input interface for sending audio to the amplifier and an output interface for the sense data. These interfaces share the same FSYNC and BCLK signals. A BCLK signal must be provided to the SSM4567 for correct operation. The BCLK signal must have a minimum frequency of 2 MHz. The BCLK signal is used for internal clocking of the device. The BCLK rate is automatically detected, but the sampling frequency must be known to the device. The BCLK rates at 32 kHz to 48 kHz that are supported are 50, 64, 100, 128, 192, 200, 256, 384, 400, and 512 times the sample rate. The serial interfaces have three main operating modes. Stereo mode, typically I2S or left justified, is used when there is a single chip on the interface bus. TDM mode is more flexible and offers the ability to have multiple chips on the bus. The third operating mode is multichip I2S mode, which uses standard I2S formatting but allows multiple chips to use the bus. It is also possible to use the serial interfaces for bidirectional control information. When this is done, the internal control registers are accessed via the serial audio interface and not from I2C. These mode selections can be set via the I2C interface with the SAI_MODE and MC_I2S bits. Alternatively, in standalone mode or when AUTO_SAI is set to 1, the interface can autoconfigure based on how the signals are connected to the clock pins and the FSYNC type (pulse or 50% duty cycle). When in standalone or automatic configuration modes, an I2S interface format can be selected by swapping the pin connections for the BCLK and FSYNC signals (with the I2S LRCLK signal connected to the DAC/PDM_CLK/BCLK pin and BCLK signal connected to the SNS_PDM_CLK/FSYNC pin). When the BCLK and FSYNC signals are connected to their respective pins, and the FYSNC signal is a single BCLK cycle pulse, TDM mode is selected. When the BCLK and FSYNC signals are connected to their respective pins, and the FYSNC signal is a 50% duty cycle signal, multichip I2S mode is selected. On the SNS_PDM_DAT/SNS_SDATAO pin, unused cycles can either be driven or set to high-Z. This is determined by the SAI_DRV control bit. If multiple chips are used on the serial interface bus, then SAI_DRV must be set to 0 so that unused cycles are not driven. SERIAL DATA PLACEMENT The SSM4567 is flexible in where within a frame it places output data and where it looks for input data. There are four control bits for when input data is expected (Px_DAC) and and six control bits for when output data is driven (Px_SNS). A single data frame is broken up into individual fields, referred to as placements. Each placement can be 8 bits, 16 bits, or 24 bits in length. A single frame on the TDM or I2S data stream can contain several data placements of varying length. When the serial port is operating in TDM mode, placements start directly after the FSYNC pulse. The first placement is referred to as P1, the second placement is referred to as P2, and so on, increasing sequentially. These placements appear in sequential order on the serial data signal. Up to four placements can be on the input stream and up to six placements can be on the output stream. Figure 37 shows a basic timing diagram of the placements in TDM mode. When the serial port is operating in I2S mode, placements start directly after the FSYNC falling clock edge, signalling the beginning of a new frame. The first placement is referred to as P1, the second placement is referred to as P2, and so on, increasing sequentially. The odd-numbered placements (P1, P3, and P5) appear sequentially in the left channel, when the FSYNC signal is low (assuming FSYNC_MODE = 0), and the even-numbered placements (P2, P4, and P6) appear sequentially in the right channel, when the FSYNC signal is high (assuming that FSYNC_MODE = 0. Up to four placements can be on the input stream and up to six placements can be on the output stream. Rev. 0| Page 17 of 52 SSM4567 Data Sheet Figure 38 shows a basic timing diagram of the placements in I2S mode. The corresponding registers allow configuration of each data placement. An input placement (Px_DAC) can carry 24-bit audio data, 16-bit audio data, or eight zero bits that are used as padding and ignored. See the Right Justified Data section for more information about using the 8 zero bits settings. A sense placement (Px_SNS) can contain 16-bit voltage output data, 16-bit current output data, 8-bit battery voltage data, 8-bit control data, alternating 16-bit voltage and current data, 8-bit status data, 8-bit V/I marker and slot ID data, or 8 zero bits. For standard I2S mode, the serial input is configured to receive mono audio data, and the serial output is configured to send voltage, current, and battery data back to the host device. The corresponding registers are in Table 9 and the corresponding timing diagram is in Figure 39. Table 9. Standard I2S Data Placement Settings Register Bit Field BCLK_POL FSYNC_MODE SDATA_FMT SAI_MODE MC_I2S P1_DAC P1_SNS P2_SNS P3_SNS Setting 0b0 0b0 0b0 0b0 0b0 0b00 0b000 0b001 0b010 Description Rising edge of BCLK is used to latch data FSYNC low corresponds to left data channel Data MSB is delayed by one bit clock cycle Stereo mode Normal I2S operation 24-bit audio input data is in input Placement P1 16-bit sense voltage is in output Placement P1 16-bit sense current is in output Placement P2 8-bit battery voltage is in Placement P3 Table 10. PCM Modes Pin Setup List Control Mode I2 C Standalone (TDM Interface) Standalone (I2S Interface) TDM TDM Slot 1 2 3 1 2 3 4 N/A N/A N/A N/A N/A 1 2 3 4 Signals Connected To Pins For Modes Listed In The First Three Columns DAC_PDM_CLK/ SNS_PDM_CLK/ LR_SEL/ADDR SCL SDA SEL BCLK FSYNC AGND SCL SDA IOVDD Bit clock Frame sync IOVDD SCL SDA IOVDD Bit clock Frame sync Open SCL SDA IOVDD Bit clock Frame sync 47 k pull-up AGND AGND IOVDD Bit clock Frame sync 47 k pull-up AGND IOVDD IOVDD Bit clock Frame sync 47 k pull-up IOVDD AGND IOVDD Bit clock Frame sync 47 k pull-up IOVDD IOVDD IOVDD Bit clock Frame sync 47 k pull-up Boost power Shutdown IOVDD Frame sync Bit clock down (active (intentional swap (intentional swap (active low) of CLK pins, Pin of CLK pins, Pin B3 low) B3 and Pin C1) and Pin C1) 47 k pull-down AGND AGND IOVDD Bit clock Frame sync 47 k pull-down AGND IOVDD IOVDD Bit clock Frame sync 47 k pull-down IOVDD AGND IOVDD Bit clock Frame sync 47 k pull-down IOVDD IOVDD IOVDD Bit clock Frame sync N/A means not applicable. BCLK FSYNC DAC_SDATAI P1 P2 8 BITS/16 BITS/24 BITS Figure 37. Basic Timing Diagram of Placements in TDM Stream Rev. 0| Page 18 of 52 Px 12278-010 1 I2C Control Address 1 0 (0x34) 1 (0x35) 2 (0x36) N/A N/A N/A N/A N/A Data Sheet SSM4567 BCLK FSYNC P1 P2 P3 P4 12278-011 DAC_SDATAI 8 BITS/16 BITS/24 BITS Figure 38. Basic Timing Diagram of Placements in I2S Stream BCLK FSYNC DAC INPUT DAC_SDATAO VOLTAGE CURRENT BATTERY 16 BCLKs 12278-012 DAC_SDATAI 16 BCLKs 8 BCLKs 2 Figure 39. Standard I S Data Placement Timing Diagram BCLK 32 BCLKS FSYNC 24 DAC DATA 1 DAC DATA 2 16 DAC_SDATAO 16 ISENSE 1 VSENSE 1 ISENSE 2 12278-013 DAC_SDATAI Figure 40. TDM Serial Interface Format STEREO (I2S/LEFT JUSTIFIED) OPERATING MODE Stereo modes use both edges of the FSYNC signal to determine placement of data. Stereo mode is enabled when SAI_MODE = 0 and I2S or left justified is determined by the SDATA_FMT bit setting. In standalone mode or when AUTO_SAI = 1, an I2S output interface can be configured by exchanging the connections to the DAC_PDM_CLK/BCLK and SNS_PDM_CLK/FSYNC pins. The I2S and left justified interface formats accept any number of BCLK cycles per FSYNC cycle. Sample rates from 8 kHz to 192 kHz are accepted. The six placement control registers, SAI_PLACEMENT_x, determine placement of input and output data. Odd numbered placement control registers determine the order on the left channel and even number on the right channel. In the timing diagrams, these placements are refered to as P1 to P6. There are four placements for the incoming DAC data and six placements for the outgoing sense data. RIGHT JUSTIFIED DATA When the audio data in either a TDM or I2S slot placement is right justified, the Px_DAC bits can be used to properly read the data. Each Px_DAC bit has a setting where it reads in eight bits of data. The data is then not used and fulfills the read requirement for that slot so that the subsequent bits are read as the data of the next slot. This continues until a slot is reached that is set to read audio data. For example, for a stereo I2S, 24-bit audio data-word that is right justified with 32 BCLKS for the left channel, set P1_DAC to b10 so that it picks up the first eight bits of zero data. Then, set P2_DAC to b00 so that it picks up the 24-bit audio data. Fo another example, for a stereo I2S 16-bit audio data word that is right justified with 32 BCLKS for the left channel, set P1_DAC to b10 so that it picks up the first eight bits of zero data.Then, set P2_DAC to b10 so that it picks up the next blank 8 bits of data, and set P3_DAC to b01 so it then picks up the 16 bits of audio data. TDM OPERATING MODE TDM operating mode allows multiple chips to use a single serial interface bus. The FSYNC signal on the SNS_PDM_CLK/FSYNC pin operates at the desired sample rate. The rising edge of the FSYNC signal indicates the start of a new frame. For proper operation, this signal must be one BCLK cycle wide, transitioning on a falling BCLK signal edge. The MSB of data is present on the SNS_PDM_DAT/SNS_SDATAO pin one BCLK cycle later. The SNS_PDM_DAT/ SNS_SDATAO signal must be latched on a rising edge of the BCLK signal (see Figure 40). Rev. 0| Page 19 of 52 SSM4567 Data Sheet Each chip on the TDM bus can occupy 32, 48, or 64 BCLK cycles. This is set with the TDM_BCLKS control register and all chips on the bus must have the same setting. Up to eight SSM4567 chips can be used on a single TDM bus, but only three unique I2C device addresses are available. The SSM4567 automatically determines how many possible chips can be placed on the bus from the BCLK rate. There is no limit to the total number of BCLK cycles per FSYNC pulse. In standalone mode, only four slots can be used because there are only four combinations of the SDA and SCL pins to choose from (see Table 10). When not in standlone mode, the slot that each SSM4567 uses is determined either by the LR_SEL/ADDR pin settings or the TDM_SLOT control register. By default, the setting is determined by the state of the LR_SEL/ADDR pin, which allows the first three slots to be selected. However, it can be overridden by the TDM_SLOT control register, which allows eight different slots to be selected. Table 11. TDM Slot Selection Device Setting TDM Chip 1 Slot Used/Driven TDM Chip 2 Slot Used/Driven TDM Chip 3 Slot Used/Driven LR_SEL/ADDR Pin Configuration Tied to AGND Tied to IOVDD Open The six placement control bits determine placement of input and output data within each chip slot. Input data to the DAC, using the DAC_PDM_DAT/DAC_SDATAI pin, can be either 16-bit or 24-bit data or it can be set to read in eight bits and ignore them. This is useful for right justified data formats where the first eight bits of the 32 bit clocks are padded zeros. The first placement register is set to read in eight bits and ignore them. Then the next placement register is set to read in the 24-bit audio data. The output data from the DAC, using the SNS_PDM_DAT/ SNS_SDATAO pin, can be any of the following: * * * * * * * * FSYNC signals are not swapped as they would be for I2S/left justified operation) except the FSYNC signal has a 50% duty cycle. The frequency of the FSYNC signal in relation to the BCLK signal determines if the device is in two-chip or fourchip mode. If the FSYNC signal consists of one BCLK cycle pulse, TDM operating mode is active instead. The multichip I2S interface allows multiple chips to drive a single I2S bus. Each chip takes control of the bus every two or four frames (depending on the number of chips placed on the bus), allowing a maximum of four chips on the bus. Each frame or cycle of the FSYNC signal must 64 BCLK cycles long. The LR_SEL/ADDR pin assignments determine the order of control. Each frame also contains a slot ID code that is appended to the current data in the frame. This code indicates the slot of the chip that sent the data for that frame. The mapping of LR_SEL/ADDR pin assignments to the ID tag when not in standalone mode is shown in Table 12. Table 12. Multichip I2S Slot Configuration in SA Mode ADDR Pin Configuration Tied to AGND Tied to IOVDD Open Slot No. 1 2 3 ID Tag 0001 0010 0100 The device automatically configures for two-chip or four-chip depending on the number of detected chips in the bus. For twochip operation, the first and second slots must be used. Unused slots are allowed; however, Slot 1 must always be used. To enable two-chip operation, the device starts in four-chip operation and, when it is detected that Slot 3 and Slot 4 are unused, it switches to two-chip operation. Table 13 describes the FSYNC and BCLK rates that are supported in multichip I2S mode. Table 13. FSYNC and BCLK Rates For Multichip I2S 16-bit voltage output 16-bit current output 8-bit battery (VBAT) voltage 8-bit control data output Alternating 16-bit voltage and current 8-bit status output 8-bit V/I marker and slot ID Blank eight bits Sample Rate 32 kHz to 48 kHz Valid Slots 1, 2 32 kHz to 48 kHz 1, 2, 3, 4 FSYNC Rate 2 x fS (32 kHz to 96 kHz) 4 x fS (64 kHz to 128 kHz) BCLK Rate 128 x fS (2.048 MHz to 6.144 MHz) 256 x fS (4.096 MHz to 12.288 MHz) SYSTEM GAIN It is possible to have as many as six output placements and four input placements per frame depending on the clock rates. MULTICHIP I2S OPERATING MODE A special multichip I2S mode is enabled by setting the MC_I2S control register (Register 0x05[4]) to 1 when under I2C control. The TDM_SLOT register (Register 0x05[2:0]) sets the slot where data is expected and sense data is transmitted. In standalone mode or when AUTO_SAI = 1, multichip I2S is enabled when the device is wired for TDM mode (that is, the BCLK and The default analog gain of the SSM4567 maps a 0 dBFS input level to 5.1 V peak nominally at the amplifier output. This setting provides optimal gain staging for best noise performance. A lower analog gain setting that maps a 0 dBFS input level to 3.6 V peak can be set via the ANA_GAIN bit, Register 0x01[0]. There is also digital gain/volume control, Register 0x03, that provides fine control in 0.375 dB steps from -71.25 dB to +24 dB. There is one additional step for mute. Rev. 0| Page 20 of 52 Data Sheet SSM4567 OUTPUT CURRENT SENSING The SSM4567 uses an on-chip sense resistor to determine the output current flowing to the load. The voltage across this sense resistor is proportional to the load current and sent to an ADC running nominally at 128 x fs. In PCM mode, the output of this ADC is downsampled using digital filtering. This downsampled signal at an 8 kHz to 192 kHz sample rate is output on the digital audio interface. The data is 16 bits and in signed fraction format. For both current and voltage sensing a sample rate equal to the DAC input is the default setting. A lower sample rate of 1/2, 1/4, or the DAC sample rate can be used. This can be set using the SNS_FS bits, Register 0x01[5:4]. level begins to decrease the output level is determined by the VBAT_INF bits (Register 0x0D[5:3]). The rate at which the threshold is lowered relative to the amount VBAT has lowered below the VBAT_INF point is determined by the slope bits (Register 0x0D[7:6]). The limiter can also be set such that it engage only when the battery voltage is lower than VBAT_INF by setting LIM_EN = 11. When VBAT is above VBAT_INF, no limiting takes place. In this case, there is hysteresis on VBAT_INF for the limiter disengaging. If LIM_EN = 10, when VBAT falls below the VBAT_INF value, the amplifier automatically mutes. In this case, there is hysteresis on VBAT_INF when the mute is disengaged. In PDM mode the sense ADC runs at the PDM clock rate. MAX PEAK OUTPUT VBAT_INF The output voltage level is monitored and sent to an ADC running nominally at 128 x fs. The output of this ADC is then downsampled using digital filtering. This downsampled signal at 8 kHz to 192 kHz sample rate is output on the digital audio interface. The data is 16 bits and in signed fraction format. For both current and voltage sensing, a sample rate equal to the DAC input is the default setting. A lower sample rate of 1/2, 1/4, or the DAC sample rate can be used. This can be set using the SNS_FS bits, Register 0x01[5:4]. LIM_THRES SLOPE In PDM mode, the sense ADC runs at the PDM clock rate. VBAT 12278-014 OUTPUT VOLTAGE SENSING Figure 41. Battery Tracking Limiter Threshold Control VBAT SENSING The LIM_THRES can be set above the maximum output voltage of the amplifier. In this case, the limiter allows maximum peak output, but limits the amount of clipping that can occur. The rate of gain reduction or attack rate and gain increase or release rate is determined by the LIM_ATR bits (Register 0x0E[5:4]) and LIM_RRT bit (Register 0x0E[7:6]), respectively. The SSM4567 can monitor the VBAT supply and automatically adjust the limiter threshold when the VBAT supply is below a selected point when LIM_EN = 01. When using the limiter, it can be selected whether the threshold is fixed or moves with the battery voltage via the VBAT_TRACK bit (Register 0x0D[2]). This function can prevent early shutdown under end-of-charge battery conditions. The VBAT supply voltage at which the limiter Rev. 0| Page 21 of 52 VBAT 12278-015 NO LIMITING Figure 42. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0b1) LIM_EN = 11 VBAT_TRACK = 0 NO LIMITING VBAT 12278-016 The SSM4567 contains an output limiter that can limit the peak output voltage of the amplifier. The threshold at which the output is limited is determined by the LIM_THRES register setting, Register 0x0E[3:0]. The audio signal is not affected by the limiter function unless the peak audio output voltage exceeds the limiter threshold level. MAX PEAK OUTPUT LIMITER AND BATTERY TRACKING THRESHOLD CONTROL LIM_EN = 11 VBAT_TRACK = 1 MAX PEAK OUTPUT The SSM4567 contains an 8-bit ADC that measures the voltage of the VBAT supply in real time. The output of the ADC is in 8-bit unsigned format and is presented on the eight MSBs of the 16 bits in Slot 3 on the TDM bus. The remaining eight LSBs are driven low (see Figure 39). Figure 43. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0) SSM4567 Data Sheet pulse. The device address of the SSM4567 is determined by the state of the LR_SEL/ADDR pin. When the LR_SEL/ADDR pin is pulled to ground, the device address is 0x34. LIM_EN = 01 VBAT_TRACK = 0 12278-017 MAX PEAK OUTPUT This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means the master writes information to the peripheral, whereas a Logic 1 means the master reads information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. The timing for the I2C port is shown in Figure 45. VBAT Figure 44. Limiter Example (LIM_EN = 0b01, VBAT_TRACK = 0) I2C CONTROL The SSM4567 supports a 2-wire, serial, I2C-compatible microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the SSM4567 and the system I2C master controller. The SSM4567 is always a slave on the bus, meaning it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address byte format is shown in Table 14. The address resides in the first seven bits of the I2C write. The LSB of this byte sets either a read or write operation. Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Both SDA and SCL need 2.2 k pull-up resistors for proper operation. Only one set of pull-up resistors are required for the entire I2C bus. The voltage on these signal lines must not be more than 3.3 V. Table 14. I2C Chip Address Byte Format Bit 0 0 Bit 1 1 Bit 2 1 Bit 3 0 Bit 4 1 Bit 5 I2C Addr. MSB Bit 6 I2C Addr. LSB Bit 7 R/W Table 15. I2C Device Address Selection Device Address (7-Bit Format) 0x34 0x35 0x36 Device Address (8-Bit Format) 0x68 0x6A 0x6C LR_SEL/ADDR Pin Configuration Tied to AGND Tied to IOVDD Open Addressing Initially, each device on the I2C bus is in an idle state, monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the SSM4567 immediately jumps to the idle condition. During a given SCL high period, the user must issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the SSM4567 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. In read mode, the SSM4567 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM4567, and the device returns to the idle condition. I2C Read and Write Operations Figure 46 shows the format of a single-word write operation. Every ninth clock, the SSM4567 issues an acknowledge message by pulling SDA low. Figure 47 shows the format of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The SSM4567 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. The timing of a single-word read operation is shown in Figure 48. Note that the first R/W bit is 0, indicating a write operation. This is because the subaddress still must be written to set up the internal address. After the SSM4567 acknowledges the receipt of the subaddress, the master must issue a repeated start command, followed by the chip address byte with the R/W set to 1 (read). This causes the SSM4567 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the SSM4567. Rev. 0| Page 22 of 52 SSM4567 Data Sheet Table 16. List of Abbreviations Used in I2C Timing Figures, Figure 46 to Figure 49 Symbol S P AM AS Meaning Start bit Stop bit Acknowledge by master Acknowledge by slave SCK SDA R/W ACK ACK START BY MASTER FRAME 1 CHIP ADDRESS BYTE FRAME 2 CHIP ADDRESS BYTE SCK (CONTINUED) ACK ACK STOP BY MASTER FRAME 4 DATA BYTE 2 FRAME 3 DATA BYTE 1 12278-018 SDA (CONTINUED) START BIT IC ADDRESS (7 BITS) R/W =0 ACK BY SLAVE SUBADDRESS (8 BITS) ACK BY SLAVE DATA BYTE 1 (8 BITS) STOP BIT 12278-019 Figure 45. I2C Read/Write Timing S CHIP ADDRESS, R/W = 0 AS AS SUBADDRESS AS DATA WORD 1 DATA WORD 2 ... AS P 12278-020 Figure 46. Single-Word I2C Write Format CHIP ADDRESS, R/W = 0 AS SUBADDRESS CHIP ADDRESS, R/W = 1 S AS AS DATA BYTE 1 AM DATA WORD 1 AM DATA BYTE N P 12278-021 S ... P 12278-022 Figure 47. Burst Mode I2C Write Format Figure 48. Single-Word I2C Read Format S CHIP ADDRESS, R/W = 0 AS SUBADDRESS AS CHIP ADDRESS, R/W = 1 S AS Figure 49. Burst Mode I2C Read Format BCLK 64 BCLKS FSYNC 8 DAC_SDATAI DAC_SDATAO 8 5 AUDIO DATA START STOP 16 16 ISENSE VSENSE R/W Figure 50. TDM Control Format Rev. 0 | Page 23 of 52 CONTROL 8 VBAT 8 CONTROL 12278-023 24 SSM4567 Data Sheet STANDALONE MODE CONTROL The SSM4567 supports control data sent over the serial audio interface (SAI). This allows flexible control of the device without requiring an I2C control port connection. Only TDM operation with 64 BCLKs per chip is supported in this mode (see Figure 50). It is not possible to modify any of the SAI control registers in this mode. The placement for DAC inputs, Px_DAC, also cannot be modified. The placements for sense outputs, Px_SNS, can be modified. An 8-bit control data output can be placed on the SNS_PDM_DAT/SNS_SDATAO line via the placement register. This allows reading of control data over the SAI. It is not necessary to use this in SAI control mode. The SSM4567 can be operated without any control interface in standalone mode. This mode is set by pulling up the LR_SEL/ADDR pin to IOVDD with a 47 k resistor. When operating in standalone mode, all control settings are set to their default state except for those listed in Table 19. P1 DAC 24-BIT P2 P3 P4 CONTROL HEADER 8-BIT CONTROL DATA 8-BIT BLANK 12278-024 TDM CONTROL INTERFACE Figure 51. SDATAI Data Placement for SAI Control, TDM with 64-Bit Slot Two bytes, the control header and control data, must be placed in the DAC input stream and one byte, control data, is placed on the output sense stream. BIT 0 BIT 1 0 0 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 0 0 0 START STOP R/W 12278-025 The three LSBs of the control header byte are used to initiate control sequences. They are the start bit indicating the start of a control sequence when set to one, the stop bit indicating the stop of a control sequence when set to one, and the read/write bit, which indicates a read or write sequence when the start bit is also set. Figure 52. SAI Control Header Byte Format The control data sequencing is the same as I2C control, except a device address is not required. The first control data byte sent after the start is the 8-bit subaddress; the subsequent control data bytes are data. Table 17. SAI Control Write Sequence Frame 1 2 3 4 5 Control Header 0x04 0x00 0x00 0x00 0x02 Control DAC_DATAI Subaddress Data 1 Data 2 Data 3 Don't care Control SNS_DATAO 0x00 0x00 0x00 0x00 0x00 Frame 1 2 3 4 5 Control DAC_DATAI Subaddress Don't care Don't care Don't care Don't care SA_MODE Setting 0 1 LIM_EN SDATA_FMT TDM_BCLKS 00 0 10 PDM_MODE b0 Function Normal operation Auto detection of serial audio interface format Disable limiter Normal I2S 64 BCLKs per chip in TDM Disable PDM mode In standalone mode with the interface set to TDM mode, the SDA pin and the SCL pin are used to select the TDM/channel slot. If in I2S mode, the SCL pin can be used to power down boost, and the SDA pin can be used to shut down the whole device (see Table 10). EMI NOISE The SSM4567 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. The SSM4567 can pass FCC Class B emissions testing with unshielded 20-inch cable using ferrite bead-based filtering. For applications that have difficulty passing FCC Class B emission tests, the SSM4567 includes an edge rate control bit, Register 0x01[2] (ultralow EMI emission mode), that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. Note that reducing the supply voltage also greatly reduces radiated emissions. OUTPUT MODULATION DESCRIPTION The SSM4567 uses five-level, - output modulation. Each output can swing from PGND to VBAT or PGND to VBST at any time and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V, because there is no need to generate a pulse. In a real-world situations, there are always noise sources present. Table 18. SAI Control Read Sequence Control Header 0x05 0x00 0x00 0x00 0x02 Table 19. Non Default Register Settings in Standalone Mode Bit Name SPWDN AUTO_SAI Control SNS_DATAO 0x00 Data 1 Data 2 Data 3 0x00 Due to this constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, output differential voltage is 0 V, due to the Analog Devices, Inc., five-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. Rev. 0| Page 24 of 52 Data Sheet SSM4567 When high output is not needed, ensure no efficiency loss due to the extra boost switch by switching off the battery supply. With variable boost methods after high output is no longer needed, the boost remains on for a long time. With five-level modulation, it instantly switches back to using the battery supply, resulting in better real-world power. Figure 53 depicts five-level, - output modulation with input stimulus. +VBST +VBAT 0 12278-026 -VBAT -VBST Figure 53. Five-Level, - Output Modulation INTEGRATED BOOST CONVERTER An integrated boost converter is provided with a nominal switching frequency of 1.536 MHz. The converter is designed to step up the VBAT supply, typically 3.6 V from a single-cell battery, to a higher VOUT voltage of 5.1 V. The output of the boost converter is available at the VBST pins. A 2.2 H inductor is required for proper operation of the boost converter. See the Component Selection for Boost Regulators section for more details on selecting the proper inductor. The boost converter can be powered down via the BOOST_PWDN control bit. When the boost is powered down and the amplifier is still active, the amplifier runs directly off the VBAT supply. This same VBAT only operation can be entered with the boost still active with the VBAT_ONLY bit. The amplifier can be powered down with the boost still enabled so that the boost output can be used for other functions. Rev. 0| Page 25 of 52 SSM4567 Data Sheet APPLICATIONS INFORMATION COMPONENT SELECTION FOR BOOST REGULATORS Inductor Selection The inductor is an essential part of the boost regulator. It stores energy during on time of the low-side power FET in the boost regulator. It is during this time that the input current is at its maximum. The maximum input current must be taken into account to determine the inductor value. The maximum dc input current (that is, the maximum average inductor current) can be estimated by using the following equation: I IN V I LOAD ( MAX ) OUT V IN 1 where 85%. The desired input and output voltages, the switching frequency, and the ripple current determine the required inductor value, as shown in the following equation: V VIN V 1 L OUT IN I RIPPLE f SW VOUT For very low ESR capacitors, such as ceramic capacitors, the ripple current due to the capacitance is calculated as follows. In continuous mode, because the capacitor discharges during the on time (tON), the charge removed from the capacitor (QC) is the load current multiplied by the on time. Therefore, the output voltage ripple (VOUT) is VOUT C OUT I L t ON C OUT where: COUT is the output capacitance. IL is the average inductor current. Using the duty cycle (D) and switching frequency (fSW), users can determine the on time by using the following equation: t ON D f SW The input (VIN) and output (VOUT) voltages determine the switch duty cycle (D) by using the following equation: In general, the ripple current is estimated as 30% of the maximum dc input current (IIN), so the equation can be rewritten as follows: L QC D VOUT VIN VOUT Choose the output capacitor based on the following equation: VOUT V IN V 1 IN 0.3 I IN f SW VOUT C OUT I L (VOUT VIN ) f SW VOUT VOUT The maximum rated current of the inductor should be greater than the peak inductor current (IPEAK). If the margin of these currents is not enough, the inductor may be saturated due to inductor value degradation, causing it to hit the current limit, even in a lower load condition than expected. The minimum output capacitor required is a 10 F, X5R capacitor; however, to maintain stability across the entire operating range and with component variations, one 22 F, X5R capacitor is recommended. The peak inductor current can be estimated as following: LAYOUT IPEAK = IIN + I RIPPLE = IIN + 0.15 x IIN = 1.15 x IIN 2 Another important specification to be considered is the parasitic series resistance in the inductor: dc resistance (DCR). A larger DCR may decrease efficiency performance, but a larger inductor size has smaller DCR; therefore, the tradeoff between available space on the PCB and device performance should be considered carefully. The recommended inductors are shown in Table 20. Output Capacitor Selection The output capacitor maintains the output voltage and supplies current to the load while the regulator switch is on. The value and characteristics of the output capacitor significantly affect the output voltage ripple and stability of the regulator. Use a low ESR output capacitor; ceramic dielectric capacitors are preferable. As output power increases, lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. It is also important to minimize the use of vias for signal lines with fast edges on the data transitions. In addition, do not place vias between the small value decoupling capacitors and the pin. Connect the vias to the ground or power planes on the far side of the capacitor from the perspective of the pin. Rev. 0 | Page 26 of 52 Data Sheet SSM4567 POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD) and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. Both the battery supply and internally generated VBST must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 10 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 1 F capacitor as close as possible to the VBAT and VBST pins of the device. If possible, avoid vias between the pins of the capacitor and the pin of the device. Placing the decoupling capacitors as close as possible to the SSM4567 helps to maintain good performance. Table 20. Suggested Inductors Part No. IFSC1008ABER2R2M01 IFSC1111ABER2R2M01 MAMK2520T2R2M L1210R2R2MDWIT LQM2HPN2R2MGHL Manufacturer Vishay Dale Vishay Dale Taiyo Yuden Kemet Murata Value (H) 2.2 2.2 2.2 2.2 2.2 Rated Current (mA) 1850 1900 1900 2000 1500 Rev. 0| Page 27 of 52 DCR () 0.09 0.098 0.117 0.08 0.110 Size (mm) 2.50 x 2.00 x 1.20 2.90 x 2.90 x 1.20 2.50 x 2.00 x 1.20 3.20 x 2.49 x 2.49 2.5 x 2.00 x 0.90 SSM4567 Data Sheet TYPICAL APPLICATION CIRCUITS SOFTWARE CONTROL MODE, I2S/TDM INTERFACE VBAT 10F 22F 2.2H 1F IOVDD LR_SEL/ ADDR VBAT SEL SSM4567 BSTSW BSTSW VBST VBST PGND BOOST (5V) DAC_PDM_CLK/ BCLK SNS_PDM_CLK/ FSYNC FILTERING MODULATION - CLASS-D MOD DAC SNS_PDM_DAT/ SNS_SDATAO DAC_PDM_DAT/ DAC_SDATAI OUTN H-BRIDGE (5V) R OUTP I2S/TDM/ PDM INTERFACE ADC V SENSE ADC I SENSE SCL SDA IOVDD 1F 12278-004 IOVDD AGND 0.1F Figure 54. Typical Application Circuit, I2S, Software Control Mode Description In this application circuit, the SSM4567 is controlled by an external master on the I2C interface. The I2C address is configured using the LR_SEL/ADDR pin. The serial data interface is in PCM mode, as configured by the SEL pin. Pin Configuration Table 21. Pin Configuration for I2S Software Control Applications, Software Control Mode, I2S/TDM Interface Hardware Pin LR_SEL/ADDR SEL SNS_PDM_CLK/FSYNC DAC_PDM_CLK/BCLK SNS_PDM_DAT/SNS_SDATAO DAC_PDM_DAT/DAC_SDATAI SCL SDA Connection Connect to AGND for I2C Address 0x34; IOVDD for I2C Address 0x35; leave open for I2C Address 0x36. Connect to IOVDD for PCM mode. Connect to an external I2S/TDM frame sync clock signal. Connect to an external I2S/TDM bit clock signal. Sends current, voltage, and battery sense data in I2S/TDM format to an external IC. Receives a serial audio data signal in I2S/TDM format from an external IC. Connect to the clock signal of an external I2C master IC. Connect to data signal of an external I2C master IC. Rev. 0| Page 28 of 52 Data Sheet SSM4567 SOFTWARE CONTROL MODE, PDM INTERFACE VBAT 10F 22F 2.2H 1F IOVDD LR_SEL/ ADDR VBAT SEL SSM4567 BSTSW BSTSW VBST VBST PGND BOOST (5V) DAC_PDM_CLK/ BCLK SNS_PDM_CLK/ FSYNC FILTERING MODULATION - CLASS-D MOD DAC SNS_PDM_DAT/ SNS_SDATAO DAC_PDM_DAT/ DAC_SDATAI OUTN H-BRIDGE (5V) R OUTP I2S/TDM/ PDM INTERFACE ADC V SENSE ADC I SENSE SCL SDA IOVDD 1F 12278-005 IOVDD AGND 0.1F Figure 55. Typical Application Circuit, PDM, Software Control Mode Description In this application circuit, the SSM4567 is controlled by an external master on the I2C interface. The I2C address is configured using the LR_SEL/ADDR pin. The serial data interface is initially set to PCM mode, as configured by the SEL pin, but must be changed to PDM mode using register writes when configuring the device via I2C. Pin Configuration Table 22. Pin Configuration for I2S Software Control Applications, Software Control Mode, PDM Interface Hardware Pin LR_SEL/ADDR SEL SNS_PDM_CLK/FSYNC DAC_PDM_CLK/BCLK SNS_PDM_DAT/SNS_SDATAO DAC_PDM_DAT/DAC_SDATAI SCL SDA Connection Connect to AGND for I2C Address 0x34; IOVDD for I2C Address 0x35; leave open for I2C Address 0x36. Connect to IOVDD for I2C control mode. Connect to an external PDM clock signal for sense data. Connect to an external PDM clock signal for audio data. Sends current, voltage, and battery sense data in PDM format to an external IC. Receives a serial audio data signal in PDM format from an external IC. Connect to the clock signal of an external I2C master IC. Connect to data signal of an external I2C master IC. Rev. 0| Page 29 of 52 SSM4567 Data Sheet STANDALONE MODE, I2S/TDM INTERFACE VBAT 10F IOVDD 22F 2.2H 1F 47k IOVDD LR_SEL/ ADDR VBAT SEL SSM4567 BSTSW BSTSW VBST VBST PGND BOOST (5V) DAC_PDM_CLK/ BCLK SNS_PDM_CLK/ FSYNC FILTERING MODULATION - CLASS-D MOD DAC SNS_PDM_DAT/ SNS_SDATAO DAC_PDM_DAT/ DAC_SDATAI OUTN H-BRIDGE (5V) R OUTP I2S/TDM/ PDM INTERFACE IOVDD ADC V SENSE ADC I SENSE SCL SDA IOVDD 1F 12278-006 IOVDD AGND 0.1F Figure 56. Typical Application Circuit, I2S, Standalone Mode Description In this application circuit, the SSM4567 operates in standalone mode, without an I2C master in the system. The I2C address is configured using the LR_SEL/ADDR pin. The serial data interface is in PCM mode, as configured by the SEL pin. Pin Configuration Table 23. Pin Configuration for I2S Software Control Applications, Standalone Mode, I2S/TDM Interface Hardware Pin LR_SEL/ADDR SEL SNS_PDM_CLK/FSYNC DAC_PDM_CLK/BCLK SNS_PDM_DAT/SNS_SDATAO DAC_PDM_DAT/DAC_SDATAI SCL SDA Connection Pull up to IOVDD with a 47 k resistor to enable standalone mode. Connect to IOVDD for PCM mode. Connect to an external I2S/TDM frame sync clock signal. Connect to an external I2S/TDM bit clock signal. Sends current, voltage, and battery sense data in I2S/TDM format to an external IC. Receives a serial audio data signal in I2S/TDM format from an external IC. Connect to either IOVDD or AGND to select which I2S/TDM audio data slot is sent to the amplifier (see Table 10). Connect to either IOVDD or AGND to select which I2S/TDM audio data slot is sent to the amplifier (see Table 10). Rev. 0| Page 30 of 52 Data Sheet SSM4567 PATTERN CONTROL MODE, PDM INTERFACE VBAT 10F 22F 2.2H 1F LR_SEL/ ADDR VBAT SEL SSM4567 BSTSW BSTSW VBST VBST PGND BOOST (5V) DAC_PDM_CLK/ BCLK SNS_PDM_CLK/ FSYNC FILTERING MODULATION - CLASS-D MOD DAC SNS_PDM_DAT/ SNS_SDATAO DAC_PDM_DAT/ DAC_SDATAI OUTN H-BRIDGE (5V) R OUTP I2S/TDM/ PDM INTERFACE ADC V SENSE ADC I SENSE SCL SDA IOVDD 1F 12278-007 IOVDD AGND 0.1F Figure 57. Typical Application Circuit, PDM, Pattern Control Mode Description In this application circuit, the SSM4567 is configured directly over the PDM interface, which is where it also receives audio data for playback and outputs sense information back to the host device. This mode is configured by connecting the SEL pin to AGND when the device is powered up. Optionally, the I2C pins can be left disconnected. The audio channel is selected by the state of the LR_SEL pin. Pin Configuration Table 24. Pin Configuration for PDM Pattern Mode Control Applications, Pattern Control Mode, PDM Interface Hardware Pin LR_SEL/ADDR SEL SNS_PDM_CLK/FSYNC DAC_PDM_CLK/BCLK SNS_PDM_DAT/SNS_SDATAO DAC_PDM_DAT/DAC_SDATAI SCL SDA Connection Connect to AGND to output the left PDM channel; connect to IOVDD to output the right PDM channel. Connect to AGND to start in PDM mode. Connect to an external PDM sense clock signal. Connect to an external PDM audio clock signal. Sends current, voltage, and battery sense data in PDM format to an external IC. Receives a serial audio data signal in PDM format from an external IC. Leave disconnected if I2C control is not needed; connect to SCL signal if I2C control is required. Leave disconnected if I2C control is not needed; connect to SDA signal if I2C control is required. Rev. 0| Page 31 of 52 SSM4567 Data Sheet REGISTER SUMMARY Table 25. REG_MAP Register Summary Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x00 POWER_CTRL [7:0] APWDN_EN BSNS_ PWDN VSNS_ PWDN ISNS_ PWDN BOOST_ PWDN AMP_ PWDN VBAT_ ONLY SPWDN 0x81 R/W 0x01 AMP_SNS_CTRL [7:0] SNS_HPF EDGES RESERVED ANA_GAIN 0x09 R/W 0x02 DAC_CTRL [7:0] 0x32 R/W 0x03 DAC_VOLUME [7:0] 0x40 R/W 0x04 SAI_CTRL_1 [7:0] SAI_DRV BCLK_POL 0x00 R/W 0x05 SAI_CTRL_2 [7:0] RESERVED PAD_DRV TDM_SLOT 0x08 R/W 0x06 SAI_PLACEMENT_ 1 [7:0] RESERVED P1_DAC RESERVED P1_SNS 0x01 R/W 0x07 SAI_PLACEMENT_ 2 [7:0] RESERVED P2_DAC RESERVED P2_SNS 0x20 R/W 0x08 SAI_PLACEMENT_ 3 [7:0] RESERVED P3_DAC RESERVED P3_SNS 0x32 R/W 0x09 SAI_PLACEMENT_ 4 [7:0] RESERVED P4_DAC RESERVED P4_SNS 0x07 R/W 0x0A SAI_PLACEMENT_ 5 [7:0] RESERVED P5_SNS 0x07 R/W 0x0B SAI_PLACEMENT_ 6 [7:0] RESERVED P6_SNS 0x07 R/W 0x0C BATTERY_V_OUT [7:0] 0x00 R 0x0D LIMITER_CTRL_1 [7:0] SLOPE 0xA4 R/W 0x0E LIMITER_CTRL_2 [7:0] LIM_RRT 0x73 R/W 0x0F LIMITER_CTRL_3 [7:0] 0x00 R/W 0x10 STATUS_1 [7:0] BAT_WARN 0x00 R 0x11 STATUS_2 [7:0] OTW 0x00 R 0x12 FAULT_CTRL [7:0] ARCV_OT ARCV_OC 0x30 R/W 0x13 PDM_CTRL [7:0] SHARED_ CLOCK SEL_VBAT 0x40 R/W 0x14 MCLK_RATIO [7:0] 0x11 R/W 0x15 BOOST_CTRL_1 [7:0] 0x03 R/W 0x16 BOOST_CTRL_2 [7:0] 0x00 R/W 0xFF SOFT_RESET [7:0] 0x00 R RESERVED DAC_HV SNS_FS DAC_MUTE DAC_HPF DAC_LPM RESERVED DAC_FS VOL TDM_BCLKS AUTO_SAI FSYNC_ MODE MC_I2S SDATA_ FMT SAI_MODE AUTO_ SLOT PDM_MODE VBAT VBAT_INF LIM_ATR RESERVED LIM_EN LIM_THRES RESERVED BST_FLT VBAT_ TRACK TAV LIM_EG CLIP VBAT_HYST UVLO AMP_OC OTF RESERVED OTW_GAIN PDM_LR_ SEL MAX_AR PAT_CTRL_ EN RESERVED RESERVED ADJ_PGATE MRCV I2C_ADDR_ SET ARCV_UV LOW_LATENCY AMCS MCS RESERVED RESERVED EN_DSCGB ARCV_BST SOFT_RESET Rev. 0| Page 32 of 52 RESERVED FPWMB SEL_FREQ SEL_GM Data Sheet SSM4567 REGISTER DETAILS POWER CONTROL REGISTER Address: 0x00, Reset: 0x81, Name: POWER_CTRL Table 26. Bit Descriptions for POWER_CTRL Bits 7 Bit Name APWDN_EN Settings 0 1 6 BSNS_PWDN 0 1 5 VSNS_PWDN 0 1 4 ISNS_PWDN 0 1 3 BOOST_PWDN 0 1 2 AMP_PWDN 0 1 1 VBAT_ONLY 0 1 0 SPWDN 0 1 Description Auto Power-Down Enable. Auto power down automatically puts the IC in a low power state when 2048 consecutive zero input samples have been received. Auto Power-Down Disabled. Auto Power-Down Enabled When APWDN_EN=1. The device automatically powers down when 2048 consecutive zero value input samples have been received. The device automatically powers up when a single non zero sample is received. Battery Voltage Sense Power Down. Battery Voltage Sense Powered On. Battery Voltage Sense Powered Off. Voltage Sense Power-Down. Voltage Sense Powered On. Voltage Sense Powered Off. Current Sense Power Down. Current Sense Powered On. Current Sense Powered Off. Boost Converter Power-Down. When the boost converter is powered down, the Class-D operates directly from VBAT power supply. Boost Converter Enabled. Boost Converter Powered Down. Amplifier Power-Down. Amplifier and DAC Normal Operation. Amplifier and DAC Powered Down. Class-D Power Switch. Class-D can switch between VBAT and PVDD as a five-level output. Class-D powered from VBAT only, even if the booster is on. Master Software Power-Down. Software power-down puts all blocks except the I2C interface in a low power state. Normal Operation. Software Master Power-Down. Rev. 0| Page 33 of 52 Reset 0x1 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W SSM4567 Data Sheet AMP AND SENSE CONTROL REGISTER Address: 0x01, Reset: 0x09, Name: AMP_SNS_CTRL Table 27. Bit Descriptions for AMP_SNS_CTRL Bits [7:6] [5:4] Bit Name RESERVED SNS_FS Settings 00 01 10 11 3 SNS_HPF 0 1 2 EDGES 0 1 1 0 RESERVED ANA_GAIN 0 1 Description Reserved. Sense Sample Rate. The sense output sample rate can be set at a lower rate than the DAC. Sense Sample Rate same as the DAC. Sense Sample Rate 1/2 of the DAC. Sense Sample Rate 1/4 of the DAC. Sense Sample Rate 1/8 of the DAC. SNS High Pass Filter Enable. SNS High Pass Filter Off. SNS High Pass Filter On Edge Rate Control. This controls the edge speed of the power stage. The low EMI operation mode reduces the edge speed, lowering EMI and power efficiency. Normal Operation. Low EMI Mode Operation for Class-D power stage. Reserved. Amplifier Analog Gain Selection. 3.6 V Full-Scale Gain Mapping. 5.2 V Full-Scale Gain Mapping. Rev. 0| Page 34 of 52 Reset 0x0 0x0 Access R/W R/W 0x1 R/W . 0x0 R/W 0x0 0x1 R/W R/W Data Sheet SSM4567 DAC CONTROL REGISTER Address: 0x02, Reset: 0x32, Name: DAC_CTRL Table 28. Bit Descriptions for DAC_CTRL Bits 7 Bit Name DAC_HV Settings 0 1 6 DAC_MUTE 0 1 5 DAC_HPF 0 1 4 DAC_LPM 0 1 3 [2:0] RESERVED DAC_FS 000 001 010 011 100 101 110 111 Description DAC Hard Volume Soft Volume Ramping Hard/Immediate Volume Change DAC Mute Control DAC Unmuted DAC Muted DAC High-Pass Filter Enable DAC High-Pass Filter Off DAC High-Pass Filter On DAC Low Power Mode Enable DAC Low Power Mode Off (128 x fs in PDM Mode) DAC Low Power Mode On (64 x fs in PDM Mode) Reserved. DAC Sample Rate Selection 8 kHz to 12 kHz Sample Rate 16 kHz to 24 kHz Sample Rate 32 kHz to 48 kHz Sample Rate 64 kHz to 96 kHz Sample Rate 128 kHz to 192 kHz Sample Rate Reserved Reserved Reserved Rev. 0| Page 35 of 52 Reset 0x0 Access R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 0x2 R/W R/W SSM4567 Data Sheet DAC VOLUME CONTROL REGISTER Address: 0x03, Reset: 0x40, Name: DAC_VOLUME Table 29. Bit Descriptions for DAC_VOLUME Bits [7:0] Bit Name VOL Settings 00000000 00000001 00000010 00000011 00000100 00000101 00111111 01000000 01000001 01000010 11111101 11111110 11111111 Description Volume Control +24 dB +23.625 dB +23.35 dB +22.875 dB +22.5 dB ... +0.375 dB 0 -0.375 dB ... -70.875 dB -71.25 dB Mute Reset 0x40 Rev. 0| Page 36 of 52 Access R/W Data Sheet SSM4567 SERIAL AUDIO INTERFACE CONTROL 1 REGISTER Address: 0x04, Reset: 0x00, Name: SAI_CTRL_1 Table 30. Bit Descriptions for SAI_CTRL_1 Bits 7 Bit Name SAI_DRV Settings 0 1 6 BCLK_POL 0 1 [5:4] TDM_BCLKS 00 01 10 11 3 FSYNC_MODE 0 1 2 SDATA_FMT 0 1 1 SAI_MODE 0 1 0 PDM_MODE 0 1 Description Drive Control for Unused BCLK Cycles Unused BCLK cycles on SNS_SDATA are not driven (high-Z) Unused BCLK cycles on SNS_SDATA are driven low BCLK Polarity Rising Edge of BCLK is used to register SDATA Falling Edge of BCLK is used to register SDATA Number of BCLK cycles per chip in TDM Mode. Any number of BCLK cycles per FSYNC can be used in stereo modes (I2S/left justified) or in TDM mode with only one chip. When in TDM mode, with multiple chips on the TDM bus, the number of BCLK cycles per chip must be defined. 32 BCLK cycles per chip in TDM 48 BCLK cycles per chip in TDM 64 BCLK cycles per chip in TDM 64 BCLK cycles per chip in TDM FSYNC Mode Control Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM Modes High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes Serial Data Format I2S/Delay by one from FSYNC edge Left Justified/No delay from FSYNC edge Serial Audio Interface Mode Selection Stereo Modes (I2S, left justified) TDM/PCM Modes PDM Input and Output Mode Normal Serial Audio Interface Operation PDM used for input and output Rev. 0| Page 37 of 52 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W SSM4567 Data Sheet SERIAL AUDIO INTERFACE CONTROL 2 REGISTER Address: 0x05, Reset: 0x08, Name: SAI_CTRL_2 Table 31. Bit Descriptions for SAI_CTRL_2 Bits 7 6 Bit Name RESERVED PAD_DRV Settings 0 1 5 AUTO_SAI 0 1 4 MC_I2S 0 1 3 AUTO_SLOT 0 1 [2:0] TDM_SLOT 000 001 010 011 100 101 110 111 Description Reserved. Output pad drive strength control. SNS_PDM_DAT/SNS_SDATAO pin output drive strength. low strength high strength Automatic Serial Audio Interface Detection Enable. When AUTO_SAI = 1 the Serial Audio Interface automatically configures based on the connections of BCLK and FSYNC. When FSYNC and BCLK are connected normally, and a pulsed FSYNC is detected, the interface automatically configures for TDM operation. When FSYNC and BCLK are connected normally, and a 50% duty cycle FSYNC is detected, the interface automatically configures for multichip I2S operation. When FSYNC and BCLK are connected to the opposite pins, the interface automatically configures for normal I2S operation. When set for automatic detection the values of SAI_MODE and SDATA_FMT are ignored. SAI_MODE, SDATA_FMT, and MC_I2S are used to set the Serial Audio Interface configuration Auto Serial Audio Interface Detection Enabled Multichip I2S Enable. When MC_I2S is selected, this overrides the SAI_MODE selection. Normal Operation Multichip I2S Operation Automatic TDM and MC I2S slot selection TDM/MC I2S Slot determined by TDM_SLOT bits TDM/MC I2S Slot determined by ADDR pin TDM and Multichip I2S slot selection Chip Slot 1 Used Chip Slot 2 Used Chip Slot 3 Used Chip Slot 4 Used Chip Slot 5 Used Chip Slot 6 Used Chip Slot 7 Used Chip Slot 8 Used Rev. 0| Page 38 of 52 Reset 0x0 0x0 Access R/W R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W Data Sheet SSM4567 SERIAL AUDIO INTERFACE PLACEMENT 1 CONTROL REGISTER Address: 0x06, Reset: 0x01, Name: SAI_PLACEMENT_1 Table 32. Bit Descriptions for SAI_PLACEMENT_1 Bits [7:6] [5:4] Bit Name RESERVED P1_DAC Settings 00 01 10 11 3 [2:0] RESERVED P1_SNS 000 001 010 011 100 101 110 111 Description Reserved. Placement 1 or L1 (Left 1) Control for DAC Input. Selects the size of the data to be read. 24 bits or 16 bits. This slot can also be set to read in eight bits, throw them away, and move on to Placement P2 to read the audio data. 24-Bit DAC Input 16-Bit DAC Input Read and Ignore 8-bits Read and Ignore 8-bits Reserved. Placement 1 or L1 (Left 1) Control for Sense Output. 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Rev. 0| Page 39 of 52 Reset 0x0 0x0 Access R/W R/W 0x0 0x1 R/W R/W SSM4567 Data Sheet SERIAL AUDIO INTERFACE PLACEMENT 2 CONTROL REGISTER Address: 0x07, Reset: 0x20, Name: SAI_PLACEMENT_2 Table 33. Bit Descriptions for SAI_PLACEMENT_2 Bits [7:6] [5:4] Bit Name RESERVED P2_DAC Settings 00 01 10 11 3 [2:0] RESERVED P2_SNS 000 001 010 011 100 101 110 111 Description Reserved. Placement 2 or R1 (Right 1) Control for DAC Input. Selects the size of the data to be read. 24 bits or 16 bits. This slot can also be set to read in eight bits, throw them away, and move on to Placement P3 to read the audio data. 24-Bit DAC Input 16-Bit DAC Input Read and Ignore 8 bits Read and Ignore 8 bits Reserved. Placement 2 or R1 (Right 1) Control for Sense Output. 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Rev. 0| Page 40 of 52 Reset 0x0 0x2 Access R/W R/W 0x0 0x0 R/W R/W Data Sheet SSM4567 SERIAL AUDIO INTERFACE PLACEMENT 3 CONTROL REGISTER Address: 0x08, Reset: 0x32, Name: SAI_PLACEMENT_3 Table 34. Bit Descriptions for SAI_PLACEMENT_3 Bits [7:6] [5:4] Bit Name RESERVED P3_DAC Settings 00 01 10 11 3 [2:0] RESERVED P3_SNS 000 001 010 011 100 101 110 111 Description Reserved. Placement 3 or L2 (Left 2) Control for DAC Input. Selects the size of the data to be read. 24 bits or 16 bits. This slot can also be set to read in eight bits, throw them away, and move on to placement P4 to read the audio data. 24-Bit DAC Input 16-Bit DAC Input Read and Ignore 8 bits Read and Ignore 8 bits Reserved. Placement 3 or L2 (Left 2) Control for Sense Output. 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Rev. 0| Page 41 of 52 Reset 0x0 0x3 Access R/W R/W 0x0 0x2 R/W R/W SSM4567 Data Sheet SERIAL AUDIO INTERFACE PLACEMENT 4 CONTROL REGISTER Address: 0x09, Reset: 0x07, Name: SAI_PLACEMENT_4 Table 35. Bit Descriptions for SAI_PLACEMENT_4 Bits [7:6] [5:4] Bit Name RESERVED P4_DAC Settings 00 01 10 11 3 [2:0] RESERVED P4_SNS 000 001 010 011 100 101 110 111 Description Reserved. Placement 4 or R2 (Right 2) Control for DAC Input 24-Bit DAC Input 16-Bit DAC Input Read and Ignore 8 bits Read and Ignore 8 bits Reserved. Placement 4 or R2 (Right 2) Control for Sense Output 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Rev. 0| Page 42 of 52 Reset 0x0 0x0 Access R/W R/W 0x0 0x7 R/W R/W Data Sheet SSM4567 SERIAL AUDIO INTERFACE PLACEMENT 5 CONTROL REGISTER Address: 0x0A, Reset: 0x07, Name: SAI_PLACEMENT_5 Table 36. Bit Descriptions for SAI_PLACEMENT_5 Bits [7:3] [2:0] Bit Name RESERVED P5_SNS Settings 000 001 010 011 100 101 110 111 Description Reserved. Placement 5 or L3 (Left 3) Control for Sense Output 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Reset 0x0 0x7 Access R/W R/W Reset 0x0 0x7 Access R/W R/W SERIAL AUDIO INTERFACE PLACEMENT 6 CONTROL REGISTER Address: 0x0B, Reset: 0x07, Name: SAI_PLACEMENT_6 Table 37. Bit Descriptions for SAI_PLACEMENT_6 Bits [7:3] [2:0] Bit Name RESERVED P6_SNS Settings 000 001 010 011 100 101 110 111 Description Reserved. Placement 6 or R3 (Right 3) Control for Sense Output 16-Bit Voltage Output 16-Bit Current Output 8-Bit Battery Voltage Output Unsigned 8-Bit Control Data Output Alternating 16-Bit Voltage and Current 8-Bit Status Output 8-Bit V/I Marker and Slot ID Blank 8 Bits Rev. 0| Page 43 of 52 SSM4567 Data Sheet BATTERY VOLTAGE OUTPUT REGISTER Address: 0x0C, Reset: 0x00, Name: BATTERY_V_OUT Table 38. Bit Descriptions for BATTERY_V_OUT Bits [7:0] Bit Name VBAT Settings Description 8-Bit Unsigned Battery Voltage Reset 0x0 Access R LIMITER CONTROL 1 REGISTER Address: 0x0D, Reset: 0xA4, Name: LIMITER_CTRL_1 Table 39. Bit Descriptions for LIMITER_CTRL_1 Bits [7:6] Bit Name SLOPE Settings 00 01 10 11 [5:3] VBAT_INF 000 001 010 011 100 101 110 111 2 VBAT_TRACK 0 1 [1:0] LIM_EN 00 01 10 11 Description Limiter Ratio below the VBAT_INF threshold. Limiter ratio once the VBAT voltage falls below the VBAT_INF threshold. This sets the slope of the limiter curve as the VBAT voltage falls. 1:1 Limiter Ratio 2:1 Limiter Ratio 3:1 Limiter Ratio 4:1 Limiter Ratio Battery Voltage Inflection point. When VBAT drops below the inflection point and VBAT_TRACK = 1 the limiter threshold starts being lowered to limit maximum output and peak current from the battery. The amount of reduction when the battery voltage is lower than VBAT_INF is determined by the SLOPE bits. 3.9 V 3.8 V 3.7 V 3.6 V 3.5 V 3.4 V 3.3 V 3.2 V Threshold Battery Tracking Enable Limiter Attack Threshold Fixed Limiter Attack Threshold Varies or gain reduction with Battery Voltage Limiter or Mute mode Enable Limiter and mute mode Off Limiter On Output will mute if VBAT is below VBAT_INF Limiter On but will only engage if VBAT is below VBAT_INF Rev. 0| Page 44 of 52 Reset 0x2 Access R/W 0x4 R/W 0x1 R/W 0x0 R/W Data Sheet SSM4567 LIMITER CONTROL 2 REGISTER Address: 0x0E, Reset: 0x73, Name: LIMITER_CTRL_2 Table 40. Bit Descriptions for LIMITER_CTRL_2 Bits [7:6] Bit Name LIM_RRT Settings 00 01 10 11 [5:4] LIM_ATR 00 01 10 11 [3:0] LIM_THRES 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Limiter Release Rate 3200 ms/dB 1600 ms/dB 1200 ms/dB 800 ms/dB Limiter Attack Rate 120 s/dB 60 s/dB 30 s/dB 20 s/dB Limiter Attack Threshold 6.6 V peak Output 6.4 V peak Output 6.2 V peak Output 6.0 V peak Output 5.8 V peak Output 5.6 V peak Output 5.4 V peak Output 5.2 V peak Output 5.0 V peak Output 4.8 V peak Output 4.6 V peak Output 4.4 V peak Output 4.2 V peak Output 4.0 V peak Output 3.8 V peak Output 3.6 V peak Output Rev. 0| Page 45 of 52 Reset 0x1 Access R/W 0x3 R/W 0x3 R/W SSM4567 Data Sheet LIMITER CONTROL 3 REGISTER Address: 0x0F, Reset: 0x00, Name: LIMITER_CTRL_3 Table 41. Bit Descriptions for LIMITER_CTRL_3 Bits [7:4] 3 Bit Name RESERVED TAV Settings 0 1 [2:0] VBAT_HYST 000 001 010 011 100 101 110 111 Description Reserved. TAV, Detector Time Averaging Filter Long RMS average time Short RMS average time vbat_hyst No hysteresis -36 dBV -33 dBV -30 dBV -27 dBV -24 dBV -21 dBV -18 dBV Rev. 0| Page 46 of 52 Reset 0x0 0x0 Access R/W R/W 0x0 R/W Data Sheet SSM4567 STATUS 1 REGISTER Address: 0x10, Reset: 0x00, Name: STATUS_1 Table 42. Bit Descriptions for STATUS_1 Bits 7 Bit Name BST_FLT Settings 0 1 6 5 RESERVED LIM_EG 0 1 4 CLIP 0 1 3 UVLO 0 1 2 AMP_OC 0 1 1 OTF 0 1 0 BAT_WARN 0 1 Description Boost Fault Status Normal Operation Boost Converter Fault Condition Reserved. Limiter/Gain Reduction Engaged Normal Operation Limiter or Gain Reduction has Reduced Gain Clip Detector Normal Operation Amplifier Clipping Detected Under Voltage Fault Status Normal Operation Under Voltage Fault Amplifier Overcurrent Fault Status Normal Operation Amp Overcurrent Fault Condition Over Temperature Fault Status Normal Operation Over Temperature Fault Condition Battery Voltage Warning Battery Voltage above VBAT_INF Battery Voltage at or below VBAT_INF Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Reset 0x0 0x0 Access R R STATUS 2 REGISTER Address: 0x11, Reset: 0x00, Name: STATUS_2 Table 43. Bit Descriptions for STATUS_2 Bits [7:1] 0 Bit Name RESERVED OTW Settings 0 1 Description Reserved. Overtemperature Warning Status Normal Operation Overtemperature Warning Condition Rev. 0| Page 47 of 52 SSM4567 Data Sheet FAULT CONTROL REGISTER Address: 0x12, Reset: 0x30, Name: FAULT_CTRL Table 44. Bit Descriptions for FAULT_CTRL Bits [7:6] Bit Name OTW_GAIN Settings 00 01 10 11 [5:4] MAX_AR 00 01 10 11 3 MRCV 0 1 2 ARCV_UV 0 1 1 ARCV_OT 0 1 0 ARCV_OC 0 1 Description Over Thermal Warning Gain Reduction No gain reduction in thermal warning 1.5 dB gain reduction in thermal warning 3 dB gain reduction in thermal warning 5.625 dB gain reduction in thermal warning Maximum Fault recovery Attempts. The Maximum autorecovery register determines how many attempts at auto recovery are performed. 1 Autorecovery Attempt 3 Autorecovery Attempts 7 Autorecovery Attempts Unlimited Autorecovery Attempts Manual Fault Recovery Normal Operation Writing of 1 causes a manual fault recovery attempt when ARCV_OC/ARCV_OT/ARCV_UV/ARCV_BST = 1 Undervoltage Autofault Recovery Control Auto Fault Recovery for Undervoltage Fault Manual Fault Recovery for Undervoltage Fault Overtemperature Auto Fault Recovery Control Auto Fault Recovery for Overtemperature Fault Manual Fault Recovery for Overtemperature Fault Overcurrent Auto Fault Recovery Control Auto Fault Recovery for Overcurrent Fault Manual Fault Recovery for Overcurrent Fault Rev. 0| Page 48 of 52 Reset 0x0 Access R/W 0x3 R/W 0x0 W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet SSM4567 PDM CONTROL REGISTER Address: 0x13, Reset: 0x40, Name: PDM_CTRL Table 45. Bit Descriptions for PDM_CTRL Bits 7 Bit Name PDM_LR_SEL Settings 0 1 6 PAT_CTRL_EN 0 1 5 4 RESERVED I2C_ADDR_SET 0 1 [3:2] LOW_LATENCY 00 01 10 1 SHARED_CLOCK 0 1 0 SEL_VBAT 0 1 Description PDM left/right channel select when external PIN SEL =1 select left channel select right channel Enable PDM pattern control when external PIN SEL=0 Disable PDM pattern control Enable PDM pattern control Reserved. Setting the I2C Address in PDM mode when external PIN SEL = 0 I2C Address is fixed to 0x34 in PDM mode I2C Address determined by LR_SEL/ADDR pin in PDM mode (LR_SEL/ADDR = 0, Address = 0x34; LR_SEL/ADDR = 1, Address = 0x35) Low latency Mode Normal Mode Low latency Mode, delay about 15 s Low latency Mode, delay about 5 s Only DAC_PDM_CLK is needed Do not share DAC_PDM_CLK is shared with SNS_PDM_CLK Select VBAT to output output sense voltage in PDM mode Output sense battery voltage (VBAT) in PDM mode MCLK RATIO SETTING REGISTER Address: 0x14, Reset: 0x11, Name: MCLK_RATIO Rev. 0| Page 49 of 52 Reset 0x0 Access R/W 0x1 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W SSM4567 Data Sheet Table 46. Bit Descriptions for MCLK_RATIO Bits [7:5] 4 Bit Name RESERVED AMCS Settings 0 1 [3:0] MCS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Description Reserved. Auto MCS. Automatic or manual Master Clock ratio Setting Manual MCLK ratio Setting by using the MCS Bits Automatic MCLK ratio detection The Master Clock ratio Setting that is detected is stored in the MCS register bits to allow the setting to be read. MCLK Ratio Setting (when AMCS = 1, this reads back the auto detection setting ) 64 x fs 128 x fs 192 x fs 256 x fs 384 x fs 512 x fs 50 x fs 100 x fs 200 x fs 400 x fs Reset 0x0 0x1 Access R/W R/W 0x1 R/W BOOST CONTROL 1 REGISTER Address: 0x15, Reset: 0x03, Name: BOOST_CTRL_1 Table 47. Bit Descriptions for BOOST_CTRL_1 Bits [7:6] Bit Name ADJ_PGATE Settings 00 01 10 11 [5:3] 2 RESERVED EN_DSCGB 0 1 1 FPWMB 0 1 0 SEL_FREQ 0 1 Description PMOS driver speed setting Fastest pmos driver speed Fast pmos driver speed Slow pmos driver speed Slowest pmos driver speed Reserved. Output discharge switch enable Disable the output discharge switch Enable the output discharge switch Force PWM mode for the boost Force PWM Mode PWM mode + PSM mode Boost clock frequency Select 2.5 MHz 1.25 MHz Rev. 0| Page 50 of 52 Reset 0x0 Access R/W 0x0 0x0 R/W R/W 0x1 R/W 0x1 R/W Data Sheet SSM4567 BOOST CONTROL 2 REGISTER Address: 0x16, Reset: 0x00, Name: BOOST_CTRL_2 Table 48. Bit Descriptions for BOOST_CTRL_2 Bits [7:4] 3 Bit Name RESERVED ARCV_BST Settings 0 1 2 [1:0] RESERVED SEL_GM 00 01 10 11 Description Reserved Autorecovery setting for boost fault Autorecovery for boost fault Manual recovery for boost fault Reserved Transconductance (gm) selection for the error amplifier in the boost 12.5 S gm 16.6 S gm 20.0 S gm 25.0 S gm Reset 0x0 0x0 Access R/W R/W 0x0 0x0 R/W R/W Reset 0x0 Access R SOFT RESET REGISTER Address: 0xFF, Reset: 0x00, Name: SOFT_RESET Table 49. Bit Descriptions for SOFT_RESET Bits [7:0] Bit Name SOFT_RESET Settings Description Soft Reset (write the value 0x00 to this register to initiate a soft reset) Rev. 0| Page 51 of 52 SSM4567 Data Sheet OUTLINE DIMENSIONS 1.780 1.740 1.700 4 3 2 1 A BALL A1 IDENTIFIER B 2.140 2.100 2.060 1.60 REF C D E 0.40 BSC BOTTOM VIEW TOP VIEW (BALL SIDE UP) (BALL SIDE DOWN) 1.20 REF 0.560 0.500 0.440 SIDE VIEW SEATING PLANE 0.300 0.260 0.220 0.230 0.200 0.170 12-19-2012-A COPLANARITY 0.05 Figure 58. 19-Ball Wafer Level Chip Scale Package [WLCSP] (CB-19-1) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM4567ACBZ-R7 SSM4567ACBZ-RL EVAL-SSM4567Z EVAL-SSM4567MINIZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 19-Ball WLCSP 19-Ball WLCSP Evaluation Board Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12278-0-4/14(0) Rev. 0| Page 52 of 52 Package Option CB-19-1 CB-19-1