(S) MOTOROLA MC14553B eeseee8ee 3-DIGIT BCD COUNTER On-Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Stow Rise Times on input Clock Output Latches Master Reset . The MC14553B 3-digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide dispiay control. All outputs are TTL compatible. An on-chip oscillator provides the low-frequency scanning clock which drives the multiplexer output selector. . This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications, : TTL Compatible Outputs MAXIMUM RATINGS" (Voltages Referenced to Vgs) Unit L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ? t ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MCi4XxxBDW SOIC Ta = 55 to 125C for ail packages. Symbol Parameter Value Vpp DC Supply Voltage -0,5 to + 18.0 Vv Vin Vout| input or Output Voltage (DC or Transient) ~0.5 10 Vpop +0.5 Vv lin Input Current (DC or Transient), per Pin +10 mA lout | Output Current (DC or Transient}, per Pin +20 mA Pp Power Dissipation, per Packaget 500 mw Tstg | Storage Temperature 65 to +150 C Tr Lead Temperature (8-Scond Soldering) 260 G *Maxitnum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW" Packages; ~7.0 mW/C From 65C To 125C Ceramic L Packages: 12 mWPC From 100C To 128C TRUTH TABLE INPUTS MASTER RESET CLOCK | DISABLE LE OUTPUTS 0 _/ Qo 9 No Change 0 Ne 9 Oo Advance Q x 1 x No Change 0 1 _/_ Advance 9 1 o No Change 0 9 x x No Change 0 x x ~~ Latched 0 x x 1 Latched 1 x x o | QO=ata2= a3=0 X = Gont Care BLOCK DIAGRAM | CtA CIB gone 9 12 O-4 Cicck AtRO 7 Q2-=5 6 10 O4 LE ashe 5 - O.F.-o 14 11 O=mmt Dis Bib 06 2 5S2-o 1 13 Ome MA BSs 15 Vop = Pin 16 Vsg = Ping This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precau- tions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For Proper Operation, Vin and Vout should be constrained to the range Vgg < (Vip or Vout) = Vpp. Unused inputs must always be tied to an ap- propriate logic voltage level (e.g., either Vss or Vpp). Unused outputs must be left open. 6-412MC14553B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vs) Characteristi symbot | OP =85C are 125C Unit aracter! mbo teuic y Vdc [win | Max | Min | Typ# | Max | Min | Max Output Voltage 0 Level 5.0 -| 0.05 0 0,05 - 0.05 Vin = Vbp or 0 VOL 10 -| 0.05 _ 0 0.05 _ 0,05 | Vde 15 _ 0.05 _ 0 0.05 . _ 0.05 1" Level 50 | 495} 4.95 5.0 | 495 | Vin = Gor Vpp . Vou jo | 995 | 9.95 10 --| 995 | | Vde 15 14,95 _ 14.95 15 _ 14.95 _ Input Voltage ~O" Level (Vo = 4.5 or 0.5 Vdc) Vv 5.0 =| 15 = 2.25 15 18 | Vado (Vo = 9.0 or 1.0 Vdc) iL 10 3.0 4.50 30 | 3.0 (VQ = 13.5 or 1.5 Vdc} 15 -| 40 6.75 4.0 4.0 "1" Level (Vo = 0.5 or 4.5 Vdc) - 5.0 3.5 _ 3.5 2.75 _ 3.5 _ (VQ = 1.0 or 9.0 Vde} MH 10 | 7.0 7.0 5,50 7.0 | Ye (Vo = 1.5 or 13.5 Vde} 15 1 1 8.25 11 Output Drive Current oO foH mAde (VOH = 4.6 Vde) Source = = Pin 3 5.0 - 0.25 _ ~0.2 ~0.36 { 0.14 _ (VoH = 9.5 Vdc) ~ io | -o62) -0.5 ~09 -| 095 | (VoH = 13.5 Vdc) 1 | -18 | -15 -3.5 w} 14 (VOH = 4.6 Vdc) Source Other 5.0 - 0.64 _ ~0.51 ~ 0.88 _ -0.36 _ mAdc (VoH = 9.5 Vde) Outputs 10 -1.6 ~13 2.25 _ -0.9 - (VOH = 13.5 Vde) , 1 | -42 4) -3.4 -88 j -24] (VOL = 0.4 Vdc} Sink Pin 3 lot 5.0 0.5 - 04 0.88 _ 0.28 _ mAde (VoL = 0.5 Vdc) 10 1.1 _ 0.9 2.25 _ 0.65 _ (VoL = 1.5 Vde) . 15 18 - 15 8.8 -| 1.20 - (VoL = 0.4 Vde) Sink Other 5.0 3.0 _ 2.5 4.0 _ 1.6 _ mAdc (VoL = 0.5 Vde) Outputs 10 6.0 - 5.0 8.0 _ 3.5 _ (Vo. = 1.5 Vdc} 15 18 _ 15 20 10 Input Current lin 15 _- +01 - +0.00001| +0.1 = 41.0 | pAdc Input Capacitance _ Cin _ _ _ _- 5.0 7.5 _ _ pF (Vin = 9) Quiescent Current , ipp 5.0 -{ 5.0 _ 0.010 5.0 _ 150 | wAde (Per Package) 10 = 10 -| 0.020 10 300 MR = Vop 15 -~]| 20 -| 0.030 20 | 600 Total Supply Current**t ly 5.0 ly = (0.35 pA/KHz) f + [DD nAdc (Dynamic plus Quiescent, . 10 ly = (0.85 pAVKHz) f + Ipp Per Package) 16 fy = (1.50 pA/KHz) f + Ipp (CL = 50 pF on all outputs, al buffers. switching) #Data labelled Typ is not to Be used for design purposes but is intended as an indication of the ICs potential performance. The formulas given are for the typical characteristics only at 25C._. +To calculate total supply current at loads other than 50 pF: IT(CL) = 17(50 pF} + (CL 50) Vik where: IT is in #A (per package), C_ in pF V = (Vpp - Vgg) in volts, f in kHz is input frequency, and k = 0.004 6-413SWITCHING CHARACTERISTICS (C_ = 50 pF, Ta = 25C) MC14553B n at Characteristic Figure Symbol Vop Min Typ # Max Unit Output Rise and Fall Time 2a tTLHe ns tTLH (THL = (1.5 ns/pF) CL + 25 ns a HL 5.0 _ 100 200 'TLH: tTHL = (0.75 ns/pF) CL + 12.5 ns 10. _ 50 100 tTLH. tTHL = (0.55 ns/pF) CL + 9.5 ns 15 - .- 40 80 Glock to BCD Out 2a tPLH. 5.0 900 1800 ns {PHL 10 _- 500 1000 ; 15 _ 200 400 Clock to Overflow 2a {PHL 5.0 _-. 600 1200 ns 10 _ 400 800 15 - 200 400 Reset to BCD Out . 2b {PHL 5.0 - 900 1800 ns 10 - 500 1000 : 15 _- 300 600 ~ Clock to Latch Enable Setup Time 2b tsu 5.0 600 300 _ ns Master Reset to Latch Enable Setup Time 10 400 200 _ 15 200 100 _ Removal Time . : 2b trem 5.0 -80 ~ 200 _ ns Latch Enable to Clock : 10 -=10 -70 ad 15 0 ~60 _ Clock Pulse Width 2a twHyol) 5.0 550 278 _ ns 10 200 100 _ | 15 150 75 _ Reset Pulse Width 2b tWH(R) 5.0 1200 600 _ ns 10 600 300 _ / 45 450 225 Reset Removal Time _ trem 5.0 ~86 - 180 _ ns 10 0 ~50 _- ; ; _ 15 20 -30 _ Input Clock Frequency 2a fol 5.0 _ 1s 0.9 MHz 10 - 5.0 25 ; 15 - 7.0 3.5 input Clock Rise Time . 2b tTLH 5.0 No ns . 10 Limit 15 Disable, MR, Latch Enable - tTLH: 5.0 = _ 15 BS Rise and Fall Times TTHL 10 _ _ 5.0 ; 15 _ = 4.0 Scan Oscillator Frequency 1 fosc 5.0 _ 1.56/01 _ Hz (C1 measured in wF) 10 al 42/01 _ 5 i | | sar] = "The formutas given are far the typical characteristics only at 25C. #Data labelled Typ is nol to be used for design purposes but is. intended as an Indication of the IC's potential performance. 6-414or ce NOTH OR OA MC14553B Units Clock U ULL ee Units Q0 n i | J yf ! J | I | [ Units Q1 i | | | 1 I 4 r 1 Units Q2 t __ Lit __f 7 Sa 888 SRSISRSB UL 1 tt uw ot vie 03 ! aon a tt a Tans Ciock ni fj SL J I ' __ - ta 5 Tens 00 es =: i = - - tt Tens Q3 ~. 11 : ~ ens Up at 80 - a i Up at 980 iL. lundreds _ fn = Clock - = I ty Hundreds QO - . = pL Hundreds O3 Disable > (Disables Clock When High) Overflow Master Reset 1 Up at 800 Scan Oscillator Digit Select 1 Ls Digit Select 2 Oigit Select 3 (a) Units? 1 Tens 16 ? Vpbo Hundreds FIGURE 2 SWITCHING TIME TEST CIRCUITS AND WAVEFORMS Pulse - Generator . MR a3 a2 at ao O.F. 551 Bs2 Os3 (b) 8 Vss Yoo Generator 1 Generator O 3 MR Dis - 20 ns Clock 90% 10% PLH: BCD Out ot Overflow Clock Latch Enable . 10% 999 tTHLE g tWL(el) TPHL __ BCD Out ---- Master Reset 6-415 50%MC14553B OPERATING CHARACTERISTICS The MC145538 three-digit counter, shown in Figure 3, consists of three negative edge-triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits Storage of any given count. The three sets of BCD outputs (active high}, after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on-chip oscillator provides the low frequency scan- ning clock which drives the multiplexer output selector. - The frequency of the oscillator can be controlied ex- ternally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow Output, which provides one pulse for every 1000 counts, The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit, - While Master Reset is high the digit scanner is set to digit one; but all three digit select Outputs are disabled to, prolong display life, and the sean oscillator is inhibited. The Disable input, when high, Prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue Operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, in- dependent of other inputs. information can be recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle. FIGURE 3 EXPANDED BLOCK DIAGRAM Latch Enable 10 a Disable {Active High) 13 14 MR Overflow (Active High) 6-416 Cia / They Pulse aT / Generator Scan Oscillator Cig FR Scanner ao Multipiexer BcD Outputs (Active High) 2 1 15 581 632 B53 (LSD) Digit Select (MSD) {Active Low)MC14553B ususbes wed yu OL > 2#24)) $O37 1UsNd MO] Ble SAECO asi We AAA, Wav A ANA, VV" AAA Viv AAA ft} jit Ld} wi LIE it i at StrSrlOW 1s qd moe a . b I Ud 9 1 v z g AA Wie vi + at a SE t ada Sy > , EL a5 | Pp a ZL} sevsytow ot ad,jg-+ rm z . ela a OL e e v 6 $ {z |. |st Je fe jo [s rsazsaesaqoo 1D zo co] _ | sol FL vO 9 ut AESSHLOW |he9 41D Zz vy, 2 uw 4 l ot z |s jor is 9 |s tsa 2$0 ESO 00 10 zd ED _ 2? so 815 Sessrion av of 5 andu} 00O | WI PT_ 019 yl '? uw 31 et OL 19s8H eqons AW1dSI0 LIDIG-XIS # FYADIA 6-417