TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
DHigh-Performance Static CMOS Technology
25-ns Instruction Cycle Time (40 MHz)
40-MIPS Performance
Low-Power 3.3-V Design
DBased on TMS320C2xx DSP CPU Core
Code-Compatible With F243/F241/C242
Instruction Set and Module Compatible
With F240
DFlash (LF) and ROM (LC) Device Options
LF240xA: LF2407A, LF2406A,
LF2403A, LF2402A
LC240xA: LC2406A, LC2404A,
LC2403A, LC2402A
DOn-Chip Memory
Up to 32K Words x 16 Bits of Flash
EEPROM (4 Sectors) or ROM
Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
Up to 2.5K Words x 16 Bits of
Data/Program RAM
544 Words of Dual-Access RAM
Up to 2K Words of Single-Access RAM
DBoot ROM (LF240xA Devices)
SCI/SPI Bootloader
DUp to Two Event-Manager (EV) Modules
(EVA and EVB), Each Includes:
Two 16-Bit General-Purpose Timers
Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
Three-Phase Inverter Control
Center- or Edge-Alignment of PWM
Channels
Emergency PWM Channel Shutdown
With External PDPINTx Pin
Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
Three Capture Units for Time-Stamping
of External Events
Input Qualifier for Select Pins
On-Chip Position Encoder Interface
Circuitry
Synchronized A-to-D Conversion
Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
Applicable for Multiple Motor and/or
Converter Control
DExternal Memory Interface (LF2407A)
192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
DWatchdog (WD) Timer Module
D10-Bit Analog-to-Digital Converter (ADC)
8 or 16 Multiplexed Input Channels
500-ns MIN Conversion Time
Selectable Twin 8-State Sequencers
Triggered by Two Event Managers
DController Area Network (CAN) 2.0B Module
(LF2407A, 2406A, 2403A)
DSerial Communications Interface (SCI)
D16-Bit Serial Peripheral Interface (SPI)
(LF2407A, 2406A, LC2404A, 2403A)
DPhase-Locked-Loop (PLL)-Based Clock
Generation
DUp to 40 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
DUp to Five External Interrupts (Power Drive
Protection, Reset, Two Maskable Interrupts)
DPower Management:
Three Power-Down Modes
Ability to Power Down Each Peripheral
Independently
DReal-Time JTAG-Compliant Scan-Based
Emulation, IEEE Standard 1149.1 (JTAG)
DDevelopment Tools Include:
Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
Evaluation Modules
Scan-Based Self-Emulation (XDS510)
Broad Third-Party Digital Motor Control
Support
DPackage Options
144-Pin LQFP PGE (LF2407A)
100-Pin LQFP PZ (2406A, LC2404A)
64-Pin TQFP PAG (LF2403A, LC2403A,
LC2402A)
64-Pin QFP PG (2402A)
DExtended Temperature Options (A and S)
A: 40°C to 85°C
S: 40°C to 125°C
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.11990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
2POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
Description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240xA Device Summary 5. . . . . . . . . . . . . . . . .
Functional Block Diagram of the 2407A
DSP Controller 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinouts 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory Map of the 2407A/2406A 29. . . . . . .
Device Reset and Interrupts 30. . . . . . . . . . . . . . . . . . . . .
DSP CPU Core 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240xA Instruction Set 34. . . . . . . . . . . . . . . . . . .
Scan-Based Emulation 34. . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram of the 2407A DSP CPU 35. .
Internal Memory 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Manager Modules (EVA, EVB) 45. . . . . . . . . . . .
Enhanced Analog-to-Digital Converter
(ADC) Module 49. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Interface (SCI) Module 53. . . .
Controller Area Network (CAN) Module 51. . . . . . . . . .
Serial Peripheral Interface (SPI) Module 55. . . . . . . . . .
PLL-Based Clock Module 57. . . . . . . . . . . . . . . . . . . . . .
Digital I/O and Shared Pin Functions 60. . . . . . . . . . . . .
External Memory Interface (LF2407A) 64. . . . . . . . . . . .
Watchdog (WD) Timer Module 65. . . . . . . . . . . . . . . . . .
Development Support 67. . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Support 70. . . . . . . . . . . . . . . . . . . . . . . . .
LF240xA and LC240xA Electrical
Specifications Data 71. . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 71. . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 71. . . . . . . . . . . . .
Migrating From LF240xA (Flash) Devices to
LC240xA (ROM) Devices 110. . . . . . . . . . . . . . . . . . .
Migrating From 240x Devices to 240xA Devices 111. . .
Migrating From LF240x Devices to
LC240xA Devices 112. . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Register Description 113. . . . . . . . . . . . . . . . . .
Mechanical Data 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
3
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
REVISION HISTORY
PAGE HIGHLIGHTS
11 Added the VCCA pin to final note on Table 2
27 Modified LC2403A memory map (Figure 7) in location 8200
50 Added a sentence to the paragraph following Figure 12
59 Added 1/4 W to second column header in Table 10, Loop Filter Component Values With Damping Factor = 2.0
71 Added a note to recommended operating conditions table
72 Added a note to electrical characteristics table
77 Added Figure 23
101 Changed parameter td(WRN) in switching characteristics over recommended operating conditions for an external
memory interface write at 40 MHz [H = 0.5tc(CO)] table
108 Changed MAX value for ICCA in operating characteristics over recommended operating condition ranges table
110 Added note to Table 18
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
4POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
description
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of
digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The
240xA devices offer the enhanced TMS320DSP architectural design of the C2xx core CPU for low-cost,
low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital
motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing
performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary
section for device-specific features.
The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific
price/performance points required by various applications. Flash devices of up to 32K words offer a
cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based
“code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in
on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit
programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash
counterparts.
All 240xA devices offer at least one event manager module which has been optimized for digital motor control
and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM
generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital
conversion. Devices with dual event managers enable multiple motor and/or converter control with a single
240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes
inadvertent pin-triggering by glitches.
The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and
offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. For systems requiring additional communication interfaces, the 2407A, 2406A,
2404A, and 2403A offer a 16-bit synchronous serial peripheral interface (SPI). The 2407A, 2406A, and 2403A
offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize
device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger
supports this family. Numerous third-party developers not only offer device-level development tools, but also
system-level design and development support.
TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
5
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
TMS320x240xA device summary
Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation
of devices.
Table 1. Hardware Features of 240xA Devices
FEATURE LF2407A LF2406A LF2403A LF2402A LC2406A LC2404A LC2403A LC2402A
C2xx DSP Core Yes Yes Yes Yes Yes Yes Yes Yes
Instruction Cycle 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns
MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS
RAM (16 bit word)
Dual-Access
RAM (DARAM) 544 544 544 544 544 544 544 544
RAM (16-bit word) Single-Access
RAM (SARAM) 2K 2K 512 512 2K 1K 512
3.3-V On-chip Flash (16-bit word)
(4 sectors: 4K, 12K, 12K, 4K) 32K 32K 16K 8K
On-chip ROM (16-bit word) 32K 16K 16K 6K
Code Security for On-Chip Flash/ROM Yes Yes Yes Yes Yes Yes Yes Yes
Boot ROM Yes Yes Yes Yes
External Memory Interface Yes ———————
Event Managers A and B (EVA and EVB) EVA,
EVB
EVA,
EVB EVA EVA EVA,
EVB
EVA,
EVB EVA EVA
SGeneral-Purpose (GP) Timers 4 4 2 2 4 4 2 2
SCompare (CMP)/PWM 12/16 12/16 6/8 6/8 12/16 12/16 6/8 6/8
SCapture (CAP)/QEP 6/4 6/4 3/2 3/2 6/4 6/4 3/2 3/2
SInput qualifier circuitry on
PDPINTx, CAPx, QEPx,
XINT1/2, and ADCSOC pins
Yes Yes Yes Yes Yes Yes Yes Yes
SStatus of PDPINTx pin reflected
in COMCONx register Yes Yes Yes Yes Yes Yes Yes Yes
Watchdog Timer Yes Yes Yes Yes Yes Yes Yes Yes
10-Bit ADC Yes Yes Yes Yes Yes Yes Yes Yes
SChannels 16 16 8 8 16 16 8 8
SConversion Time (minimum) 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns
SPI Yes Yes Yes Yes Yes Yes
SCI Yes Yes Yes Yes Yes Yes Yes Yes
CAN Yes Yes Yes Yes Yes
Digital I/O Pins
(Shared) 41 41 21 21 41 41 21 21
External Interrupts 5 5 3 3 5 5 3 3
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Packaging 144-pin
PGE
100-pin
PZ
64-pin
PAG
64-pin
PG
100-pin
PZ
100-pin
PZ
64-pin
PAG
64-pin
PG, PAG
Product Status:
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD PD PD PD PD PD PD PD
Denotes features that are different/new compared to 240x devices.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
6POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
functional block diagram of the 2407A DSP controller
XTAL1/CLKIN
XTAL2
PLLVCCA
PLLF2
PLLF
VSSA
VREFHI
ADCIN08ADCIN15
VCCA
ADCIN00ADCIN07
SCIRXD/IOPA1
SPISIMO/IOPC2
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
VREFLO
Port A(07) IOPA[0:7]
SPICLK/IOPC4
SPISTE/IOPC5
SPISOMI/IOPC3
Port E(07) IOPE[0:7]
Port F(06) IOPF[0:6]
Port C(07) IOPC[0:7]
Port D(0) IOPD[0]
Port B(07) IOPB[0:7]
TDO
TDI
CANRX/IOPC7
TRST
CANTX/IOPC6
EMU1
PDPINTB
TCK
EMU0
TMS
CAP5/QEP4/IOPF0
CAP4/QEP3/IOPE7
PWM7/IOPE1
PWM8/IOPE2
CAP6/IOPF1
PWM10/IOPE4
PWM9/IOPE3
PWM11/IOPE5
PWM12/IOPE6
T4PWM/T4CMP/IOPF3
T3PWM/T3CMP/IOPF2
TDIRB/IOPF4
TCLKINB/IOPF5
DARAM (B0)
256 Words
DARAM (B1)
256 Words
DARAM (B2)
32 Words
C2xx
DSP
Core
PLL Clock
10-Bit ADC
(With Twin
Autosequencer)
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
RS
CLKOUT/IOPE0
XINT1/IOPA2
BIO/IOPC1
MP/MC
TMS2
A0A15
D0D15
TP1
TP2
BOOT_EN/XF
READY
STRB
R/W
RD
PS, DS, IS
VIS_OE
ENA_144
WE
CAP3/IOPA5
PWM1/IOPA6
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
PDPINTA
PWM5/IOPB2
PWM6/IOPB3
PWM3/IOPB0
PWM4/IOPB1
PWM2/IOPA7
T2PWM/T2CMP/IOPB5
T1PWM/T1CMP/IOPB4
TCLKINA/IOPB7
TDIRA/IOPB6
VDD (3.3 V)
VSS
VCCP(5V)
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
SARAM (2K Words)
Flash/ROM
(32K Words:
4K/12K/12K/4K)
External Memory
Interface
Event Manager A
D3 × Capture Input
D6 × Compare/PWM
Output
D2 × GP
Timers/PWM
SCI
SPI
WD
Digital I/O
(Shared With
Other Pins)
CAN
JTAG Port
Event Manager B
D3 × Capture Input
D6 × Compare/PWM
Output
D2 × GP
Timers/PWM
ÈÈÈ
ÈÈÈ
ÈÈÈ
Indicates optional modules.
The memory size and peripheral selection of these modules change for different 240xA devices.
See Table 1 for device-specific details.
W/R / IOPC0
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
7
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pinouts
144
143
142
141
140
139
138
137
136
135
134
RS
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
111
110
109
70
71
72
TMS320LF2407A PGE
PDPINTA
PLLF
TDIRA/IOPB6
XINT2/ADCSOC/IOPD0
CLKOUT/IOPE0
PDPINTB
XTAL1/CLKIN
XTAL2
PLLVCCA
PLLF2
BOOT_EN/XF
CCP
V
TP1
TP2
IOPF6
EMU0
EMU1/OFF
TCK
TDI
TDO
TMS
TMS2
TRST
DS
IS
PS
R/W
W/R/IOPC0
RD
WE
STRB
READY
MP/MC
ENA_144
VIS_OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PLLVCCA
VDD
DD
V
VDD
DD
V
VDDO
DDO
V
DDO
V
VDDO
VDDO
DDO
V
VSS
SS
V
VSS
SS
V
VSSO
SSO
V
SSO
V
VSSO
VSSO
SSO
V
SSO
V
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
CAP3/IOPA5
PWM1/
PWM2/
PWM3/
PWM4/
PWM5/
PWM6/
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
TCLKINA/
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/
PWM7/
PWM8/
PWM9/
PWM10/
PWM11/
PWM12/
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04
ADCIN05
ADCIN06
ADCIN07
ADCIN08
ADCIN09
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
REFHI
V
REFLO
V
CCA
V
SSA
V
CANRX/
CANTX/
SCITXD/IOPA0
SCIRXD/IOPA1
SPICLK/IOPC4
SPISIMO/IOPC2
SPISOMI/IOPC3
SPISTE/IOPC5
XINT1/IOPA2
Bold, italicized pin names indicate pin function after reset.
BOOT_EN is available only on Flash devices.
IOPB7
IOPE6
IOPB3
IOPB2
IOPE5
IOPB1
IOPB0
IOPA7
IOPE4
IOPA6
IOPE3
IOPE2
IOPE1
IOPF1
IOPC7
IOPC6
IOPF5
IOPC1BIO/
PGE PACKAGE
(TOP VIEW)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
8POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pinouts (continued)
SCIRXD/
TMS
TDO
VDDO
VSSO
TDI
PDPINTB
TCK
RS
IOPF6
VDD
VSS
TCLKINB/IOPF5
XTAL2
XTAL1/CLKIN
BOOT_EN/XF§
BIO/IOPC1
VSSA
VCCA
VREFHI
VREFLO
ADCIN08
ADCIN00
ADCIN09
ADCIN01
ADCIN10
TCLKINA/IOPB7
PWM12/IOPE6
PWM6/IOPB3
VSSO
VDDO
PWM5/IOPB2
PWM11/IOPE5
PWM4/IOPB1
VSS
VDD
PWM3/IOPB0
PWM2/IOPA7
PWM10/IOPE4
PWM1/IOPA6
VCCP
PWM9/IOPE3
TP1
PWM8/IOPE2
TP2
PWM7/IOPE1
VSSO
VDDO
CAP6/IOPF1
CANRX/IOPC7
CANTX/IOPC6
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
25242322212019181716151413121110987654321
51525354555657585960616263646566676869707172737475
ADCIN11
ADCIN02
ADCIN12
ADCIN03
ADCIN13
ADCIN04
ADCIN05
ADCIN14
ADCIN06
ADCIN07
ADCIN15
EMU1/
EMU0
CAP4/QEP3/
V
CAP1/QEP1/
CAP5/QEP4/
CAP2/QEP2/
V
CAP3/
/IOPE0
DD
DDO
TRST
TDIRB/
V
T4PWM/T4CMP/
PDPINTA
PLLF2
PLLF
T1PWM/T1CMP/
T2PWM/T2CMP/
XINT2/ADCSOC/
SCITXD/
SPISOMI/
SPISTE/
SPICLK/
DDO
PZ PACKAGE
( TOP VIEW)
TDIRA/
TMS320LC2404A PZ
TMS320LC2406A PZ
TMS320LF2406A PZ
T3PWM/T3CMP/
XINT1/
PLLVCCA
TMS2
VDD
VDDO
VSS
VSS
VSSO
VSSO
VSSO
VSSO
Bold, italicized pin names indicate pin function after reset.
CANTX and CANRX are not available on LC2404A devices.
§BOOT_EN is available only on Flash devices.
On the ROM devices (LC240xA), VCCP is a No Connect (NC).
IOPF4
IOPF3
IOPF2
IOPB6
IOPB4
IOPB5
IOPC0
IOPD0
IOPA2
IOPA0
IOPA1
SPISIMO/IOPC2
IOPC3
IOPC5
IOPC4
IOPE7
CLKOUT
IOPA3
IOPF0
IOPA4
IOPA5
TDIRB/ IOPF4
OFF
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
9
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pinouts (continued)
PAG PACKAGE†‡
(TOP VIEW)
33
16
48
1
49
64 17
32
TMS320LF2403A PAG
TMS320LC2403A PAG
TMS320LC2402A PAG
CLKOUT/IOPE0
CAP3/IOPA5
234567 89101112131415
47 46 45 44 4342 41 40 39 38 37 36 35 34
1863
1962
2061
2160
2259
2358
2457
2556
2655
27
54
2853
2952
3051
3150
CAP2/QEP2/IOPA4
CAP1/QEP1/IOPA3
VSS
V
DD
EMU0
EMU1/ OFF
VSSO
V
DDO
ADCIN07
ADCIN06
ADCIN05
ADCIN04
ADCIN03
ADCIN02
VREFHI
VCCA
VSSA
BOOT_EN/XF§
XTAL1/CLKIN
XTAL2
VSS
VDD
RS
TCK
TDI
TDO
TMS
VREFLO
ADCIN00
ADCIN01CANTX/IOPC6
CANRX/IOPC7
TP2
TP1
VCCP
PWM1/IOPA6
PWM2/IOPA7
PWM3/IOPB0
VDD
VSS
PWM4/IOPB1
PWM5/IOPB2
VDDO
VSSO
PWM6/IOPB3
TCLKINA/IOPB7
TRST
VSSO
V
DDO
PDPINTA
PLLF2
PLLF
PLLVCCA
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
SCIRXD/IOPA1
TMS2
Bold, italicized pin names indicate pin function after reset.
For LC2402A, the following pins are different from what is shown:
Pin 45: IOPC2
Pin 46: IOPC3
Pin 47: IOPC4
Pin 63: IOPC7
Pin 64: IOPC6
§BOOT_EN is available only on flash devices.
On the ROM devices (LC240xA), VCCP is a No Connect (NC).
SPICLK/
SPISOMI/
SPISIMO/
IOPC4
IOPC3
IOPC2
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
10 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pinouts (continued)
VREFHI
VCCA
VSSA
BOOT_EN/XF
XTAL1/CLKIN
XTAL2
VSS
VDD
RS
TCK
TDI
TDO
TMS
VDDO
IOPC6
IOPC7
TP2
TP1
VCCP§
PWM1/IOPA6
PWM2/IOPA7
PWM3/IOPB0
VDD
VSS
PWM4/IOPB1
PWM5/IOPB2
V
ADCIN00
PDPINTA
PLLF2
PLLF
T1PWM/T1CMP/
T2PWM/T2CMP/
SCITXD/
EMU0
TMS2
TCLKINA/
PWM6/
CAP1/QEP1/
CAP2/QEP2/
CAP3/
CLKOUT
ADCIN01
ADCIN02
ADCIN03
ADCIN04
ADCIN05
ADCIN06
ADCIN07
REFLO
SCIRXD/
XINT2/ADCSOC/
PLLVCCA
EMU1/
TRST
TMS320LC2402A PG
TMS320LF2402A PG
VSSO
V
DDO
V
DDO
VSSO
VDD
VSS
IOPB4
IOPB5
IOPD0
IOPA0
IOPA1
IOPC2
IOPC3
IOPC4
IOPB7
IOPB3
/IOPE0
IOPA5
IOPA4
IOPA3
OFF
191 2 3 4 5 6 7 8 9101112131415161718
3351 343550 49 48 47 46 45 44 43 42 41 40 3938 37 36
52
64
53
54
55
56
57
58
59
60
61
62
63
32
20
31
30
29
28
27
26
25
24
23
22
21
PG PACKAGE
(TOP VIEW)
Bold, italicized pin names indicate pin function after reset.
BOOT_EN is available only on Flash devices.
§On the ROM devices (LC240xA), VCCP is a No Connect (NC).
VSSO
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
11
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions
The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A
device. Table 2 lists the signals available in the 240xA generation of devices.
Table 2. LF240xA and LC240xA Pin List and Package Options†‡
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EVENT MANAGER A (EVA)
CAP1/QEP1/IOPA3 83 57 57 4 Capture input #1/quadrature encoder pulse input #1 (EVA) or
GPIO ()
CAP2/QEP2/IOPA4 79 55 55 3 Capture input #2/quadrature encoder pulse input #2 (EVA) or
GPIO ()
CAP3/IOPA5 75 52 52 2 Capture input #3 (EVA) or GPIO ()
PWM1/IOPA6 56 39 39 59 Compare/PWM output pin #1 (EVA) or GPIO ()
PWM2/IOPA7 54 37 37 58 Compare/PWM output pin #2 (EVA) or GPIO ()
PWM3/IOPB0 52 36 36 57 Compare/PWM output pin #3 (EVA) or GPIO ()
PWM4/IOPB1 47 33 33 54 Compare/PWM output pin #4 (EVA) or GPIO ()
PWM5/IOPB2 44 31 31 53 Compare/PWM output pin #5 (EVA) or GPIO ()
PWM6/IOPB3 40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO ()
T1PWM/T1CMP/IOPB4 16 12 12 40 Timer 1 compare output (EVA) or GPIO ()
T2PWM/T2CMP/IOPB5 18 13 13 41 Timer 2 compare output (EVA) or GPIO ()
TDIRA/IOPB6 14 11 11
Counting direction for general-purpose (GP) timer (EVA) or
GPIO. If TDIRA = 1, upward counting is selected. If
TDIRA = 0, downward counting is selected. ()
TCLKINA/IOPB7 37 26 26 49 External clock input for GP timer (EVA) or GPIO. Note that
the timer can also use the internal device clock. ()
EVENT MANAGER B (EVB)
CAP4/QEP3/IOPE7 88 60 60 Capture input #4/quadrature encoder pulse input #3 (EVB) or
GPIO ()
CAP5/QEP4/IOPF0 81 56 56 Capture input #5/quadrature encoder pulse input #4 (EVB) or
GPIO ()
CAP6/IOPF1 69 48 48 Capture input #6 (EVB) or GPIO ()
PWM7/IOPE1 65 45 45 Compare/PWM output pin #7 (EVB) or GPIO ()
PWM8/IOPE2 62 43 43 Compare/PWM output pin #8 (EVB) or GPIO ()
PWM9/IOPE3 59 41 41 Compare/PWM output pin #9 (EVB) or GPIO ()
PWM10/IOPE4 55 38 38 Compare/PWM output pin #10 (EVB) or GPIO ()
PWM11/IOPE5 46 32 32 Compare/PWM output pin #11 (EVB) or GPIO ()
PWM12/IOPE6 38 27 27 Compare/PWM output pin #12 (EVB) or GPIO ()
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
12 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EVENT MANAGER B (EVB) (CONTINUED)
T3PWM/T3CMP/IOPF2 8 7 7 Timer 3 compare output (EVB) or GPIO ()
T4PWM/T4CMP/IOPF3 6 5 5 Timer 4 compare output (EVB) or GPIO ()
TDIRB/IOPF4 2 2 2
Counting direction for general-purpose (GP) timer
(EVB) or GPIO. If TDIRB = 1, upward counting is
selected. If TDIRB = 0, downward counting is
selected. ()
TCLKINB/IOPF5 126 89 89
External clock input for GP timer (EVB) or GPIO.
Note that the timer can also use the internal
device clock. ()
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADCIN00 112 79 79 18 Analog input #0 to the ADC
ADCIN01 110 77 77 17 Analog input #1 to the ADC
ADCIN02 107 74 74 16 Analog input #2 to the ADC
ADCIN03 105 72 72 15 Analog input #3 to the ADC
ADCIN04 103 70 70 14 Analog input #4 to the ADC
ADCIN05 102 69 69 13 Analog input #5 to the ADC
ADCIN06 100 67 67 12 Analog input #6 to the ADC
ADCIN07 99 66 66 11 Analog input #7 to the ADC
ADCIN08 113 80 80 Analog input #8 to the ADC
ADCIN09 111 78 78 Analog input #9 to the ADC
ADCIN10 109 76 76 Analog input #10 to the ADC
ADCIN11 108 75 75 Analog input #11 to the ADC
ADCIN12 106 73 73 Analog input #12 to the ADC
ADCIN13 104 71 71 Analog input #13 to the ADC
ADCIN14 101 68 68 Analog input #14 to the ADC
ADCIN15 98 65 65 Analog input #15 to the ADC
VREFHI 115 82 82 20 ADC analog high-voltage reference input
VREFLO 114 81 81 19 ADC analog low-voltage reference input
VCCA 116 83 83 21 Analog supply voltage for ADC (3.3 V)§
VSSA 117 84 84 22 Analog ground reference for ADC
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
13
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX/IOPC7
CANRX 70 49 63 CAN receive data or GPIO (LF2403A) ()
CANRX/IOPC7 IOPC7 70 49 49 63 GPIO only (2402A) ()
CANTX/IOPC6
CANTX 72 50 64 CAN transmit data or GPIO (LF2403A) ()
CANTX/IOPC6 IOPC6 72 50 50 64 GPIO only (2402A) ()
SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO ()
SCIRXD/IOPA1 26 18 18 44 SCI asynchronous serial port receive data or or
GPIO ()
SPICLK/IOPC4
SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) ()
SPICLK/IOPC4 IOPC4 35 24 24 47 GPIO only (2402A) ()
SPISIMO/IOPC2
SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) ()
SPISIMO/IOPC2 IOPC2 30 21 21 45 GPIO only (2402A) ()
SPISOMI/IOPC3
SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) ()
SPISOMI/IOPC3 IOPC3 32 22 22 46 GPIO only (2402A) ()
SPISTE/IOPC5
SPISTE 33 23 23
SPI slave transmit enable (optional) or GPIO ()
SPISTE/IOPC5 IOPC5 33 23 23 SPI slave transmit-enable (optional) or GPIO ()
EXTERNAL INTERRUPTS, CLOCK
RS 133 93 93 28
Device Reset (in) and Watchdog Reset (out).
Device reset. RS causes the device to terminate execution
and to set PC = 0. When RS is brought to a high level,
execution begins at location 0x0000 of program memory.
This pin is driven low by the DSP when a watchdog reset
occurs. During watchdog reset, the RS pin will be driven
low for the watchdog reset duration of 128 CLKIN cycles.
The output buffer of this pin is an open-drain with an
internal pullup (20 µA, typical). It is recommended that this
pin be driven by an open-drain device. ()
PDPINTA 7 6 6 36
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTA is a falling-edge-sensitive interrupt. ()
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
14 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK (CONTINUED)
XINT1/IOPA2 23 16 16
External user interrupt 1 or GPIO. Both XINT1 and XINT2
are edge-sensitive. The edge polarity is
programmable. ()
XINT2/ADCSOC/IOPD0 21 15 15 42
External user interrupt 2 and ADC start of conversion or
GPIO. External “start-of-conversion” input for ADC/GPIO.
Both XINT1 and XINT2 are edge-sensitive. The edge
polarity is programmable. ()
CLKOUT/IOPE0 73 51 51 1
Clock output or GPIO. This pin outputs either the CPU clock
(CLKOUT) or the watchdog clock (WDCLK). The selection
is made by the CLKSRC bit (bit 14) of the system control
and status register (SCSR). This pin can be used as a GPIO
if not used as a clock output pin. ()
PDPINTB 137 95 95
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVB) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTB is a falling-edge-sensitive interrupt. ()
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
XTAL1/CLKIN 123 87 87 24
PLL oscillator input pin. Crystal input to PLL/clock source
input to PLL. XTAL1/CLKIN is tied to one side of a reference
crystal.
XTAL2 124 88 88 25
Crystal output. PLL oscillator output pin. XTAL2 is tied to
one side of a reference crystal. This pin goes in the
high-impedance state when EMU1/OFF is active low.
PLLVCCA 12 10 10 39 PLL supply (3.3 V)
IOPF6 131 92 92 General-purpose I/O ()
BOOT
_
EN /
BOOT_EN 121 86 23
Boot ROM enable, GPO, XF. This pin will be sampled as
input (BOOT_EN) to update SCSR2.3 (BOOT_EN bit)
durin
g
reset and then driven as an out
p
ut si
g
nal for XF. After
BOOT
_
EN /
XF
XF 121 86 86 23
during reset and then driven as an output signal for XF
.
After
reset, XF is driven high. ROM devices do not have boot
ROM, hence, no BOOT_EN modes. The BOOT_EN pin
must be driven with a passive circuit only. ()
PLLF 11 9 9 38 PLL loop filter input 1
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
15
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)
PLLF2 10 8 8 37 PLL loop filter input 2
VCCP (5V) 58 40 40 60
Flash programming voltage pin. This pin must be connected to
a 5-V supply for Flash programming. The Flash cannot be
programmed if this pin is connected to GND. When not
programming the Flash (i.e., during normal device operation),
this pin can either be left connected to the 5-V supply or it can
be tied to GND. This pin must not be left floating at any time. Do
not use any current-limiting resistor in series with the 5-V supply
on this pin. This pin is a “no connect” (NC) on ROM parts (i.e.,
this pin is not connected to any circuitry internal to the device).
Connecting this pin to 5 V or leaving it open makes no difference
on ROM parts.
TP1 60 42 42 61 Test pin 1. Do not connect.
TP2 63 44 44 62 Test pin 2. Do not connect.
BIO/IOPC1 119 85 85
Branch control input. BIO is polled by the BCND pma,BIO
instruction. If BIO is low, a branch is executed. If BIO is not used,
it should be pulled high. This pin is configured as a branch
control input by all device resets. It can be used as a GPIO, if
not used as a branch control input. ()
EMULATION AND TEST
EMU0 90 61 61 7
Emulator I/O #0 with internal pullup. When TRST is driven high,
this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan. ()
EMU1/OFF 91 62 62 8
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST
is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as an input/output through the
JTAG scan. When TRST is driven low, this pin is configured as
OFF. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF is used exclusively for
testing and emulation purposes (not for multiprocessing
applications). Therefore, for the OFF condition, the following
apply:
TRST = 0
EMU0 = 1
EMU1/OFF = 0 ()
TCK 135 94 94 29 JTAG test clock with internal pullup ()
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately
for proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
16 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EMULATION AND TEST (CONTINUED)
TDI 139 96 96 30
JTAG test data input (TDI) with internal pullup. TDI
is clocked into the selected register (instruction or
data) on a rising edge of TCK. ()
TDO 142 99 99 31
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge of
TCK. ()
TMS 144 100 100 32
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK. ()
TMS2 36 25 25 48
JTAG test-mode select 2 (TMS2) with internal
pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK. Used for
test and emulation only. This pin can be left
unconnected in user applications. If the PLL bypass
mode is desired, TMS2, TMS, and TRST should be
held low during reset. ()
TRST 1 1 1 33
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. ()
NOTE: Do not use pullup resistors on TRST; it has
an internal pulldown device. TRST is an active high
test pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST may be left floating. In other
instances, an external pulldown resistor is highly
recommended. The value of this resistor should be
based on drive strength of the debugger pods
applicable to the design. A 2.2-k resistor generally
offers adequate protection. Since this is
applicationspecific, it is recommended that each
target board be validated for proper operation of the
debugger and the application. (I )
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
17
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS
DS 87
Data space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
IS 82
I/O space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
PS 84
Program space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
R/W 92
Read/write qualifier signal. R/W indicates transfer
direction during communication to an external
device. It is normally in read mode (high), unless
low level is asserted for performing a write
operation. R/W is placed in the high-impedance
state.
W/R / IOPC0
W/R 19
Write/Read qualifier or GPIO. This is an inverted
R/W signal useful for zero-wait-state memory
interface. It is normall
low
unless a memor
write
W/R / IOPC0
IOPC0 19 14 14
.
,
operation is performed. See Table 12, Port C
section, for reset note regarding LF2406A and
LF2402A. ()
RD 93
Read-enable strobe. Read-select indicates an
active, external read cycle. RD is active on all
external program, data, and I/O reads. RD is
placed in the high-impedance state.
WE 89
Write-enable strobe. The falling edge of WE
indicates that the device is driving the external
data bus (D15D0). WE is active on all external
program, data, and I/O writes. WE is placed in the
high-impedance state.
STRB 96
External memory access strobe. STRB is always
high unless asserted low to indicate an external
bus cycle. STRB is active for all off-chip
accesses. STRB is placed in the high-impedance
state.
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
18 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
READY 120
READY is pulled low to add wait states for external accesses.
READY indicates that an external device is prepared for a bus
transaction to be completed. If the device is not ready, it pulls the
READY pin low. The processor waits one cycle and checks
READY again. Note that the processor performs
READY-detection if at least one software wait state is
programmed. To meet the external READY timing parameters,
the wait-state generator control register (WSGR) should be
programmed for at least one wait state. ()
MP/MC 118
Microprocessor/Microcomputer mode select. If this pin is low
during reset, the device is put in microcomputer mode and
program execution begins at 0000h of internal program memory
(Flash EEPROM). A high value during reset puts the device in
microprocessor mode and program execution begins at 0000h
of external program memory. This line sets the MP/MC bit (bit 2
in the SCSR2 register). ()
ENA_144 122
Active high to enable external interface signals. If pulled low, the
2407A behaves like the 2406A/2403A/2402A—i.e., it has no
external memory and generates an illegal address if DS is
asserted. This pin has an internal pulldown. ()
VIS_OE 97
Visibility output enable (active when data bus is output). This pin
is active (low) whenever the external data bus is driving as an
output during visibility mode. Can be used by external decode
logic to prevent data bus contention while running in visibility
mode.
A0 80 Bit 0 of the 16-bit address bus
A1 78 Bit 1 of the 16-bit address bus
A2 74 Bit 2 of the 16-bit address bus
A3 71 Bit 3 of the 16-bit address bus
A4 68 Bit 4 of the 16-bit address bus
A5 64 Bit 5 of the 16-bit address bus
A6 61 Bit 6 of the 16-bit address bus
A7 57 Bit 7 of the 16-bit address bus
A8 53 Bit 8 of the 16-bit address bus
A9 51 Bit 9 of the 16-bit address bus
A10 48 Bit 10 of the 16-bit address bus
A11 45 Bit 11 of the 16-bit address bus
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
19
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
A12 43 Bit 12 of the 16-bit address bus
A13 39 Bit 13 of the 16-bit address bus
A14 34 Bit 14 of the 16-bit address bus
A15 31 Bit 15 of the 16-bit address bus
D0 127 Bit 0 of 16-bit data bus ()
D1 130 Bit 1 of 16-bit data bus ()
D2 132 Bit 2 of 16-bit data bus ()
D3 134 Bit 3 of 16-bit data bus ()
D4 136 Bit 4 of 16-bit data bus ()
D5 138 Bit 5 of 16-bit data bus ()
D6 143 Bit 6 of 16-bit data bus ()
D7 5 Bit 7 of 16-bit data bus ()
D8 9 Bit 8 of 16-bit data bus ()
D9 13 Bit 9 of 16-bit data bus ()
D10 15 Bit 10 of 16-bit data bus ()
D11 17 Bit 11 of 16-bit data bus ()
D12 20 Bit 12 of 16-bit data bus ()
D13 22 Bit 13 of 16-bit data bus ()
D14 24 Bit 14 of 16-bit data bus ()
D15 27 Bit 15 of 16-bit data bus ()
POWER SUPPLY
29 20 20 6
V#
50 35 35 27
Core supply 3 3 V Digital logic supply voltage
VDD#
86 59 59 56 Core supply +3.3 V. Digital logic supply voltage.
129 91 91
4 4 4 10
42 30 30 35
V#
67 47 47 52 I/O buffer suppl
y
+3.3 V. Di
g
ital lo
g
ic and buffer suppl
y
VDDO#
77 54 54
I/O buffer supply +3
.
3 V
.
Digital logic and buffer supply
voltage.
95 64 64
141 98 98
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
20 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
PIN NAME LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
POWER SUPPLY (CONTINUED)
28 19 19 5
V#
49 34 34 26
Core ground Digital logic ground reference
VSS#
85 58 58 55 Core ground. Digital logic ground reference.
128 90 90
3 3 3 9
41 29 29 34
66 46 46 51
VSSO#76 53 53 I/O buffer ground. Digital logic and buffer ground reference.
VSSO
94 63 63
I/O buffer ground. Digital logic and buffer ground reference.
125 97 97
140
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: Internal pullup Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
21
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Reserved
0000
Hex Program
On-Chip Flash Memory (Sectored) if MP/MC = 0
External Program Memory if MP/MC = 1
7FFF
8000
0000
005F
0060
Hex Data
Memory-Mapped
Registers/Reserved Addresses
007F
0080
On-Chip DARAM B2
01FF
Illegal
02FF
0300
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
03FF
0400
On-Chip DARAM (B1)
07FF
0800
Reserved
6FFF
7000
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
7FFF
8000
External
0000
Hex I/O
FEFF
FF00
FF0E
FF0F
Reserved
External
FFFF
FEFF
FF00
FDFF
FE00
External
On-Chip DARAM (B0) (CNF = 1)
External (CNF = 0)
FFFF
FFFE
Wait-State Generator Control
Register (On-Chip)
FF10
Flash Control Mode Register
SARAM (See Table 1 for details.)
FFFF
SARAM (2K)
Internal (PON = 1)
External (PON=0)
87FF
8800
0FFF
1000
3FFF
Flash Sector 1 (12K)
Flash Sector 2 (12K)
Flash Sector 3 (4K)
4000
6FFF
7000
0FFF
1000
0200
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
SARAM (2K)
Internal (DON = 1)
Reserved (DON=0)
ÉÉÉ
ÉÉÉ
ÈÈÈ
ÈÈÈ
Reserved or Illegal
Flash Sector 0 (4K)
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved (CNF = 1)
External (CNF = 0)
Reserved
00FF
0100
Illegal
04FF
0500
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 000000FF in the program space will be occupied by boot ROM.
Addresses 0040h0043h in on-chip program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved when
CNF = 1.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 1. TMS320LF2407A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
22 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Reserved
On-Chip Flash Memory (Sectored)
0000
005F
0060
Hex Data
Memory-Mapped
Registers/Reserved Addresses
007F
0080
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
01FF
0200
Illegal
02FF
0300
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
03FF
0400
On-Chip DARAM (B1)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
07FF
0800
Illegal
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
SARAM (2K)
Internal (DON = 1)
Reserved (DON = 0)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
6FFF
7000
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
7FFF
8000
Illegal
0000
Hex I/O
FEFF
FF00
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
FF0E
FF0F
Reserved
Illegal
FFFF
FFFE
Reserved
FF10
Flash Control Mode Register
ÉÉÉ
ÉÉÉ
SARAM (See Table 1 for details.)
FFFF
0FFF
1000
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
Hex Program
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
On-Chip DARAM (B0) (CNF = 1)
External (CNF = 0)
SARAM (2K)
Internal (PON = 1)
Reserved (PON=0)
87FF
8800
Flash Sector 3 (4K)
6FFF
7000
Illegal
ÈÈÈ
ÈÈÈ
Reserved or Illegal
0000
0FFF
1000
3FFF
Flash Sector 1 (12K)
Flash Sector 2 (12K)
Flash Sector 0 (4K)
4000
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
Reserved
00FF
0100
Reserved
04FF
0500
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 000000FF in the program space will be occupied by boot ROM.
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 2. TMS320LF2406A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
23
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Reserved
On-Chip Flash Memory (Sectored)
0000
005F
0060
Hex Data
Memory-Mapped
Registers/Reserved Addresses
007F
0080
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
01FF
0200
Illegal
02FF
0300
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
03FF
0400
On-Chip DARAM (B1)
07FF
0800
Reserved
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
6FFF
7000
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
7FFF
8000
Illegal
0000
Hex I/O
FEFF
FF00
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
FF0E
FF0F
Reserved
Illegal
FFFF
FFFE
FF10
Flash Control Mode Register
FFFF
0FFF
1000
Reserved
Reserved
0000
Program
FFFF
FEFF
FF00
FDFF
FE00
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
0FFF
Hex
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
Illegal
Flash Sector 0 (4K)
Flash Sector 1 (12K)
Reserved
87FF
8800
4000
Reserved
1000
3FFF
ÈÈÈ
ÈÈÈ
Reserved or Illegal
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
81FF
8200
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
09FF
0A00
ÉÉÉ
ÉÉÉ
SARAM (See Table 1 for details.)
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
0100
00FF
Illegal
04FF
0500
Reserved
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 000000FF in the program space will be occupied by boot ROM.
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 3. TMS320LF2403A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
24 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Reserved
On-Chip Flash Memory (Sectored)
0000
005F
0060
Hex Data
Memory-Mapped
Registers/Reserved Addresses
007F
0080
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
01FF
0200
Illegal
02FF
0300
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
03FF
0400
On-Chip DARAM (B1)
07FF
0800
Reserved
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
6FFF
7000
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
7FFF
8000
Illegal
0000
Hex I/O
FEFF
FF00
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
FF0E
FF0F
Reserved
Illegal
FFFF
FFFE
FF10
Flash Control Mode Register
FFFF
0FFF
1000
Reserved
Reserved
0000
Program
FFFF
FEFF
FF00
FDFF
FE00
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
0FFF
Hex
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
Illegal
Flash Sector 0 (4K)
Flash Sector 1 (4K)
Reserved
87FF
8800
2000
Reserved
1000
1FFF
ÈÈÈ
ÈÈÈ
Reserved or Illegal
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
81FF
8200
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
09FF
0A00
ÉÉÉ
ÉÉÉ
SARAM (See Table 1 for details.)
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
0100
00FF
Illegal
04FF
0500
Reserved
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 000000FF in the program space will be occupied by boot ROM.
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 4. TMS320LF2402A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
25
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Illegal
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Illegal
On-Chip ROM (32K)
Program Hex Data
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Illegal
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Reserved
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
SARAM (2K)
Internal (DON = 1)
Reserved (DON = 0)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
ÉÉÉ
ÉÉÉ
SARAM (See Table 1 for details.)
On-Chip ROM
ÈÈÈ
ÈÈÈ
Reserved or Illegal
0000
Hex
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
0000
005F
0060
007F
0080
01FF
0200
02FF
0300
03FF
0400
07FF
0800
6FFF
7000
7FFF
8000
FFFF
0FFF
1000
SARAM (2K)
Internal (PON = 1)
Reserved (PON = 0)
87FF
8800
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
Reserved
00FF
0100
Illegal
04FF
0500
Reserved
Reserved
7FC0
7FBF
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 5. TMS320LC2406A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
26 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
Reserved
Program Hex Data
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Reserved
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
SARAM (1K)
Internal (DON = 1)
Reserved (DON = 0)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, I/O, Interrupts)
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
ÉÉ
ÉÉ
SARAM (See Table 1 for details.)
On-Chip ROM
ÈÈ
ÈÈ
Reserved or Illegal
0000
Hex
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
83FF
8400
0000
005F
0060
007F
0080
01FF
0200
02FF
0300
03FF
0400
07FF
0800
6FFF
7000
7FFF
8000
FFFF
0BFF
0C00
SARAM (1K)
Internal (PON = 1)
Reserved (PON = 0)
Reserved
3FFF
4000
On-Chip ROM (16K)
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
00FF
0100 Reserved
Illegal
04FF
0500
Reserved
3FBF
3FC0
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 6. TMS320LC2404A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
27
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
On-Chip ROM
0000
005F
0060
Hex Data
Memory-Mapped
Registers/Reserved Addresses
007F
0080
On-Chip DARAM B2
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
01FF
0200
Illegal
02FF
0300
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
03FF
0400
On-Chip DARAM (B1)
07FF
0800
Reserved
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
6FFF
7000
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
7FFF
8000
Illegal
FFFF
0FFF
1000
Reserved
0000
Program
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
Hex
7FFF
8000
FFFF
FEFF
FF00
FDFF
FE00
Reserved
On-chip ROM (16K)
4000
3FFF
ÈÈÈ
ÈÈÈ
Reserved or Illegal
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
81FF
8200
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
09FF
0A00
ÉÉÉ
ÉÉÉ
SARAM (See Table 1 for details.)
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
0100
00FF
Illegal
04FF
0500
Reserved
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Reserved
Reserved
3FCO
3FBF
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 7. TMS320LC2403A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
28 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
memory maps (continued)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
Reserved
On-Chip ROM (6K)
Program Hex Data
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
On-Chip ROM
ÈÈÈ
ÈÈÈ
Reserved or Illegal
0000
Hex
8000
FFFF
FEFF
FF00
FDFF
FE00
87FF
8800
0000
005F
0060
007F
0080
01FF
0200
02FF
0300
03FF
0400
04FF
0800
6FFF
7000
7FFF
8000
FFFF
0FFF
1000
7FFF Reserved
Reserved
Reserved
Interrupt Vectors (0000003Fh)
Reserved (00400043h)
User code begins at 0044h
Reserved
00FF
Reserved
0100
0500
07FF
Illegal
17C0
17BF
Reserved
17FF
1800
Addresses 0040h0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00hFEFFh and FF00hFFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00hFEFFh are referred to as reserved.
§When CNF = 0, addresses 0100h01FFh and 0200h02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h01FFh are referred to as reserved.
Addresses 0300h03FFh and 0400h04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h04FFh are referred to as reserved.
Figure 8. TMS320LC2402A Memory Map
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
29
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral memory map of the 2407A/2406A
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Reserved
Reserved
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
70C070FF
General-Purpose
Timer Registers
Flag Registers
Event Manager EVB
Deadband Registers
Compare, PWM, and
Interrupt Mask, Vector, and
Capture and QEP Registers
75007508
75117519
75207529
752C7531
7532753F
7432743F
742C7431
74207429
74117419
74007408
Illegal
Flag Registers
Interrupt Mask, Vector and
Capture and QEP Registers
Deadband Registers
Compare, PWM, and
Timer Registers
General-Purpose
Event Manager EVA
710F71FF
7100710E
70A070BF
7090709F
7080708F
7070707F
7060706F
7050705F
7040704F
7030703F
7020702F
7010701F
7000700F
CAN Control Registers
ADC Control Registers
Digital I/O Control Registers
External-Interrupt Registers
SCI
SPI
Watchdog Timer Registers
Control Registers
System Configuration and
Hex
Hex
005F
0007
0006
0005
0004
0003
0000
and Reserved
Emulation Registers
Interrupt Flag Register
Interrupt-Mask Register
FFFF
77F0
77EF
7540
753F
7500
74FF
7440
743F
7400
73FF
7000
6FFF
1000
07FF
0400
03FF
0300
02FF
0200
01FF
0080
007F
0060
005F
0000
External
Peripheral Frame 3 (PF3)
Peripheral Frame 2 (PF2)
Peripheral Frame 1 (PF1)
On-Chip DARAM B1
On-Chip DARAM B0
Reserved
On-Chip DARAM B2
and Reserved
Memory-Mapped Registers
“Illegal” indicates that access to
these addresses causes a
nonmaskable interrupt (NMI).
ÈÈÈÈ
ÈÈÈÈ
ÈÈÈÈ
Reserved “Reserved” indicates addresses that
are reserved for test.
Available in LF2407A only
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
0100
00FF
Reserved
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
Illegal
0500
04FF
SARAM (2K)
0800
0FFF
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
CAN Mailbox
Illegal 723073FF
7200722F
Illegal
Reserved
Code Security Passwords
Illegal
77F3
77F4
7FFF
8000
Reserved
77FF
7800
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
30 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
device reset and interrupts
The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types
of interrupt sources.
DReset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
DHardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
External interrupts are generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the
CPU interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in
each peripheral and by the CPU IMR, which can mask each maskable interrupt line at the DSP core.
DSoftware-generated interrupts for the LF240xA devices include:
The INTR instruction. This instruction allows initialization of any LF240xA interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only
software activation is provided.
The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to
share the six core level interrupts. Figure 9 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 9) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely
code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x plus additional
interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt
grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
31
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
device reset and interrupts (continued)
CPU
IACK
Addr BusData Bus
PIVR & Logic
PIRQR#
PIACK#
IRQ GEN
Level 6
IRQ GEN
Level 5
IRQ GEN
Level 4
IRQ GEN
Level 3
IRQ GEN
Level 2
IRQ GEN
Level 1
ADCINT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
CAP3INT
CAP2INT
CAP1INT
T2OFINT
T2UFINT
T2CINT
T2PINT
T1OFINT
T1UFINT
T1CINT
T1PINT
CMP3INT
CMP2INT
CMP1INT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
ADCINT
PDPINTB
INT1
INT2
INT3
INT4
INT6
INT5
IMR
IFR
PIE
CAP6INT
CAP5INT
CAP4INT
T4OFINT
T4UFINT
T4CINT
T4PINT
CMP6INT
CMP5INT
CMP4INT
T3OFINT
T3UFINT
T3PINT
T3CINT
PDPINTA
Indicates change with respect to the TMS320F243/F241/C242 data sheets.
XINT1
XINT2
XINT1
XINT2
Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals.
Figure 9. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
32 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
interrupt request structure
Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION IN
PIRQRx AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASK-
ABLE?
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
Reset 1 RSN
0000h N/A N RS pin,
Watchdog
Reset from pin, watchdog
timeout
Reserved 2
0026h N/A N CPU Emulator trap
NMI 3 NMI
0024h N/A N Nonmaskable
Interrupt
Nonmaskable interrupt,
software interrupt only
PDPINTA 4 0.0 0020h Y EVA Power device protection
PDPINTB 5 2.0 0019h Y EVB
Power device protection
interrupt pins
ADCINT 6 0.1 0004h Y ADC ADC interrupt in
high-priority mode
XINT1 7 0.2 0001h Y External
Interrupt Logic External interru
p
t
p
ins in hi
g
h
XINT2 8
INT1
0.3 0011h Y External
Interrupt Logic
External interrupt pins in high
priority
SPIINT 9 INT1
0002h
0.4 0005h Y SPI SPI interrupt pins in high priority
RXINT 10
0002h
0.5 0006h Y SCI SCI receiver interrupt in
high-priority mode
TXINT 11 0.6 0007h Y SCI SCI transmitter interrupt in
high-priority mode
CANMBINT 12 0.7 0040 Y CAN CAN mailbox in high-priority
mode
CANERINT 13 0.8 0041 Y CAN CAN error interrupt in
high-priority mode
CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt
CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt
CMP3INT 16 0.11 0023h Y EVA Compare 3 interrupt
T1PINT 17
INT2
0.12 0027h Y EVA Timer 1 period interrupt
T1CINT 18 INT2
0004h
0.13 0028h Y EVA Timer 1 compare interrupt
T1UFINT 19
0004h
0.14 0029h Y EVA Timer 1 underflow interrupt
T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt
CMP4INT 21 2.1 0024h Y EVB Compare 4 interrupt
CMP5INT 22 2.2 0025h Y EVB Compare 5 interrupt
CMP6INT 23 2.3 0026h Y EVB Compare 6 interrupt
T3PINT 24 2.4 002Fh Y EVB Timer 3 period interrupt
T3CINT 25 2.5 0030h Y EVB Timer 3 compare interrupt
T3UFINT 26 2.6 0031h Y EVB Timer 3 underflow interrupt
T3OFINT 27 2.7 0032h Y EVB Timer 3 overflow interrupt
See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
New peripheral interrupts and vectors with respect to the F243/F241 devices.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
33
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
interrupt request structure (continued)
Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors (Continued)
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION IN
PIRQRx AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASK-
ABLE?
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt
T2CINT 29 1.1 002Ch Y EVA Timer 2 compare interrupt
T2UFINT 30 1.2 002Dh Y EVA Timer 2 underflow interrupt
T2OFINT 31 INT3 1.3 002Eh Y EVA Timer 2 overflow interrupt
T4PINT 32
INT3
0006h 2.8 0039h Y EVB Timer 4 period interrupt
T4CINT 33 2.9 003Ah Y EVB Timer 4 compare interrupt
T4UFINT 34 2.10 003Bh Y EVB Timer 4 underflow interrupt
T4OFINT 35 2.11 003Ch Y EVB Timer 4 overflow interrupt
CAP1INT 36 1.4 0033h Y EVA Capture 1 interrupt
CAP2INT 37 1.5 0034h Y EVA Capture 2 interrupt
CAP3INT 38 INT4 1.6 0035h Y EVA Capture 3 interrupt
CAP4INT 39
INT4
0008h 2.12 0036h Y EVB Capture 4 interrupt
CAP5INT 40 2.13 0037h Y EVB Capture 5 interrupt
CAP6INT 41 2.14 0038h Y EVB Capture 6 interrupt
SPIINT 42 1.7 0005h Y SPI SPI interrupt (low priority)
RXINT 43 1.8 0006h Y SCI SCI receiver interrupt
(low-priority mode)
TXINT 44 INT5
000Ah
1.9 0007h Y SCI SCI transmitter interrupt
(low-priority mode)
CANMBINT 45
000Ah
1.10 0040h Y CAN CAN mailbox interrupt
(low-priority mode)
CANERINT 46 1.11 0041h Y CAN CAN error interrupt
(low-priority mode)
ADCINT 47 1.12 0004h Y ADC ADC interrupt
(low priority)
XINT1 48 INT6
000Ch 1.13 0001h Y External
Interrupt Logic External interrupt pins
XINT2 49
000Ch
1.14 0011h Y External
Interrupt Logic
External interrupt pins
(low-priority mode)
Reserved 000Eh N/A Y CPU Analysis interrupt
TRAP N/A 0022h N/A N/A CPU TRAP instruction
Phantom
Interrupt
Vector
N/A N/A 0000h N/A CPU Phantom interrupt vector
INT8INT16 N/A 0010h0020h N/A N/A CPU
Software interrupt vectors
INT20INT31 N/A 00028h0003Fh N/A N/A CPU Software interrupt vectors
See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
New peripheral interrupts and vectors with respect to the F243/F241 devices.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
34 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
DSP CPU core
The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a
four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See
the functional block diagram of the 240xA DSP CPU for more information.
TMS320x240xA instruction set
The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The
scan chain of these devices is useful for emulation function only.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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functional block diagram of the 2407A DSP CPU
32
16
Data Bus
16
OSCALE (07)
D15D0
A15A0
16
1616
32
32
ACCL(16)ACCH(16)C
32
CALU(32)
3232
MUX
ISCALE (016)
16
MUX
PREG(32)
Multiplier
TREG0(16)
MUX
16
16
MUX
B1 (256 ×16)
B2 (32 ×16)
DARAM
B0 (256 ×16)
DARAM
7
LSB
from
IR
MUX
DP(9)
9
9
MUX
1616
ARAU(16)
16
3
3
3
3
ARB(3)
ARP(3)
Program Bus
16
16
16
16
AR7(16)
AR6(16)
AR5(16)
AR3(16)
AR2(16)
AR1(16)
AR0(16)
Stack 8 ×16
PC
MUX
WE
RD
16
XTAL2
CLKOUT
XTAL1
2
XINT[12]
MP/MC
RS
XF
READY
STRB
R/W
PS
DS
IS
Control
Data Bus
Program Bus
Data Bus
AR4(16)
16
MUXMUX
Data/Prog
16
PSCALE (6,0,1,4)
16
Data
32
16
16
16
16
16
FLASH EEPROM/
ROM
MUX
MUX
NPAR
PAR MSTACK
Program Control
(PCTRL)
Memory Map
Register
IMR (16)
IFR (16)
GREG (16)
16
Program Bus
NOTES: A. See Table 4 for symbol descriptions.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. See the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
36 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
240xA legend for the internal hardware
Table 4. Legend for the 240xA DSP CPU Internal Hardware
SYMBOL NAME DESCRIPTION
ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
ARAU Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs
AUX
REGS
Auxiliary Registers
07
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
C Carry
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
CALU Central Arithmetic
Logic Unit
32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
DARAM Dual-Access RAM
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 030003FF and 0060007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.
DP Data Memory
Page Pointer
The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
GREG
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space. Since the global memory space is not used in
the 240xA devices, this register is reserved.
IMR Interrupt Mask
Register IMR individually masks or enables the six core-level interrupts.
IFR Interrupt Flag
Register
The 6-bit IFR indicates that the TMS320Lx240xA has latched an interrupt from one of the six maskable
interrupts.
INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.
ISCALE Input Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
MPY Multiplier 16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MSTACK Micro Stack MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MUX Multiplexer Multiplexes buses to a common input
NPAR Next Program
Address Register NPAR holds the program address to be driven out on the PAB in the next cycle.
OSCALE
Output
Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
bus (DWEB).
PAR Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PC Program Counter PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PCTRL Program
Controller PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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240xA legend for the internal hardware (continued)
Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued)
SYMBOL NAME DESCRIPTION
PREG Product Register 32-bit register holds results of 16 × 16 multiply
PSCALE Product-Scaling
Shifter
0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.
STACK Stack STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.
TREG Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 10 shows the organization of status registers ST0 and ST1, indicating all status bits
contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status
register field definitions.
15 13 12 11 10 9 8 0
ST0 ARP OV OVM 1 INTM DP
15 131211109876543210
ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM
Figure 10. Organization of Status Registers ST0 and ST1
Table 5. Status Register Field Definitions
FIELD FUNCTION
ARB Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
ARP
Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
C
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
CNF
On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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38 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
status and control registers (continued)
Table 5. Status Register Field Definitions (Continued)
FIELD FUNCTION
DP Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory
address of 16 bits. DP can be modified by the LST and LDP instructions.
INTM
Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable
RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when
a maskable interrupt trap is taken.
OV Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.
OVM
Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset
this bit, respectively. LST can also be used to modify the OVM.
PM
Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits
and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS.
SXM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction
and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.
TC
Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most
significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute based on the condition of TC.
XF XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset
by the CLRC XF instruction. XF is set to 1 by reset.
central processing unit
The TMS320x240xA central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel
multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the
outputs of both the accumulator and the multiplier. This section describes the CPU components and their
functions. The functional block diagram shows the components of the CPU.
input scaling shifter
The TMS320x240xA provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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multiplier
The TMS320x240xA devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an
unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated
with the multiplier, as follow:
D16-bit temporary register (TREG) that holds one of the operands for the multiplier
D32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.
Table 6. PSCALE Product-Shift Modes
PM SHIFT DESCRIPTION
00 No shift Product feed to CALU or data bus with no shift
01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
10 Left 4 Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when
using the multiply-by-a-13-bit constant
11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
40 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
multiplier (continued)
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits
to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This
is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot
be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product
register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high
half, then, is loaded using the LPH instruction.
central arithmetic logic unit
The TMS320x240xA central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate
it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).
Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from
immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean
operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320x240xA devices support floating-point operations for applications requiring a large dynamic range.
The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator
by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result
in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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central arithmetic logic unit (continued)
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing,
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 1631), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 015). When the postscaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The 240xA provides a register file containing eight auxiliary registers (AR0AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers also can be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary
register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0
register can be performed. As a result, accessing tables of information does not require the CALU for address
manipulation; therefore, the CALU is free for other operations in parallel.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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internal memory
The TMS320x240xA devices are configured with the following memory modules:
DDual-access random-access memory (DARAM)
DSingle-access random-access memory (SARAM)
DFlash
DROM
DBoot ROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the 240xA devices. The 240xA DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 240xA runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 240xA architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY
line or on-chip software wait-state generator can be used to interface the 2407A to slower, less expensive
external memory.
single-access RAM (SARAM)
There are 2K words × 16 bits of SARAM on some of the 240xA devices. The PON and DON bits select SARAM
(2K) mapping in program space, data space, or both. See Table 19 for details on the SCSR2 register and the
PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data
spaces. The SARAM (starting at 8000h in program memory) is accessible in external memory space (for 2407A
only), if the on-chip SARAM is not enabled.
flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2407A incorporates one 32K 16-bit
Flash EEPROM module in program space. The Flash module has multiple sectors that can be individually
protected while erasing or programming. The sector size is non-uniform and partitioned as 4K/12K/12K/4K
sectors.
Unlike most discrete Flash memory, the LF240xA Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at VCCP pin only) the array. The Flash runs
at zero wait state while the device is powered at 3.3 V.
ROM
The LC240xA devices contain mask-programmable ROM located in program memory space. Customers can
arrange to have this ROM programmed with contents unique to any particular application. See Table 1 for the
ROM memory capacity of each LC240xA device.
See Table 1 for device-specific features.
IEEE Standard 1149.11990, IEEE Standard Test Access Port.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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boot ROM (LF240xA only)
Boot ROM is a 256-word ROM memory-mapped in program space 000000FF. This ROM will be enabled if the
BOOT_EN pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN
pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.3 bit and disabled by writing 1 to
this bit.
The boot ROM has a generic bootloader to transfer code through SCI or SPI ports. The incoming code should
disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not
be enabled.
The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The
SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
DIf the SCITXD pin is pulled low, the PLL multiplier is set to 2.
DIf the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default)
DIf the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in
a CPU clock speed of greater than 40 MHz, the maximum rated speed.
Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI.
See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357) for more details about the bootloader operation.
flash/ROM security
240xA devices incorporate a security feature that prevents external access to program memory. This feature
is useful in preventing unauthorized duplication of proprietary code.
If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken:
1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word
“dummy” indicates that the destination address of this read is insignificant.
NOTE: Step 2 is not required if 40h43h contain 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh.
2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h,
77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h,
41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle
after the last instruction that unsecures the part.
Code Security Module Disclaimer
The Code Security Module (“CSM”) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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44 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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PERIPHERALS
The integrated peripherals of the TMS320x240xA are described in the following subsections:
DTwo event-manager modules (EVA, EVB)
DEnhanced analog-to-digital converter (ADC) module
DController area network (CAN) module
DSerial communications interface (SCI) module
DSerial peripheral interface (SPI) module
DPLL-based clock module
DDigital I/O and shared pin functions
DExternal memory interfaces (LF2407A only)
DWatchdog (WD) timer module
event manager modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 7 shows the module and signal names
used. Table 7 shows the features and functionality available for the event-manager modules and highlights EVA
nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ.
Table 7. Module and Signal Names for EVA and EVB
EVENT MANAGER MODULES
EVA EVB
EVENT MANAGER MODULES MODULE SIGNAL MODULE SIGNAL
GP Timers Timer 1
Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
Timer 3
Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare Units
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP QEP1
QEP2
QEP1
QEP2
QEP3
QEP4
QEP3
QEP4
External Inputs Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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event manager modules (EVA, EVB) (continued)
Data Bus ADDR Bus Reset INT2,3,4
Output
Logic
PWM1
PWM6
T2PWM/
T2CMP
16
16
16
16
16
16
16
16
16
16
16
33 3
ADC Start of
Conversion
QEP
Circuit
ClockDIR
16
16
2
Prescaler
TDIRA
TCLKINA
CLKOUT
(Internal)
T1CON[8,9,10]T1CON[4,5]
T2CON[8,9,10]
T2CON[4,5]
TCLKINA
TDIRA
Output
Logic
Deadband
Units
SVPWM
State
Machine
2
2
CAPCONA[14,13]
Capture Units
MUX
GP Timer 1
Full-Compare
Units
GP Timer 2
Compare
GP Timer 2
EV Control Registers
and Control Logic
GP Timer 1
Compare
Output
Logic
Clock
240xA DSP Core
3
Prescaler CLKOUT
(Internal)
CAP1/QEP1
CAP3
CAP2/QEP2
T1PWM/
T1CMP
2402A devices do not support external direction control. TDIR is not available.
Figure 11. Event Manager A Block Diagram
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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general-purpose (GP) timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
DA 16-bit timer, up-/down-counter, TxCNT, for reads or writes
DA 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
DA 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
DA 16-bit timer-control register,TxCON, for reads or writes
DSelectable internal or external input clocks
DA programmable prescaler for internal or external clock inputs
DControl and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
DA selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time
base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1
for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare
registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as
needed.
full-compare units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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PWM characteristics
Characteristics of the PWMs are as follows:
D16-bit registers
DProgrammable deadband for the PWM output pairs, from 0 to 12 µs
DMinimum deadband width of 25 ns
DChange of the PWM carrier frequency for PWM frequency wobbling as needed
DChange of the PWM pulse widths within and after each PWM period as needed
DExternal-maskable power and drive-protection interrupts
DPulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
DMinimized CPU overhead using auto-reload of the compare and period registers
DThe PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
DOne 16-bit capture control register, CAPCONx (R/W)
DOne 16-bit capture FIFO status register, CAPFIFOx
DSelection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
DThree 16-bit 2-level-deep FIFO stacks, one for each capture unit
DThree capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs
are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold
at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also
be used as QEP inputs to the QEP circuit.]
DUser-specified transition (rising edge, falling edge, or both edges) detection
DThree maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP16, QEP14, XINT1/2, ADCSOC and
PDPINTA/B pins in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry).
The state of the internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures
that a glitch smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must
hold the pin high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register
controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches.
On the LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA, and XINT2/ADCSOC pins.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
D10-bit ADC core with built-in S/H
D16-channel, MUXed inputs
DAutosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
DSequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
DSixteen result registers (individually addressable) to store conversion values
The digital value of the input analog voltage is derived by:
Digital Value +1024 Input Analog Voltage *VREFLO
VREFHI *VREFLO
Digital Value = 0
Digital Value = 1023
when input VREFLO
when VREFLO < input < VREFHI
when input VREFHI
Note: All fractional values are truncated.
DMultiple triggers as sources for the start-of-conversion (SOC) sequence
S/W software immediate start
EVA Event manager A (multiple event sources within EVA)
EVB Event manager B (multiple event sources within EVB)
Ext External pin (ADCSOC)
DFlexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
DSequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
DEVA and EVB triggers can operate independently in dual-sequencer mode
DSample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The calibration and self-test features are not present in 240xA devices.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the 240xA has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 10-bit ADC module with a total minimum conversion time of 375 ns
(S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules
to service event managers A and B. The two independent 8-channel modules can be cascaded to form a
16-channel module. Although there are multiple input channels and two sequencers, there is only one converter
in the ADC module. Figure 12 shows the block diagram of the 240xA ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the
conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing
allows the system to convert the same channel multiple times, allowing the user to perform oversampling
algorithms. This gives increased resolution over traditional single-sampled conversion results.
Result Registers
EVB
S/W
ADCSOC
EVA
S/W
Sequencer 2
Sequencer 1 SOCSOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
(375 ns MIN)
Module
ADC
10-Bit
Analog MUX
ADCIN00
ADCIN07
ADCIN08
ADCIN15
Figure 12. Block Diagram of the 240xA ADC Module
To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible, traces
leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (such as VCCA, VREFHI, and VSSA) from the
digital supply. Unused ADC inputs should be connected to analog ground for improved accuracy and ESD
protection.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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controller area network (CAN) module
The CAN module is a full-CAN controller designed as a 16-bit peripheral module and supports the following
features:
DCAN specification 2.0B (active)
Standard data and remote frames
Extended data and remote frames
DSix mailboxes for objects of 0- to 8-byte data length
Two receive mailboxes, two transmit mailboxes
Two configurable transmit/receive mailboxes
DLocal acceptance mask registers for mailboxes 0 and 1 and mailboxes 2 and 3
DConfigurable standard or extended message identifier
DProgrammable bit rate
DProgrammable interrupt scheme
DReadable error counters
DSelf-test mode
In this mode, the CAN module operates in a loop-back fashion, receiving its own transmitted message.
The CAN module is a 16-bit peripheral. The accesses are split into the control/status-registers accesses and
the mailbox-RAM accesses.
CAN peripheral registers: The CPU can access the CAN peripheral registers only using 16-bit write accesses.
The CAN peripheral always presents full 16-bit data to the CPU bus during read cycles.
CAN controller architecture
Figure 13 shows the basic architecture of the CAN controller through this block diagram of the CAN Peripherals.
Temporary Receive Buffer
Data ID
CAN Module
Control Logic
CPU Interface/
Memory Management Unit
CAN
Core
Control/Status Registers
Interrupt Logic
Control Bus
Acceptance Filter
Transmit Buffer
RAM 48x16
CANTX
CAN
Transceiver
Matchid
CPU
mailbox 0
mailbox 1
mailbox 2
mailbox 3
mailbox 4
mailbox 5
R
R
T/R
T/R
T
T
CANRX
Figure 13. CAN Module Block Diagram
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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52 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
controller area network (CAN) module (continued)
The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN.
The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and, therefore,
inserts one wait state for the CPU.
Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1)
16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address
bus.
Table 8. 3.3-V CAN Transceivers for the TMS320Lx240xA DSPs
PART NUMBER LOW-POWER MODE INTEGRATED
SLOPE CONTROL Vref PIN TAMARKED AS
SN65HVD230 370 µA standby mode Yes Yes VP230
SN65HVD231 40 nA sleep mode Yes Yes 40°C to 85°CVP231
SN65HVD232 No standby or sleep mode No No
40 C to 85 C
VP232
This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number.
CAN interrupt logic
There are two interrupt requests from the CAN module to the peripheral interrupt expansion (PIE) controller:
the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. Since CAN mailboxes can generate multiple interrupts, the software should
read the CAN_IFR register for every interrupt and prioritize the interrupt service, or else, these multiple
interrupts will not be recognized by the CPU and PIE hardware logic. Each interrupt routine should service all
the interrupt bits that are set and clear them after service.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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serial communications interface (SCI) module
The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
DTwo external pins:
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
DBaud rate programmable to 64K different rates
Up to 2500 Kbps at 40-MHz CPUCLK
DData-word format
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
DFour error-detection flags: parity, overrun, framing, and break detection
DTwo wake-up multiprocessor modes: idle-line and address bit
DHalf- or full-duplex operation
DDouble-buffered receive and transmit functions
DTransmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
DSeparate enable bits for transmitter and receiver interrupts (except BRKDT)
DNRZ (non-return-to-zero) format
DTen SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (70), and the upper byte (158) is read as zeros. Writing to the upper byte has no effect.
Figure 14 shows the SCI module block diagram.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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54 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
serial communications interface (SCI) module (continued)
Internal
Clock
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt
BRKDT
SCICTL1.1
RXRDY
SCIRXST.6
SCICTL1.3 External
Connections
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.0
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
TXINT
SCICCR.6 SCICCR.5
SCITXBUF.70
SCIHBAUD. 15 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 0
SCIRXBUF.70
Receiver-Data
Buffer
Register
SCIRXST.7
PEFE OE
RX Error
RX Error
SCIRXST.4 2
Transmitter-Data
Buffer Register
8
SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
RXINT
SCIPRI.5
SCIPRI.6
SCI Priority Level
Level 5 Int.
Level 1 Int.
Level 5 Int.
Level 1 Int.
1
0
1
0
SCI TX
Priority
SCI RX
Priority
Figure 14. Serial Communications Interface (SCI) Module Block Diagram
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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serial peripheral interface (SPI) module
Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted
into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:
DFour external pins:
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
DTwo operational modes: master and slave
DBaud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK
DData word length: one to sixteen data bits
DFour clocking schemes (controlled by clock polarity and clock phase bits) include:
Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
DSimultaneous receive and transmit operation (transmit function can be disabled in software)
DTransmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
DNine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. Writing to the upper byte has no effect.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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serial peripheral interface (SPI) module (continued)
Figure 15 is a block diagram of the SPI in slave mode.
S
S
Clock
Polarity
Talk
Internal
Clock
456
012
SPI Bit Rate
State Control
SPIRXBUF
Buffer Register
16
Clock
Phase
1230
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 0
SPIBRR.6 0SPICCR.6 SPICTL.3
SPIRXBUF.15 0
SPIDAT.15 0
SPICTL.1
M
S
M
Master/Slave
SPI INT FLAG
SPICTL.0
SPI INT
ENA
SPISTS.7
SPIDAT
Data Register
SPISTS.6
M
S
SPICTL.2
SPI Char
External
Connections
SPISIMO
SPISOMI
SPISTE
SPICLK
SW2
S
M
M
S
SW3
To CPU
M
SW1
SPIPRI.6
SPI Priority
Level 1
INT
1
0
Level 5
INT
SPITXBUF.150
3
16
SPITXBUF
Buffer Register
NOTE A: The diagram is shown in the slave mode.
The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. See the following errata for restrictions
on using the SPISTE pin:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata
(literature number SPRZ002)
TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185)
Figure 15. Four-Pin Serial Peripheral Interface Module Block Diagram
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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SPI slave mode operation in LF2403A
The LF2403A device does not have the SPISTE/IOPC5 pin. (This function is available as an internal signal only.)
The following must be done to put the LF2403A SPI in slave mode:
1. Configure SPISTE/IOPC5 signal for GPIO mode by clearing the MCRB.5 bit.
2. Configure SPISTE/IOPC5 signal as an output (by writing a 1 to bit 13 of PCDATDIR) and drive it low (by
writing a 0 to bit 5 of PCDATDIR). Note that SPISTE/IOPC5 should not be driven low until after the SPI is
configured and taken out of reset.
NOTE: The slave SPISTE/IOPC5 signal must not be driven low until after the master and slave SPI modules
are configured and taken out of reset. The initialization sequence is as follows:
a. The master SPI is configured first and taken out of reset. This ensures that the master SPICLK is
initialized to its appropriate level (high or low, depending on the polarity bit) first, before the slave SPI
starts accepting clock pulses.
b. The slave SPI is configured and taken out of reset.
c. The GPIO/SPI pins of the slave is then configured for SPI operation and the SPISTE/IOPC5 signal is
driven low. This is done after ensuring the correct level of the master SPICLK signal. One method of
doing this would be to read the level of the SPICLK pin through the PCDATDIR register and then
deciding on the appropriate course of action.
d. SPI transmission may commence now. Transmission of data should not be attempted until both master
and slave are configured and the slave SPISTE/IOPC5 signal is driven low.
PLL-based clock module
The 240xA has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 16 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10
for the loop filter component values.
The PLL-based clock module provides two modes of operation:
DCrystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
DExternal clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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58 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
PLL-based clock module (continued)
XTAL2
XTAL1/CLKIN
PLL
XTAL
OSC
CLKOUT
Fin
3-bit
PLL Select
(SCSR1.[11:9])
R1
C1
C2
PLLF
RESONATOR/
CRYSTAL
PLLF2
Cb1
Cb2
Figure 16. PLL Clock Module Block Diagram
Table 9. PLL Clock Selection Through Bits (119) in SCSR1 Register
CLK PS2 CLK PS1 CLK PS0 CLKOUT
000 4 × Fin
001 2 × Fin
010 1.33 × Fin
011 1 × Fin
100 0.8 × Fin
101 0.66 × Fin
110 0.57 × Fin
111 0.5 × Fin
Default multiplication factor after reset is (1,1,1), i.e., 0.5 × Fin.
NOTE:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN used
should not force CLKOUT to exceed the maximum rated device speed. See the “Boot ROM” section
for more details.
external reference crystal clock option
The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown
in Figure 17a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 150 and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF.
NOTE: Lx240xA crystal biasing needs an external 1 M resistor across X1 and X2 pins for reliable operation. See the TMS320LF2407A,
LF2406A, LF2403A, LF2402A DSP Controllers Silicon Errata (literature number SPRZ002) or the TMS320LC2406A, TMS320LC2404A,
TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185) for details on this requirement.
external reference oscillator clock option
The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input
pin unconnected as shown in part b of Figure 17.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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external reference oscillator clock option (continued)
External Clock Signal
(Toggling 0 3.3 V)
Cb1
(see Note A)
XTAL2XTAL1/CLKIN XTAL1/CLKIN XTAL2
Crystal
Cb2
(see Note A)
(a) (b)
NC
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 17. Recommended Crystal/Clock Connection
loop filter
The PLL module uses an external loop filter circuit for jitter minimization. The components for the loop filter
circuit are R1, C1, and C2. The capacitors (C1 and C2) must be non-polarized. This loop filter circuit is connected
between the PLLF and PLLF2 pins (see Figure 16). For examples of component values of R1, C1, and C2 at
a specified oscillator frequency (XTAL1), see Table 10.
Table 10. Loop Filter Component Values With Damping Factor = 2.0
XTAL1/CLKIN FREQUENCY
(MHz) R1 () (±5% TOLERANCE) 1/4 W C1 (µF) (±20% TOLERANCE) C2 (µF) (±20% TOLERANCE)
4 4.7 3.9 0.082
5 5.6 2.7 0.056
6 6.8 1.8 0.039
7 8.2 1.5 0.033
8 9.1 1 0.022
9 10 0.82 0.015
10 11 0.68 0.015
11 12 0.56 0.012
12 13 0.47 0.01
13 15 0.39 0.0082
14 15 0.33 0.0068
15 16 0.33 0.0068
16 18 0.27 0.0056
17 18 0.22 0.0047
18 20 0.22 0.0047
19 22 0.18 0.0039
20 24 0.15 0.0033
low-power modes
The 240xA has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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clock domains
All 240xA-based devices have two clock domains:
1. CPU clock domain consists of the clock for most of the CPU logic
2. System clock domain consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 240xA CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 240xA CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 11). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
Table 11. Low-Power Modes Summary
LOW-POWER MODE
LPMx BITS
SCSR1
[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
FLASH
POWER
EXIT
CONDITION
CPU running normally XX On On On On On On
IDLE1 (LPM0) 00 Off On On On On On
Peripheral
Interrupt,
External Interrupt,
Reset,
PDPINTA/B
IDLE2 (LPM1) 01 Off Off On On On On
Wakeup
Interrupts,
External Interrupt,
Reset,
PDPINTA/B
HALT (LPM2)
[PLL/OSC power down] 1X Off Off Off Off Off OffReset,
PDPINTA/B
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357).
other power-down options
240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA.
Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
See the SCSR1 register for details on the peripheral clock enable bits.
digital I/O and shared pin functions
The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared
between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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digital I/O and shared pin functions (continued)
DOutput Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
DData and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 18, where each pin has three bits that define its
operation:
DMUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
DI/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
DI/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
Pin
(Read/Write)
IOP Data Bit
In Out
0 = Input
1 = Output
01 MUX Control Bit
0 = I/O Function
1 = Primary Function
IOP DIR Bit
Primary
Function
or I/O Pin
Pullup
or
Pulldown
(Internal)
Primary
Function
(Output Section)
Primary
Function
(Input Section)
Figure 18. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 12.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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62 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
description of shared I/O pins (continued)
Table 12. Shared Pin Configurations
PIN FUNCTION SELECTED MUX
CONTROL
MUX CONTROL I/O PORT DATA AND DIRECTION
(MCRx.n = 1)
Primary Function
(MCRX.N = 0)
I/O
CONTROL
REGISTER
(name.bit #)
MUX CONTROL
VALUE AT RESET
(MCRx.n) REGISTER DATA BIT NO.§DIR BIT NO.
PORT A
SCITXD IOPA0 MCRA.0 0 PADATDIR 0 8
SCIRXD IOPA1 MCRA.1 0 PADATDIR 1 9
XINT1 IOPA2 MCRA.2 0 PADATDIR 2 10
CAP1/QEP1 IOPA3 MCRA.3 0 PADATDIR 3 11
CAP2/QEP2 IOPA4 MCRA.4 0 PADATDIR 4 12
CAP3 IOPA5 MCRA.5 0 PADATDIR 5 13
PWM1 IOPA6 MCRA.6 0 PADATDIR 6 14
PWM2 IOPA7 MCRA.7 0 PADATDIR 7 15
PORT B
PWM3 IOPB0 MCRA.8 0 PBDATDIR 0 8
PWM4 IOPB1 MCRA.9 0 PBDATDIR 1 9
PWM5 IOPB2 MCRA.10 0 PBDATDIR 2 10
PWM6 IOPB3 MCRA.11 0 PBDATDIR 3 11
T1PWM/T1CMP IOPB4 MCRA.12 0 PBDATDIR 4 12
T2PWM/T2CMP IOPB5 MCRA.13 0 PBDATDIR 5 13
TDIRA IOPB6 MCRA.14 0 PBDATDIR 6 14
TCLKINA IOPB7 MCRA.15 0 PBDATDIR 7 15
PORT C
W/R #IOPC0 MCRB.0 1 PCDATDIR 0 8
BIO IOPC1 MCRB.1 1 PCDATDIR 1 9
SPISIMO IOPC2 MCRB.2 0 PCDATDIR 2 10
SPISOMI IOPC3 MCRB.3 0 PCDATDIR 3 11
SPICLK IOPC4 MCRB.4 0 PCDATDIR 4 12
SPISTE IOPC5 MCRB.5 0 PCDATDIR 5 13
CANTX IOPC6 MCRB.6 0 PCDATDIR 6 14
CANRX IOPC7 MCRB.7 0 PCDATDIR 7 15
PORT D
XINT2/ADCSOC IOPD0 MCRB.8 0 PDDATDIR 0 8
EMU0 Reserved MCRB.9|| 1 PDDATDIR 1 9
EMU1 Reserved MCRB.10|| 1 PDDATDIR 2 10
TCK Reserved MCRB.11|| 1 PDDATDIR 3 11
TDI Reserved MCRB.12|| 1 PDDATDIR 4 12
TDO Reserved MCRB.13|| 1 PDDATDIR 5 13
TMS Reserved MCRB.14|| 1 PDDATDIR 6 14
TMS2 Reserved MCRB.15|| 1 PDDATDIR 7 15
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
§If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
#At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A),
W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)
is reserved in these devices and must be written with a zero.
|| Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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description of shared I/O pins (continued)
Table 12. Shared Pin Configurations (Continued)
PIN FUNCTION SELECTED MUX
CONTROL
MUX CONTROL I/O PORT DATA AND DIRECTION
(MCRx.n = 1)
Primary Function
(MCRX.N = 0)
I/O
CONTROL
REGISTER
(name.bit #)
MUX CONTROL
VALUE AT RESET
(MCRx.n) REGISTER DATA BIT NO.§DIR BIT NO.
PORT E
CLKOUT IOPE0 MCRC.0 1 PEDATDIR 0 8
PWM7 IOPE1 MCRC.1 0 PEDATDIR 1 9
PWM8 IOPE2 MCRC.2 0 PEDATDIR 2 10
PWM9 IOPE3 MCRC.3 0 PEDATDIR 3 11
PWM10 IOPE4 MCRC.4 0 PEDATDIR 4 12
PWM11 IOPE5 MCRC.5 0 PEDATDIR 5 13
PWM12 IOPE6 MCRC.6 0 PEDATDIR 6 14
CAP4/QEP3 IOPE7 MCRC.7 0 PEDATDIR 7 15
PORT F
CAP5/QEP4 IOPF0 MCRC.8 0 PFDATDIR 0 8
CAP6 IOPF1 MCRC.9 0 PFDATDIR 1 9
T3PWM/T3CMP IOPF2 MCRC.10 0 PFDATDIR 2 10
T4PWM/T4CMP IOPF3 MCRC.11 0 PFDATDIR 3 11
TDIRB IOPF4 MCRC.12 0 PFDATDIR 4 12
TCLKINB IOPF5 MCRC.13 0 PFDATDIR 5 13
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
§If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
#At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A),
W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)
is reserved in these devices and must be written with a zero.
|| Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.
digital I/O control registers
Table 13 lists the registers available in the digital I/O module. As with other 240xA peripherals, these registers
are memory-mapped to the data space.
Table 13. Addresses of Digital I/O Control Registers
ADDRESS REGISTER NAME
7090h MCRA I/O MUX control register A
7092h MCRB I/O mux control register B
7094h MCRC I/O mux control register C
7095h PEDATDIR I/O port E data and direction register
7096h PFDATDIR I/O port F data and direction register
7098h PADATDIR I/O port A data and direction register
709Ah PBDATDIR I/O port B data and direction register
709Ch PCDATDIR I/O port C data and direction register
709Eh PDDATDIR I/O port D data and direction register
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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external memory interface (LF2407A)
The TMS320LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data,
and I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range.
The CPU of the TMS320LF2407A schedules a program fetch, data read, and data write on the same machine
cycle. This is because from on-chip memory, the CPU can execute all three of these operations in the same
cycle. However, the external interface multiplexes the internal buses to one address bus and one data bus. The
external interface sequences these operations to complete first the data write, then the data read, and finally
the program read.
The LF2407A supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address
and data buses, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in
program, data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space
(70007FFF), the externally addressable data-memory space is 32K 16-bit words (8000FFFF). Note that the
global memory space of the C2xx core is not used for 240xA DSP devices. Therefore, the global memory
allocation register (GREG) is reserved for all these devices.
Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are
accessed in the I/O address space using the processor’s external address and data buses in the same manner
as memory-mapped devices.
The LF2407A external parallel interface provides various control signals to facilitate interfacing to the device.
The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output
signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and
the WE output signals, which indicate a read cycle and a write cycle, respectively, along with timing information
for those cycles. The availability of these signals minimizes external gating necessary for interfacing external
devices to the LF2407A.
The 2407A provides RD and W/R signals to help the zero-wait-state external memory interface. At higher
CLKOUT speeds, RD may not meet the slow memory device’s timing. In such instances, the W/R signal could
be used as an alternative signal with some tradeoffs. See the timing parameters for details.
The TMS320LF2407A supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the TMS320LF2407A to buffer the transition of the data bus from input to
output (or from output to input) by a half cycle. In most systems, the TMS320LF2407A ratio of reads to writes
is significantly large to minimize the overhead of the extra cycle on writes.
wait-state generation (LF2407A only)
Wait-state generation is incorporated in the LF2407A without any external hardware for interfacing the LF2407A
with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external
memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O
port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states
operate on CLKOUT cycle boundaries.
To avoid bus conflicts, writes from the LF2407A always take at least two CLKOUT cycles. The LF2407A offers
two options for generating wait states:
DREADY Signal. With the READY signal, you can externally generate any number of wait states. The READY
pin has no effect on accesses to internal memory.
DOn-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
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generating wait states with the READY signal
When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The
LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is
not used, it should be pulled high.
The READY pin can be used to generate any number of wait states. However, when the LF2407A operates at
full speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended
wait states using external READY logic, the on-chip wait-state generator should be programmed to generate
at least one wait state.
generating wait states with the LF2407A on-chip software wait-state generator
The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip
memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait
states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information
on the WSGR and associated bit functions, see the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
watchdog (WD) timer module
The x240xA devices include a watchdog (WD) timer module. The WD function of this module monitors software
and hardware operation by generating a system reset if it is not periodically serviced by software by having the
correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization
to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK
signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer
begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up
sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:
DWD Timer
Seven different WD overflow rates
A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
DAutomatic activation of the WD timer, once system reset is released
Three WD control registers located in control register frame beginning at address 7020h.
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte
is read as zeros. Writing to the upper byte has no effect.
Figure 19 shows the WD block diagram. Table 14 shows the different WD overflow (time-out) selections.
The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of
the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent
to the WDDIS pin of the TMS320F243/241 devices.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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watchdog (WD) timer module (continued)
55 + AA
Detector
System
Reset
Request
WDCNTR.7 0
6-Bit
Free-
Running
Counter
/64
/32
/16
/8
/4
/2
111
110
101
100
011
010
001
000
WDCLK
System
Reset
System Reset
CLR
Watchdog
Reset Key
Register
8-Bit Watchdog
Counter
CLR
Bad WDCR Key
Good Key
Bad Key
WDPS
WDCR.2 0
210
WDKEY.7 0
WDCHK20
WDCR.5 3
WDCR.7
WDFLAG
Reset Flag
PS/257
WDDIS
WDCR.6
101
(Constant
Value)
3
3
On-Chip
Oscillator or
External
Clock
÷ 512 PLL
CLKOUT CLKIN
3-bit
Prescaler
Internal
Pullup
RS Pin
One-Cycle
Delay
Writing to bits WDCR.53 with anything but the correct pattern (101) generates a system reset.
Figure 19. Block Diagram of the WD Module
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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watchdog (WD) timer module (continued)
Table 14. WD Overflow (Time-out) Selections
WD PRESCALE SELECT BITS WDCLK DIVIDER
WATCHDOG
CLOCK RATE
WDPS2 WDPS1 WDPS0
WDCLK DIVIDER
FREQUENCY (Hz)
0 0 X1 WDCLK/1
0 1 0 2 WDCLK/2
0 1 1 4 WDCLK/4
1 0 0 8 WDCLK/8
1 0 1 16 WDCLK/16
1 1 0 32 WDCLK/32
1 1 1 64 WDCLK/64
WDCLK = CLKOUT/512
X = Don’t care
development support
Texas Instruments (TI) offers an extensive line of development tools for the x240xA generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of x240xA-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 (supports x24x multiprocessor system debug)
TMS320LF2407 EVM (Evaluation module for 2407 DSP)
See Table 15 and Table 16 for complete listings of development support tools for the x240xA. For information
on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Table 15. Development Support Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Software
Code Composer Studio v.2.2 PCTMDSCCS2000-1
Hardware Emulation Debug Tools
XDS510PP Pod (Parallel Port) with JTAG cable PC TMDS3P701014
PC is a trademark of International Business Machines Corp..
Code Composer Studio, XDS510, and XDS510PP are trademarks of Texas Instruments.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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development support (continued)
Table 16. TMS320x24x-Specific Development Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Hardware Evaluation/Starter Kits
2401A eZdsp PC TMDSeZD2401
F2407A EVM PC TMDS3P701016A
LF2407A eZdsp PC TMDSEZD2407
The LF2407 Evaluation Module (EVM) provide designers of motor and motion control applications with a
complete and cost-effective way to take their designs from concept to production. These tools offer both a
hardware and software development environment and include:
DFlash-based LF240xA evaluation board
DCode Generation Tools
DAssembler/Linker
DC Compiler
DSource code debugger
DC24x Debugger
DCode Composer IDE
DXDS510PP JTAG-based emulator
DSample applications code
DUniversal 5-V DC power supply
DDocumentation and cables
device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
TMS320 is a trademark of Texas Instruments.
eZdsp is a trademark of Spectrum Digital, Inc.
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
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device and development support tool nomenclature (continued)
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PAG, PG, PGE, and PZ) and temperature range (for example, A). Figure 20 provides a legend
for reading the complete device name for any TMS320x240xA family member. See the timing section for specific
options that are available on 240xA devices.
PREFIX
TMS 320 LF 2407A PGE
TMX = experimental device
TMP = prototype device
TMS = qualified device
DEVICE FAMILY
320 = TMS320 DSP Family
TECHNOLOGY
PACKAGE TYPE†‡
PG = 64-pin QFP
PAG = 64-pin TQFP
PGE = 144-pin plastic LQFP
PZ = 100-pin plastic LQFP
VF = 32-pin plastic LQFP
LC = ROM (3.3 V)
LF = Flash EEPROM (3.3 V)
DEVICE
240xA DSP
2407A§
2406A§
2404A
2403A
2402A
2401A
QFP = Quad Flatpack
LQFP = Low-Profile Quad Flatpack
TQFP = Thin Quad Flatpack
Not yet available Lead (Pb)-free. For estimated conversion dates, go to www.ti.com/leadfree
§The package dimensions of the 2407A and 2406A devices correspond to the LQFP package. These devices were stated to be
in TQFP packaging in the TMX data sheets. The package dimensions have not changed; only the package designation has
changed.
TEMPERATURE RANGE
A=40°C to 85°C
S=40°C to 125°C
PGE A
Figure 20. TMS320x240xA Device Nomenclature
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s guides for all devices and development
support tools; and hardware and software applications. Useful reference documentation includes:
DUser Guides
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357)
Manual Update Sheet for TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (SPRU357) [literature number SPRZ015]
TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide
(literature number SPRU160)
DData Sheets
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A,
TMS320LC2404A, TMS320LC2402A DSP Controllers (literature number SPRS145)
TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers (literature number SPRS094)
TMS320LF2401A DSP Controller (literature number SPRS161)
DApplication Reports
3.3-V DSP for Digital Motor Control (literature number SPRA550)
To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this TMS320x240xA data sheet (literature number SPRS145), use the
comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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LF240xA AND LC240xA ELECTRICAL SPECIFICATIONS DATA
absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)
Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA (see Note 1) 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . .
VCCP range 0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VIN 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO LF240xA 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range,VO LC240xA 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VIN < 0 or VIN > VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature ranges, TA: A version 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S version 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature range, TJ (see Note 2) 40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg (see Note 2) 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. Longterm hightemperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall
device life. For additional information, see the IC Package Thermal Metrics Application Report (literature number SPRA953) and
the Reliability Data for TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
recommended operating conditions‡§
MIN NOM MAX UNIT
VDD/VDDO Supply voltage VDDO = VDD ± 0.3 V 3 3.3 3.6 V
VSS Supply ground 0 0 0 V
PLLVCCA PLL supply voltage 3 3.3 3.6 V
VCCAADC supply voltage 3 3.3 3.6 V
VCCP Flash programming supply voltage#4.75 5 5.25 V
fCLKOUT Device clock frequency (system clock) 2 40 MHz
V||
High level input voltage
All inputs
2
V 03
V
VIH|| High-level input voltage All inputs 2 VDD + 0.3 V
V
Low level input voltage
All inputs
08
V
VIL Low-level input voltage All inputs 0.8 V
Output pins Group 1k 2 mA
IOH High-level output source current, VOH = 2.4 V Output pins Group 2k 4 mA
IOH
High level output source current, VOH 2.4 V
Output pins Group 3k 8 mA
Output pins Group 1k2 mA
IOL Low-level output sink current, VOL = VOL MAX Output pins Group 2k4 mA
IOL
Low level output sink current, VOL V
OL MAX
Output pins Group 3k8 mA
T
Free air temperature
A version 40 85
°C
TAFree-air temperature S version 40 125 °C
TJJunction temperature 40 25 150 °C
NfFlash endurance for the array (Write/erase cycles) 40°C to 85°C 10K cycles
See the mechanical data package page for thermal resistance values, ΘJA (junction-to-ambient), ΘJC (junction-to-case), and Ψjt (junction-to-top
of case)
§The drive strengths of the EVA PWM pins and the EVB PWM pins are not identical.
VCCA should not differ from VDD by more than 0.3 V.
#For applications that involve millions of power cycles, it is recommended that VCCP be powered after VDD.
|| The input buffers used in 240x/240xA are not 5-V compatible.
kPrimary signals and their groupings:
Group 1: PWM1PWM6, T1PWM, T2PWM, CAP1CAP6, TCLKINA, IOPF6, IOPC1, TCK, TDI, TMS, XF, A0A15, RS
Group 2: PS/DS/IS, RD, W/R, STRB, R/W, VIS_OE, D0D15, T3PWM, T4PWM, PWM7PWM12, CANTX, CANRX, SPICLK,
SPISOMI, SPISIMO, SPISTE, EMU0, EMU1, TDO, TMS2
Group 3: TDIRA, TDIRB, SCIRXD, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
72 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
electrical characteristics over recommended operating free-air temperature ranges (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
High level output voltage
VDD = 3.0 V, IOH = IOHMAX 2.4 VDDO
V
VOH High-level output voltage All outputs at 50 µAVDDO 0.2 V
VOLLow-level output voltage IOL = IOLMAX 0.4 V
I
Input current (low level)
With pullup
V 33 V V 0 V
10 16 30
A
IIL Input current (low level) With pulldown VDD = 3.3 V, VIN = 0 V ±2µA
I
Input current (high level)
With pullup
V 33 V V V
±2
A
IIH Input current (high level) With pulldown VDD = 3.3 V, VIN = VDD 10 16 30 µA
IOZ Leakage current, high-impedance state (off-state) VO = VDD or 0 V ±2µA
CiInput capacitance 2 pF
CoOutput capacitance 3 pF
For group 3 pins, VOL could be up to 0.6 V, when output source current is 8 mA.
current consumption by power-supply pins over recommended operating free-air temperature
ranges at 40-MHz CLOCKOUT
PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT
A test code running in B0 RAM does the
LF2407A 95 120 mA
A test code running in B0 RAM does the
followin
g
:LF2406A 95 120 mA
following:
1. Enables clock to all peripherals.
2 Toggles all PWM outputs at 20 kHz
LF2403A 95 120 mA
I
Operational Current
2. Toggles all PWM outputs at 20 kHz.
3. Performs a continuous conversion of all LF2402A 85 110 mA
IDD
Operational Current
3
.
Performs a continuous conversion of all
ADC channels.
4 An infinite loop which transmits a character
LC2406A 85 110 mA
4.
A
n
i
n
fi
n
i
te
l
oop
w
hi
c
h
transm
i
ts
a
c
h
aracter
out of SCI and executes MACD instructions. LC2404A 85 110 mA
out of SCI and executes MACD instructions.
NOTE: All I/O pins are floating
LC2403A 75 95 mA
NOTE
:
All I/O
p
i
ns
are
fl
oa
ti
ng.
LC2402A 75 95 mA
LF2407A 10 22 mA
LF2406A 10 22 mA
LF2403A 10 22 mA
ICCA
ADC module current
LF2402A 10 22 mA
I
CCA
ADC
mo
d
u
l
e
current LC2406A 10 22 mA
LC2404A 10 22 mA
LC2403A 10 22 mA
LC2402A 10 22 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
73
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2407A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 70 80 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
IDDOperational Current
LPM2
Clock to all peripherals is disabled.
Flash is powered down
200 400 µA
ICCA ADC module current
LPM2
Flash is powered down.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2406A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 70 80 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
IDDOperational Current
LPM2
Clock to all peripherals is disabled.
Flash is powered down
200 400 µA
ICCA ADC module current
LPM2
Flash is powered down.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2403A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 70 80 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
IDDOperational Current
LPM2
Clock to all peripherals is disabled.
Flash is powered down
200 400 µA
ICCA ADC module current
LPM2
Flash is powered down.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
74 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2402A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 60 70 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
IDDOperational Current
LPM2
Clock to all peripherals is disabled.
Flash is powered down
200 400 µA
ICCA ADC module current
LPM2
Flash is powered down.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2406A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 50 70 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
I
Operational Current
40°C to 85°C 20 200 µA
IDD
Operational Current
LPM2
40°C to 125°C 20 400 µA
ICCA ADC module current
LPM2
Clock to all peripherals is disabled.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2404A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 50 70 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
I
Operational Current
40°C to 85°C 20 200 µA
IDD
Operational Current
LPM2
40°C to 125°C 20 400 µA
ICCA ADC module current
LPM2
Clock to all peripherals is disabled.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
75
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2403A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 50 70 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
I
Operational Current
40°C to 85°C 20 200 µA
IDD
Operational Current
LPM2
40°C to 125°C 20 400 µA
ICCA ADC module current
LPM2
Clock to all peripherals is disabled.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
current consumption by power-supply pins over recommended operating free-air temperature
ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2402A)
PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT
IDDOperational Current
LPM0
Clock to all peripherals is enabled. 40 60 mA
ICCA ADC module current LPM0
Clock to all peripherals is enabled.
No I/O pins are switching. 10 22 mA
IDDOperational Current
LPM1
Clock to all peripherals is disabled. 35 45 mA
ICCA ADC module current LPM1
Clock to all peripherals is disabled.
No I/O pins are switching. 0 0 mA
I
Operational Current
40°C to 85°C 20 200 µA
IDD
Operational Current
LPM2
40°C to 125°C 20 400 µA
ICCA ADC module current
LPM2
Clock to all peripherals is disabled.
Input clock is disabled.0 0 mA
IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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76 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
current consumption graphs
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45
CLKOUT Frequency (MHz)
Current (mA)
IDD
Figure 21. LF2407A Typical Current Consumption (With Peripheral Clocks Enabled)
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45
CLKOUT Frequency (MHz)
Current (mA)
IDD
Figure 22. LC2406A Typical Current Consumption (With Peripheral Clocks Enabled)
Figure 23 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 23 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on
buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP Controllers CPU and
Instruction Set Reference Guide (literature number SPRU160).
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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EMU0
EMU1
TMS
TDI
TDO
TCK
VDDO
DSP
EMU0
EMU1
TMS
TDI
TDO
TCK
TCK_RET
13
14
2
1
3
7
11
9
6 inches or less
PD
GND
GND
GND
GND
GND
5
4
6
8
10
12
JTAG Header
VDDIO
TRSTTRST
Figure 23. Emulator Connection Without Signal Buffering for the DSP
reducing current consumption
240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 17 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals. See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals.
Table 17. Typical Current Consumption by Various Peripherals (at 40 MHz)
PERIPHERAL MODULE CURRENT REDUCTION (mA)
CAN 8.4
EVA 6.1
EVB 6.1
ADC 3.7
SCI 1.9
SPI 1.3
This number represents the current drawn by the digital portion of the ADC module.
Turning off the clock to the ADC module results in the elimination of the current drawn
by the analog portion of the ADC (ICCA) as well.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
78 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50
Where: IOL = 2 mA (all outputs)
IOH = 300 µA (all outputs)
VLOAD = 1.5 V
CT= 50-pF typical load-circuit capacitance
Figure 24. Test Load Circuit
signal transition levels
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.4 V.
Figure 25 shows output levels.
0.4 V (VOL)
20%
2.4 V (VOH)
80%
Figure 25. Output Levels
Output transition times are specified as follows:
DFor a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
DFor a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 26 shows the input levels.
0.8 V (VIL)
10%
2.0 V (VIH)
90%
Figure 26. Input Levels
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
Input transition times are specified as follows:
DFor a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
DFor a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
A A[15:0] MS Memory strobe pins IS, DS, or PS
Cl XTAL1/CLKIN R READY
CO CLKOUT RD Read cycle or RD
D D[15:0] RS RESET pin RS
INT XINT1, XINT2 W Write cycle or WE
Lowercase subscripts and their meanings: Letters and symbols and their meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don’t care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
general notes on timing
All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this data sheet.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
80 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
external reference crystal/clock with PLL circuit enabled
timing parameters with the PLL circuit enabled
PARAMETER MIN MAX UNIT
Resonator 4 13
fxInput clock frequencyCrystal 4 20 MHz
fx
Input clock frequency
CLKIN 4 20
MHz
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 27)
PARAMETER PLL MODE MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT ×4 mode25 ns
tf(CO) Fall time, CLKOUT 4 ns
tr(CO) Rise time, CLKOUT 4 ns
tw(COL) Pulse duration, CLKOUT low H3 H H+3 ns
tw(COH) Pulse duration, CLKOUT high H3 H H+3 ns
ttTransition time, PLL synchronized after RS pin high 4096tc(Cl) ns
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
timing requirements (see Figure 27)
MIN MAX UNIT
tc(Cl) Cycle time, XTAL1/CLKIN 250 ns
tf(Cl) Fall time, XTAL1/CLKIN 5 ns
tr(Cl) Rise time, XTAL1/CLKIN 5 ns
tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl) 40 60 %
tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl) 40 60 %
XTAL1/CLKIN
tc(CI)
tw(CIL)
tw(CIH)
tf(Cl) tr(Cl)
tc(CO)
tw(COH)
tw(COL) tr(CO) tf(CO)
CLKOUT
Figure 27. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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RS timing
timing requirements for a reset [H = 0.5tc(CO)] (see Figure 28 and Figure 29)
MIN NOM MAX UNIT
tw(RSL) Pulse duration, stable CLKIN to RS high 8tc(CI)cycles
tw(RSL2) Pulse duration, RS low 8tc(CI) cycles
tpPLL lock-up time 4096tc(CI) cycles
td(EX) Delay time, reset vector executed after PLL lock time 36H ns
During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles.
XTAL1
(See Note B)
Address/
Data/
Control
CLKOUT
RS
tw(RSL)
tp td(EX)
VDD/VDDO
CLKIN
BOOT_EN/XF
tOSCST
(See Note C)
BOOT_EN
I/Os
XF
Code-Dependent
Address/Data/Control Valid
Hi-Z (See Note D)
NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before
the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New
generation emulators such as SPI515 and XDS510 USB emulators have built-in protection mechanism to take care of this
requirement.
B. XTAL1 refers to the internal oscillator clock if on-chip oscillator is used.
C. tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design.
D. All I/Os contain a clamp to VDD. Inputs of approximately 0.7 V above VDD will cause the I/O to sink current. I/Os containing pullups
or pulldowns will always sink/source a small amount of current once powered.
Figure 28. Power-on Reset (See Note A)
XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital.
XDS510 and XDS510PP, are trademarks of Texas Instruments.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
82 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
RS timing (continued)
XTAL1
Address/
Data/
Control
CLKOUT
RS
tw(RSL2) tp
td(EX)
CLKIN
BOOT_EN
/XF
I/Os
XF
Code-Dependent
Address/Data/Control Valid
Hi-Z
BOOT_EN
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
Figure 29. Warm Reset
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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RS timing (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5tc(CO)]
(see Figure 30)
PARAMETER MIN MAX UNIT
tw(RSL1) Pulse duration, RS low128tc(CI) ns
td(EX) Delay time, reset vector executed after PLL lock time 36H ns
tpPLL lock time (input cycles) 4096tc(CI) ns
The parameter tw(RSL1) refers to the time RS is an output.
XTAL1
Address/
Data/
Control
CLKOUT
RS
tw(RSL1) tp
td(EX)
CLKIN
BOOT_EN
/XF BOOT_EN
I/Os
XF
Code-Dependent
Address/Data/Control Valid
Hi-Z
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
Figure 30. Watchdog Initiated Reset
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
84 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
low-power mode timing
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
(see Figure 31, Figure 32, and Figure 33)
PARAMETER LOW-POWER MODES MIN TYP MAX UNIT
t
Dela
y
time
,
CLKOUT switchin
g
to IDLE1 LPM0 12 × tc(CO)
ns
td(WAKE-A)
Delay time
,
CLKOUT switching to
program execution resume IDLE2 LPM1 15 × tc(CO)
ns
td(IDLE-COH) Delay time, Idle instruction executed to
CLKOUT high IDLE2 LPM1 4tc(CO) ns
td(WAKE-OSC) Delay time, wakeup interrupt
asserted to oscillator running HALT
LPM2
OSC start-up
time ms
td(IDLE-OSC) Delay time, Idle instruction executed to
oscillator power off
HALT
{PLL/OSC power down} LPM2
4tc(CO) ns
td(EX) Delay time, reset vector executed after PLL lock time 36H ns
WAKE INT
CLKOUT
A0A15
td(WAKEA)
WAKE INT can be any valid interrupt or RESET.
Figure 31. IDLE1 Entry and Exit Timing LPM0
td(WAKEA)
td(IDLECOH)
WAKE INT
CLKOUT
A0A15
WAKE INT can be any valid interrupt or RESET.
Figure 32. IDLE2 Entry and Exit Timing LPM1
td(EX)
td(IDLECOH)
td(IDLEOSC)
RESET
CLKOUT
A0A15
td(WAKEOSC) tw(RSL)
tp
Figure 33. HALT Mode LPM2
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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LPM2 wakeup timing
switching characteristics over recommended operating conditions (see Figure 34)
PARAMETER MIN MAX UNIT
t
Dela
y
time, PDPINTA low to PWM if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12ns
td(PDP-PWM)HZ
Delay time
,
PDPINTA low to PWM
high-impedance state if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12ns
td(INT) Delay time, INT low/high to interrupt-vector
fetch 10tc(CO) + tw(PDPWAKE) ns
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 34)
MIN MAX UNIT
t
Pulse duration PDPINTA input low
if bit 6 of SCSR2 = 0 6tc(CO)
ns
tw(PDPWAKE)
Pulse duration, PDPINTA input low if bit 6 of SCSR2 = 1 12tc(CO)
ns
tpPLL lock-up time 4096tc(CI) cycles
This is different from 240x devices.
PWM
PDPINTx
CLKOUT
tw(PDPWAKE)
td(PDP-PWM)HZ
CPU Status Interrupt Vector§ or
Next Instruction
td(INT)
XTAL1 Oscillator Disabled
CLKIN
tp
tOSC
CPU IDLE State (LPM2)
tOSC is the oscillator start-up time.
CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example).
§PDPINTx interrupt vector, if PDPINTx interrupt is enabled.
If PDPINTx interrupt is disabled.
Figure 34. LPM2 Wakeup Using PDPINTx
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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XF, BIO, and MP/MC timing
switching characteristics over recommended operating conditions (see Figure 35)
PARAMETER MIN MAX UNIT
td(XF) Delay time, CLKOUT high to XF high/low 3 7 ns
timing requirements (see Figure 35)
MIN MAX UNIT
tsu(BIO)CO Setup time, BIO or MP/MC low before CLKOUT low 0 ns
th(BIO)CO Hold time, BIO or MP/MC low after CLKOUT low 19 ns
td(XF)
XF
BIO,
MP/MC
CLKOUT
tsu(BIO)CO th(BIO)CO
Figure 35. XF and BIO Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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TIMING EVENT MANAGER INTERFACE
PWM timing
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5tc(CO)] (see Figure 36)
PARAMETER MIN MAX UNIT
tw(PWM)Pulse duration, PWMx output high/low 2H+5 ns
td(PWM)CO Delay time, CLKOUT low to PWMx output switching 15 ns
PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
timing requirements [H = 0.5tc(CO)] (see Figure 37)
MIN MAX UNIT
tw(TMRDIR) Pulse duration, TMRDIR low/high 4H+5 ns
tw(TMRCLK) Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time 40 60 %
twh(TMRCLK) Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time 40 60 %
tc(TMRCLK) Cycle time, TMRCLK 4 tc(CO) ns
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
tw(PWM)
td(PWM)CO
PWMx
CLKOUT
Figure 36. PWM Output Timing
CLKOUT
tw(TMRDIR)
TMRDIR
Parameter TMRDIR is equal to the pin TDIRx.
Figure 37. TMRDIR Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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capture and QEP timing
CAP refers to all QEP and capture input pins.
timing requirements (see Figure 38)
MIN MAX UNIT
t
Pulse duration CAPx input low/high
if bit 6 of SCSR2 = 0 6tc(CO)
ns
tw(CAP)
Pulse duration, CAPx input low/high if bit 6 of SCSR2 = 1 12tc(CO)
ns
This is different from 240x devices.
CAPx
tw(CAP)
CLKOUT
Figure 38. Capture Input and QEP Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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interrupt timing
INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
switching characteristics over recommended operating conditions (see Figure 39)
PARAMETER MIN MAX UNIT
t
Dela
y
time, PDPINTA low to PWM if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12ns
td(PDP-PWM)HZ
Delay time
,
PDPINTA low to PWM
high-impedance state if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12ns
td(INT) Delay time, INT low/high to interrupt-vector
fetch 10tc(CO) + tW (INT) ns
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 39)
MIN MAX UNIT
t
Pulse duration INT input low/high
if bit 6 of SCSR2 = 0 6tc(CO)
ns
tw(INT)
Pulse duration, INT input low/high if bit 6 of SCSR2 = 1 12tc(CO)
ns
t
Pulse duration PDPINTx input low
if bit 6 of SCSR2 = 0 6tc(CO)
ns
tw(PDP)
Pulse duration, PDPINTx input low if bit 6 of SCSR2 = 1 12tc(CO)
ns
This is different from 240x devices.
PWM
PDPINTx
CLKOUT
tw(PDP)
td(PDP-PWM)HZ
XINT1, XINT2
tw(INT)
Interrupt Vector
td(INT)
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken
high depends on the state of the FCOMPOE bit.
A0A15
Figure 39. External Interrupts Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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general-purpose input/output timing
switching characteristics over recommended operating conditions (see Figure 40)
PARAMETER MIN MAX UNIT
t
Dela time CLKOUT lo to GPIO lo /high
All GPIOs
9
ns
td(GPO)CO Delay time, CLKOUT low to GPIO low/high All GPIOs 9ns
tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 6 ns
timing requirements [H = 0.5tc(CO)] (see Figure 41)
MIN MAX UNIT
tw(GPI) Pulse duration, GPI high/low 2H+15 ns
td(GPO)CO
GPIO
CLKOUT
tr(GPO)
tf(GPO)
Figure 40. General-Purpose Output Timing
GPIO
CLKOUT
tw(GPI)
Figure 41. General-Purpose Input Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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91
SPI MASTER MODE TIMING PARAMETERS
SPI master mode timing information is listed in the following tables.
SPI master mode external timing parameters (clock phase = 0)†‡ (see Figure 42)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3 UNIT
NO
.
MIN MAX MIN MAX
UNIT
1 tc(SPC)M Cycle time, SPICLK 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) ns
2§
tw(SPCH)M Pulse duration, SPICLK high
(clock polarity = 0) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(CO) 10 0.5tc(SPC)M 0.5tc(CO)
ns
2§
tw(SPCL)M Pulse duration, SPICLK low
(clock polarity = 1) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(CO) 10 0.5tc(SPC)M 0.5tc(CO)
ns
3§
tw(SPCL)M Pulse duration, SPICLK low
(clock polarity = 0) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M +0.5tc(CO)
10 0.5tc(SPC)M + 0.5tc(CO)
ns
3§
tw(SPCH)M Pulse duration, SPICLK high
(clock polarity = 1) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M +0.5tc(CO)
10 0.5tc(SPC)M + 0.5tc(CO)
ns
4§
td(SPCH-SIMO)M Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0) 10 10 10 10
ns
4§
td(SPCL-SIMO)M Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1) 10 10 10 10
ns
5§
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after
SPICLK low (clock polarity =0) 0.5tc(SPC)M 10 0.5tc(SPC)M +0.5tc(CO) 10
ns
5§
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after
SPICLK high (clock polarity =1) 0.5tc(SPC)M 10 0.5tc(SPC)M +0.5tc(CO) 10
ns
8§
tsu(SOMI-SPCL)M Setup time, SPISOMI before
SPICLK low (clock polarity = 0) 0 0
ns
8§
tsu(SOMI-SPCH)M Setup time, SPISOMI before
SPICLK high (clock polarity = 1) 0 0
ns
9§
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0) 0.25tc(SPC)M 10 0.5tc(SPC)M 0.5tc(CO) 10
ns
9
§
tv(SPCH-SOMI)M Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1) 0.25tc(SPC)M 10 0.5tc(SPC)M 0.5tc(CO)
10
ns
The MASTER/ SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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92 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
8
5
3
2
1
SPISTE
The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI
communication stream is complete.
Figure 42. SPI Master Mode External Timing (Clock Phase = 0)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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93
SPI master mode external timing parameters (clock phase = 1)†‡ (see Figure 43)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3 UNIT
NO
.
MIN MAX MIN MAX
UNIT
1 tc(SPC)M Cycle time, SPICLK 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) ns
2§
tw(SPCH)M Pulse duration, SPICLK high
(clock polarity = 0) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(CO)
10 0.5tc(SPC)M 0.5tc(CO)
ns
2§
tw(SPCL)M Pulse duration, SPICLK low
(clock polarity = 1) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(CO)
10 0.5tc(SPC)M 0.5tc(CO)
ns
3§
tw(SPCL)M Pulse duration, SPICLK low
(clock polarity = 0) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M +0.5tc(CO) 10 0.5tc(SPC)M + 0.5tc(CO)
ns
3§
tw(SPCH)M Pulse duration, SPICLK high
(clock polarity = 1) 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M +0.5tc(CO) 10 0.5tc(SPC)M + 0.5tc(CO)
ns
6§
tsu(SIMO-SPCH)M
Setup time, SPISIMO data
valid before SPICLK high
(clock polarity = 0)
0.5tc(SPC)M 10 0.5tc(SPC)M 10
ns
6§
tsu(SIMO-SPCL)M
Setup time, SPISIMO data
valid before SPICLK low
(clock polarity = 1)
0.5tc(SPC)M 10 0.5tc(SPC)M 10
ns
7§
tv(SPCH-SIMO)M
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity =0)
0.5tc(SPC)M 10 0.5tc(SPC)M 10
ns
7§
tv(SPCL-SIMO)M
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity =1)
0.5tc(SPC)M 10 0.5tc(SPC)M 10
ns
10§
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high
(clock polarity = 0)
0 0
ns
10§
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low
(clock polarity = 1)
0 0
ns
11§
tv(SPCH-SOMI)M
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
0.25tc(SPC)M 10 0.5tc(SPC)M 10
ns
11
§
tv(SPCL-SOMI)M
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
0.25tc(SPC)M 10 0.5tc(SPC)M 10
ns
The MASTER/ SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
94 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE
The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI
communication stream is complete.
Figure 43. SPI Master Mode External Timing (Clock Phase = 1)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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SPI slave mode timing parameters
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)†‡ (see Figure 44)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(CO)ns
13§
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S 10 0.5tc(SPC)S
13§
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
14§
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S 10 0.5tc(SPC)S
14§
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
15§td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0) 0.375tc(SPC)S 10 ns
15§
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375tc(SPC)S 10
ns
16§
tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0) 0.75tc(SPC)S
16§
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1) 0.75tc(SPC)S
ns
19§
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0
19§
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0ns
20§
tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0) 0.5tc(SPC)S
ns
20
§
tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1) 0.5tc(SPC)S
ns
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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96 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
SPI slave mode external timing parameters (continued)
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 44. SPI Slave Mode External Timing (Clock Phase = 0)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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SPI slave mode timing parameters (continued)
SPI slave mode external timing parameters (clock phase = 1)†‡ (see Figure 45)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 8tc(CO) ns
13§
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
13§
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
14§
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
14§
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S 10 0.5tc(SPC)S
ns
17§
tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S
ns
17§
tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S
ns
18§
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0) 0.75tc(SPC)S
ns
18§
tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1) 0.75tc(SPC)S
ns
21§
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0
ns
21§
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0ns
22§
tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0) 0.5tc(SPC)S
ns
22
§
tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1) 0.5tc(SPC)S
ns
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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98 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
SPI slave mode timing parameters (continued)
Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
12
18
17
14
13
SPISTE
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 45. SPI Slave Mode External Timing (Clock Phase = 1)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface read timing
switching characteristics over recommended operating conditions for an external memory
interface read at 40 MHz [H = 0.5tc(CO)] (see Figure 46)
PARAMETER MIN MAX UNIT
td(COL-CNTL) Delay time, CLKOUT low to control valid 4 ns
td(COL-CNTH) Delay time, CLKOUT low to control inactive 5 ns
td(COL-A)RD Delay time, CLKOUT low to address valid 8 ns
td(COH-RDL) Delay time, CLKOUT high to RD strobe active 5 ns
td(COL-RDH) Delay time, CLKOUT low to RD strobe inactive high 8 1 ns
td(COL-SL) Delay time, CLKOUT low to STRB strobe active low 5 ns
td(COL-SH) Delay time, CLKOUT low to STRB strobe inactive high 6 ns
td(WRN) Delay time, W/R going low to R/W rising 5 ns
th(A)COL Hold time, address valid after CLKOUT low 2 ns
tsu(A)RD Setup time, address valid before RD strobe active low H 7 ns
th(A)RD Hold time, address valid after RD strobe inactive high 0 ns
timing requirements [H = 0.5tc(CO)] (see Figure 46)
MIN MAX UNIT
ta(A) Access time, read data from address valid 2H 10 ns
ta(RD) Access time, read data from RD low H 7 ns
tsu(D)RD Setup time, read data before RD strobe inactive high 8 ns
th(D)RD Hold time, read data after RD strobe inactive high 0 ns
th(AIV-D) Hold time, read data after address invalid 0 ns
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface read timing (continued)
td(COLCNTH)
th(A)COL
td(COLA)RD
th(A)COL
td(COLRDH)
td(COHRDL)
ta(A)
td(COHRDL)
CLKOUT
PS, DS,
IS
A[0:15]
td(COLCNTL)
td(COLA)RD
th(A)RD
tsu(D)RD
th(D)RD
tsu(A)RD
th(D)RD
tsu(D)RD
td(COLSH)
RD
D[0:15]
STRB
td(COLSL)
td(COLRDH)
ta(A)
th(AIVD)
W/R
R/W
ta(RD)
td(WRN)
Figure 46. Memory Interface Read/Read Timings
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface write timing
switching characteristics over recommended operating conditions for an external memory
interface write at 40 MHz [H = 0.5tc(CO)] (see Figure 47)
PARAMETER MIN MAX UNIT
td(COH-CNTL) Delay time, CLKOUT high to control valid 4 ns
td(COH-CNTH) Delay time, CLKOUT high to control inactive 5 ns
td(COH-A)W Delay time, CLKOUT high to address valid 10 ns
td(COH-RWL) Delay time, CLKOUT high to R/W low 6 ns
td(COH-RWH) Delay time, CLKOUT high to R/W high 6 ns
td(COL-WL) Delay time, CLKOUT low to WE strobe active low 6 ns
td(COL-WH) Delay time, CLKOUT low to WE strobe inactive high 6 ns
ten(D)COL Enable time, data bus driven from CLKOUT low 3 ns
td(COL-SL) Delay time, CLKOUT low to STRB active low 6 ns
td(COL-SH) Delay time, CLKOUT low to STRB inactive high 6 ns
td(WRN) Delay time, R/W rising to W/R going low 5 ns
th(A)COLW Hold time, address valid after CLKOUT low 5 ns
tsu(A)W Setup time, address valid before WE strobe active low H9 ns
tsu(D)W Setup time, write data before WE strobe inactive high 2H17 ns
th(D)W Hold time, write data after WE strobe inactive high 2 ns
tdis(W-D) Disable time, data bus high impedance from WE high 5 ns
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface write timing (continued)
tdis(W-D)
td(COHA)W
td(COHRWL)
tsu(A)W
td(COLWH)
WE
STRB
ten(D)COL
td(COLWL)
th(A)COLW
td(COHCNTL)
td(COHCNTH)
CLKOUT
A[0:15]
R/W
PS, DS, IS
td(COHCNTL)
td(COHRWH)
td(COLWL)
td(COLWH)
th(D)W
tsu(D)W
ten(D)COL
td(COLSH)
CLKOUT
ENA_144
VIS_OE
th(D)W
td(COLSL)
NOTE A: VIS_OE will be visible at pin 97 of LF2407A when ENA_144 is high along with BVIS bits (10,9 of WSGR register FFFFh@I/O) set to
10 or 11. CLKOUT and VIS_OE indicate internal memory write cycles (program/data). During VIS_OE cycles, the external bus will be
driven. CLKOUT is to be used along with VIS_OE for trace capabilities.
tsu(D)W
td(COLSL)
D[0:15]
td(COLSH)
2H 2H
W/R
td(WRN)
Figure 47. Memory Interface Write/Write Timings
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface ready-on-read timing
switching characteristics over recommended operating conditions for an external memory
interface ready-on-read (see Figure 48)
PARAMETER MIN MAX UNIT
td(COL-A)RD Delay time, CLKOUT low to address valid 8 ns
timing requirements for an external memory interface ready-on-read (see Figure 48)
MIN MAX UNIT
th(RDY)COH Hold time, READY after CLKOUT high 3 ns
tsu(D)RD Setup time, read data before RD strobe inactive high 8 ns
tv(RDY)ARD Valid time, READY after address valid on read 2 ns
tsu(RDY)COH Setup time, READY before CLKOUT high 22 ns
th(RDY)COH
CLKOUT
PS, DS, IS
RD
D[0:15]
STRB
A[0:15]
td(COLA)RD
tv(RDY)ARD
tsu(RDY)COH
READY
Wait Cycle
tsu(D)RD
The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details.
Figure 48. Ready-on-Read Timings
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface ready-on-read timing (continued)
timing requirements for an external memory interface ready-on-read with one software wait state
and one external wait state (see Figure 49)
MIN MAX UNIT
th(RDY)COH Hold time, READY after CLKOUT high H 2.5 ns
tsu(RDY)COH Setup time, READY before CLKOUT high H 9.5 ns
td(COL-A)RD Delay time, CLKOUT low to address valid 8 ns
PS, DS, IS
RD
READY
SW = 1 cycle EXW = 1 cycle Read Cycle
th(RDY)COH
tsu(RDY)COH
CLKOUT
R/W
W/R
D[0:15]
STRB
A[0:15]
td(COL-A)RD
Figure 49. Ready-on-Read Timings With One Software Wait (SW) State and
One External Wait (EXW) State
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface ready-on-write timing
switching characteristics over recommended operating conditions for an external memory
interface ready-on-write (see Figure 50)
PARAMETER MIN MAX UNIT
td(COH-A)W Delay time, CLKOUT high to address valid 10 ns
timing requirements for an external memory interface ready-on-write [H = 0.5tc(CO)]
(see Figure 50)
MIN MAX UNIT
th(RDY)COH Hold time, READY after CLKOUT high 3 ns
tsu(D)W Setup time, write data before WE strobe inactive high 2H17 ns
tv(RDY)AW Valid time, READY after address valid on write 3 ns
tsu(RDY)COH Setup time, READY before CLKOUT high 22 ns
tsu(D)W
CLKOUT
PS, DS, IS
td(COHA)W
A[0:15]
WE
D[0:15]
STRB
tsu(RDY)COH
th(RDY)COH
READY
tv(RDY)AW
Wait Cycle
Figure 50. Ready-on-Write Timings
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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external memory interface ready-on-write timing (continued)
timing requirements for an external memory interface ready-on-write with one software wait state
and one external wait state (see Figure 51)
MIN MAX UNIT
th(RDY)COH Hold time, READY after CLKOUT high H 2.5 ns
tsu(RDY)COH Setup time, READY before CLKOUT high H 9.5 ns
td(COH-A)W Delay time, CLKOUT high to address valid 10 ns
PS, DS, IS
READY
WE
SW = 1 cycle EXW = 1 cycle Write Cycle
D[0:15]
STRB
th(RDY)COH
tsu(RDY)COH
CLKOUT
R/W
td(COHA)W
A[0:15]
Figure 51. Ready-on-Write Timings With One Software Wait (SW) State and
One External Wait (EXW) State
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications
are given with respect to VSSA unless otherwise noted.
Resolution 10-bit (1024 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic Assured. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode 000h to 3FFh (000h for VI VREFLO; 3FFh for VI VREFHI). . . . . . . . . . . . . . . . . . . .
Minimum conversion time (including sample time) 500 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
VCCA Analog supply voltage 3.0 3.3 3.6 V
VSSA Analog ground 0 V
VREFHI Analog supply reference source VCCA V
VREFLO Analog ground reference sourceVSSA V
VAI Analog input voltage, ADCIN00ADCIN07 VREFLO VREFHI V
VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.
VREFHI can be from 2.0 V to VCCA; however, the accuracy of the ADC depends on the ground bounce and noise on the target board.
ADC operating frequency
MIN MAX UNIT
ADC operating frequency 4 30 MHz
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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10-bit analog-to-digital converter (ADC) (continued)
operating characteristics over recommended operating condition ranges
PARAMETER DESCRIPTION MIN TYP MAX UNIT
VCCA = 3.3 V 10 22 mA
ICCA Analog supply current VCCA = VREFHI = 3.3 V PLL or OSC power
down 1µA
IADREFHI VREFHI input current 0.75 1.5 mA
IADCIN Analog input leakage 1µA
C
Analog input capacitance
T
y
pical capacitive load on Non-sampling 10
pF
Cai Analog input capacitance
Typical capacitive load on
analog input pin Sampling 30 pF
td(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 µs
ZAI Analog input source impedance
Analog input source impedance needed for
conversions to remain within specifications at min
tw(SH)
53 10
Zero-offset error "2 LSB
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
EDNL and EINL
PARAMETER DESCRIPTION CLKOUT MIN MAX UNIT
EDNLDifferential nonlinearity error Difference between the actual step width
and the ideal value 30 MHz "2 LSB
EINLIntegral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
30 MHz "2 LSB
Test conditions: VREFHI = VCCA , VREFLO = VSSA
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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10-bit analog-to-digital converter (ADC) (continued)
internal ADC module timing (see Figure 52)
MIN MAX UNIT
t
C l ti ADC al d l k
33 3
tc
(
AD
)
Cycle time, ADC prescaled clock 33.3 ns
Pulse duration total sample/hold and
tw(SHC)
P
u
l
se
d
urat
i
on,
tota
l
samp
l
e
/h
o
ld
an
d
i ti
500
ns
t
w(SHC) conversion time
500
ns
td(SOC-SH) Delay time, start of conversion to beginning of sample and hold 2tc(CO) ns
tw(SH) Pulse duration, sample and hold time 2tc(AD)§32tc(AD) ns
tw(C) Pulse duration, total conversion time 10tc(AD) ns
td(EOC) Delay time, end of conversion to data loaded into result register 2tc(CO) ns
td(ADCINT) Delay time, ADC flag to ADC interrupt 2tc(CO) ns
The ADC timing diagram represents a typical conversion sequence. See the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference
Guide: System and Peripherals (literature number SPRU357) for more details.
The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC) .
§Can be varied by ACQ Prescaler bits in the ADCTRL1 register
03 2
451
tw(C)
678
tc(AD)
ADC Clock
Analog Input
Bit Converted
td(SOCSH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to RESULTn
tw(SHC)
Á
Á
Á
Á
td(EOC)
9
tw(SH)
td(ADCINT)
ADC Interrupt
Figure 52. Analog-to-Digital Internal Module Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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Flash parameters @40 MHz CLOCKOUT
PARAMETER MIN TYP MAX UNIT
Time/Word (16-bit) 30 µs
Clear/Programming timeTime/4K Sector 130 ms
Clear/Programming time
Time/12K Sector 400 ms
Erase time
Time/4K Sector 350 ms
Erase time
Time/12K Sector 1 s
ICCP (VCCP pin current) Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle 5 15 mA
TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change.
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance
could also impact the timing parameters.
migrating from LF240xA (Flash) devices to LC240xA (ROM) devices
When migrating from a Flash to a ROM device, be sure to review this section for a list of important differences
that should be considered. Customer applications should consider these differences in their design, prior to
ROM code submission. Due to the fact that the flash and ROM are different silicon, the following parameters
may be similar but not exactly identical. Refer to the respective datasheet sections for more detail:
DEMI/ESD behavior
DADC performance
DCurrent consumption
DDevice ID register values
Table 18 outlines the differences between the LF240xA (Flash) devices and the LC240xA (ROM) devices.
Table 18. Differences Between LF240xA (Flash) Devices and LC240xA (ROM) Devices
FEATURE LF2406A LC2406A LC2404A LF2403A LC2403A LF2402A LC2402A
On-chip Flash or ROM (see Note 1) 32K 32K 16K 16K 16K 8K 6K
Single-Access RAM (SARAM)
(16-bit words) 2K 2K 1K 512 512 512
Boot ROM Yes Yes Yes Yes
Event Managers EVA, EVB EVA, EVB EVA, EVB EVA EVA EVA EVA
ADC Channels 16 16 16 8 8 8 8
SPI Yes Yes Yes Yes§Yes§
CAN Yes Yes Yes Yes
GPIO Pins 41 41 41 21 21 21 21
BIO Pin Yes Yes Yes ————
TDIRx Pin Yes Yes Yes ————
External Interrupts 5553333
Access to External Memory SpacesSee Note 2 See Note 3 See Note 3 See Note 2 See Note 3 See Note 2 See Note 3
VCCP Pin Functionality VCCP No Connect No Connect VCCP No Connect VCCP No Connect
Packaging 100-pin
PZ
100-pin
PZ
100-pin
PZ
64-pin
PAG
64-pin
PAG
64-pin
PG
64-pin
PG, PAG
§The SPISTE pin is not available on the LF2403A. See the SPI Slave Mode Operation in LF2403A section.
Application code should NOT access Illegal/Reserved addresses.
NOTES: 1. The last 64 words of ROM are reserved for TI internal testing. User code should not occupy these locations. See the device memory
map for details.
2. Access to external Program, Data, and I/O space is considered illegal and would assert an NMI.
3. The external Program and I/O spaces are implemented as “reserved” addresses and any access will not assert an NMI. However,
the external data memory space is illegal.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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migrating from 240x devices to 240xA devices
This section highlights the new features/migration issues of the 240xA devices (as compared to the 240x family)
and describes the impact these features/issues have on user applications.
maximum clock speed
240xA devices can operate at a maximum speed of 40 MHz compared to the 30-MHz operation of 240x devices.
This change in clock speed warrants a change in the register contents of all the peripherals. For example, to
maintain the same baud rate, the divisor values that are loaded to the SPI, SCI, and CAN registers must be
recalculated.
code security module
240xA devices incorporate a “code security module” which protects the contents of program memory from
unauthorized duplication. Passwords stored in password locations (PWL) 0040h to 0043h are used for this
purpose. Even if the code is not secured with passwords (i.e., PWL contains FFFFFFFFFFFFFFFFh), the PWL
must still be read to gain access to the program memory contents. Note that locations 0040h to 0043h were
available for user code in the 240x devices, which lack the “code security module”. In 240xA devices, these
locations are reserved for the passwords and are not available for the user code. Even if code security feature
is not used, these locations must be written with all ones. This fact must be borne in mind while submitting ROM
codes to TI.
input-qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1–6 (QEP14), XINT1/2, ADCSOC, and
PDPINTA/B pins in the x240xA devices. The state of the internal input signal will change only after these pins
are high/low for 6 (12) clock edges. The user must hold the pin high/low for 6 (12) cycles to ensure that the device
see the level change. The increase in the pulse width of the signals used to excite these pins must be taken
into account while migrating from the 240x to the 240xA family.
Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used
to block 5- or 11-cycle glitches. This bit is a “reserved” bit in 240x devices.
status of the PDPINTx pin
The current status of the PDPINTx pins is now reflected in bit 8 of the COMCONx registers. This bit is a
“reserved” bit in 240x devices.
operation of the IOPC0 pin
At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external
memory interface (e.g., LF2406A), W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0
pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register) is reserved in these devices and must
be written with a zero.
external pulldown resistor for TRST pin
An external pulldown resistor may be needed for the TRST pin in boards that operate in noisy environments.
Refer to the TRST pin description for more details.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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migrating from LF240x devices to LC240xA devices
When migrating from an “unsecured” Flash device (LF240x) to a “secured” ROM device (LC240xA), two
migration paths have to be taken into consideration:
DMigrating from a 240x device to a 240xA device (see the Migrating From 240x Devices to 240xA Devices
section)
DMigrating from a Flash (LF) device to a ROM (LC) device (see the Migrating From LF240xA (Flash) Devices
to LC240xA (ROM) Devices section)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
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peripheral register description
Table 19 is a collection of all the programmable registers of the LF240xA/LC240xA and is provided as a quick
reference.
Table 19. LF240xA/LC240xA DSP Peripheral Register Description
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP OV OVM 1 INTM DP(8)
ST0
DP(7) DP(6) DP(5) DP(4) DP(3) DP(2) DP(1) DP(0) ST0
ARB CNF TC SXM C 1
ST1
1 1 1 XF 1 1 PM ST1
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
00004h
IMR
00004h INT6 MASK INT5 MASK INT4 MASK INT3 MASK INT2 MASK INT1 MASK IMR
00005h
Reserved
GREG
00005h Reserved GREG
00006h
IFR
00006h INT6 FLAG INT5 FLAG INT4 FLAG INT3 FLAG INT2 FLAG INT1 FLAG IFR
SYSTEM REGISTERS
07010h
IRQ0.15 IRQ0.14 IRQ0.13 IRQ0.12 IRQ0.11 IRQ0.10 IRQ0.9 IRQ0.8
PIRQR0
07010h IRQ0.7 IRQ0.6 IRQ0.5 IRQ0.4 IRQ0.3 IRQ0.2 IRQ0.1 IRQ0.0 PIRQR0
07011h
IRQ1.15 IRQ1.14 IRQ1.13 IRQ1.12 IRQ1.11 IRQ1.10 IRQ1.9 IRQ1.8
PIRQR1
07011h IRQ1.7 IRQ1.6 IRQ1.5 IRQ1.4 IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0 PIRQR1
07012h
IRQ2.15 IRQ2.14 IRQ2.13 IRQ2.12 IRQ2.11 IRQ2.10 IRQ2.9 IRQ2.8
PIRQR2
07012h IRQ2.7 IRQ2.6 IRQ2.5 IRQ2.4 IRQ2.3 IRQ2.2 IRQ2.1 IRQ2.0 PIRQR2
07013h Illegal
07014h
IAK0.15 IAK0.14 IAK0.13 IAK0.12 IAK0.11 IAK0.10 IAK0.9 IAK0.8
PIACKR0
07014h IAK0.7 IAK0.6 IAK0.5 IAK0.4 IAK0.3 IAK0.2 IAK0.1 IAK0.0 PIACKR0
07015h
IAK1.15 IAK1.14 IAK1.13 IAK1.12 IAK1.11 IAK1.10 IAK1.9 IAK1.8
PIACKR1
07015h IAK1.7 IAK1.6 IAK1.5 IAK1.4 IAK1.3 IAK1.2 IAK1.1 IAK1.0 PIACKR1
07016h
IAK2.15 IAK2.14 IAK2.13 IAK2.12 IAK2.11 IAK2.10 IAK2.9 IAK2.8
PIACKR2
07016h IAK2.7 IAK2.6 IAK2.5 IAK2.4 IAK2.3 IAK2.2 IAK2.1 IAK2.0 PIACKR2
07017h Illegal
07018h
CLKSRC LPM1 LPM0 CLK PS2 CLK PS1 CLK PS0
SCSR1
07018h ADC CLKEN SCI CLKEN SPI CLKEN CAN CLKEN EVB CLKEN EVA CLKEN ILLADR SCSR1
07019h
I/P
QUALIFIER
CLOCKS
WD
OVERRIDE XMIF HI Z BOOT_EN MP/MC DON PON SCSR2
0701Ah
to
0701Bh
Illegal
0701Ch
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8
DINR
0701Ch DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DINR
0701Dh Illegal
0701Eh
V15 V14 V13 V12 V11 V10 V9 V8
PIVR
0701Eh V7 V6 V5 V4 V3 V2 V1 V0 PIVR
0701Fh Illegal
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
114 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
WD CONTROL REGISTERS
07020h
to
07022h
Illegal
07023h D7 D6 D5 D4 D3 D2 D1 D0 WDCNTR
07024h Illegal
07025h D7 D6 D5 D4 D3 D2 D1 D0 WDKEY
07026h
to
07028h
Illegal
07029h WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 WDCR
0702Ah
to
0703Fh
Illegal
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
07040h SPI SW
RESET
CLOCK
POLARITY SPI
CHAR3
SPI
CHAR2
SPI
CHAR1
SPI
CHAR0 SPICCR
07041h OVERRUN
INT ENA
CLOCK
PHASE
MASTER/
SLAVE TALK SPI INT
ENA SPICTL
07042h
RECEIVER
OVERRUN
FLAG
SPI INT
FLAG
TX BUF
FULL FLAG SPISTS
07043h Illegal
07044h SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
SPI BIT
RATE 0 SPIBRR
07045h Illegal
07046h
ERXB15 ERXB14 ERXB13 ERXB12 ERXB11 ERXB10 ERXB9 ERXB8
SPIRXEMU
07046h ERXB7 ERXB6 ERXB5 ERXB4 ERXB3 ERXB2 ERXB1 ERXB0 SPIRXEMU
07047h
RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8
SPIRXBUF
07047h RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 SPIRXBUF
07048h
TXB15 TXB14 TXB13 TXB12 TXB11 TXB10 TXB9 TXB8
SPITXBUF
07048h TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 SPITXBUF
07049h
SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8
SPIDAT
07049h SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 SPIDAT
0704Ah
0704Ah
to Ille
g
al
to
0704Eh
Illegal
0704Fh SPI
PRIORITY
SPI
SUSP SOFT
SPI
SUSP FREE SPIPRI
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
115
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
07050h STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOP BACK
ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
SCI
CHAR0 SCICCR
07051h RX ERR
INT ENA SW RESET TXWAKE SLEEP TXENA RXENA SCICTL1
07052h BAUD15
(MSB) BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD
07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0
(LSB) SCILBAUD
07054h TXRDY TX EMPTY RX/BK
INT ENA
TX
INT ENA SCICTL2
07055h RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCIRXST
07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 SCIRXEMU
07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 SCIRXBUF
07058h Illegal
07059h TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 SCITXBUF
0705Ah
to
0705Eh
Illegal
0705Fh SCITX
PRIORITY
SCIRX
PRIORITY
SCI
SOFT
SCI
FREE SCIPRI
07060h
to
0706Fh
Illegal
EXTERNAL INTERRUPT CONTROL REGISTERS
07070h
XINT1
FLAG
XINT1CR
07070h
XINT1
POLARITY
XINT1
PRIORITY
XINT1
ENA
XINT1CR
07071h
XINT2
FLAG
XINT2CR
07071h
XINT2
POLARITY
XINT2
PRIORITY
XINT2
ENA
XINT2CR
07072h
to
0708Fh
Illegal
DIGITAL I/O CONTROL REGISTERS
07090h
MCRA.15 MCRA.14 MCRA.13 MCRA.12 MCRA.11 MCRA.10 MCRA.9 MCRA.8
MCRA
07090h MCRA.7 MCRA.6 MCRA.5 MCRA.4 MCRA.3 MCRA.2 MCRA.1 MCRA.0 MCRA
07091h Illegal
07092h
MCRB.15 MCRB.14 MCRB.13 MCRB.12 MCRB.11 MCRB.10 MCRB.9 MCRB.8
MCRB
07092h MCRB.7 MCRB.6 MCRB.5 MCRB.4 MCRB.3 MCRB.2 MCRB.1 MCRB.0 MCRB
07093h Illegal
07094h
MCRC.15 MCRC.14 MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8
MCRC
07094h MCRC.7 MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0 MCRC
07095h
E7DIR E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR
PEDATDIR
07095h IOPE7 IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0 PEDATDIR
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
116 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
DIGITAL I/O CONTROL REGISTERS (CONTINUED)
07096h
F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR
PFDATDIR
07096h IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0 PFDATDIR
07098h
A7DIR A6DIR A5DIR A4DIR A3DIR A2DIR A1DIR A0DIR
PADATDIR
07098h IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0 PADATDIR
07099h Illegal
0709Ah
B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR
PBDATDIR
0709Ah IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0 PBDATDIR
0709Bh Illegal
0709Ch
C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR
PCDATDIR
0709Ch IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0 PCDATDIR
0709Dh Illegal
0709Eh
D0DIR
PDDATDIR
0709Eh IOPD0 PDDATDIR
0709Fh Illegal
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS
070A0h
ADC
S/W RESET SOFT FREE ACQ
PRESCALE3
ACQ
PRESCALE2
ACQ
PRESCALE1
ACQ
PRESCALE0
ADCTRL1
070A0h CONV PRE-
SCALE (CPS)
CONTIN-
UOUS RUN
INT
PRIORITY
SEQ1/2
CASCADE
ADCTRL1
070A1h
EVB SOC
EN SEQ1
RESET
SEQ1 SOC SEQ1 SEQ1 BUSY INT ENA
SEQ1 Mode1
INT ENA
SEQ1 Mode0
INT FLAG
SEQ1
EVA SOC
EN SEQ1
ADCTRL2
070A1h EXT SOC
EN SEQ1 Reset SEQ2 SOC SEQ2 SEQ2 BUSY INT ENA
SEQ2 Mode1
INT ENA
SEQ2 Mode0
INT FLAG
SEQ2
EVB SOC
EN SEQ2
ADCTRL2
070A2h MAXCONV2
2
MAXCONV2
1
MAXCONV2
0
MAXCONV1
3
MAXCONV1
2
MAXCONV1
1
MAXCONV1
0
MAXCONV
070A3h
CONV 3 CONV 3 CONV 3 CONV 3 CONV 2 CONV 2 CONV 2 CONV 2
CHSELSEQ1
070A3h CONV 1 CONV 1 CONV 1 CONV 1 CONV 0 CONV 0 CONV 0 CONV 0 CHSELSEQ1
070A4h
CONV 7 CONV 7 CONV 7 CONV 7 CONV 6 CONV 6 CONV 6 CONV 6
CHSELSEQ2
070A4h CONV 5 CONV 5 CONV 5 CONV 5 CONV 4 CONV 4 CONV 4 CONV 4 CHSELSEQ2
070A5h
CONV 11 CONV 11 CONV 11 CONV 11 CONV 10 CONV 10 CONV 10 CONV 10
CHSELSEQ3
070A5h CONV 9 CONV 9 CONV 9 CONV 9 CONV 8 CONV 8 CONV 8 CONV 8 CHSELSEQ3
070A6h
CONV 15 CONV 15 CONV 15 CONV 15 CONV 14 CONV 14 CONV 14 CONV 14
CHSELSEQ4
070A6h CONV 13 CONV 13 CONV 13 CONV 13 CONV 12 CONV 12 CONV 12 CONV 12 CHSELSEQ4
SEQ CNTR3 SEQ CNTR2 SEQ CNTR1 SEQ CNTR0
070A7h SEQ2
STATE 3
SEQ2
STATE 2
SEQ2
STATE 1
SEQ2
STATE 0
SEQ1
STATE 3
SEQ1
STATE 2
SEQ1
STATE 1
SEQ1
STATE 0
AUTO_SEQ_SR
070A8h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT0
070A8h D1 D0 0 0 0 0 0 0 RESULT0
070A9h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT1
070A9h D1 D0 0 0 0 0 0 0 RESULT1
070AAh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT2
070AAh D1 D0 0 0 0 0 0 0 RESULT2
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
117
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED)
070ABh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT3
070ABh D1 D0 0 0 0 0 0 0 RESULT3
070ACh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT4
070ACh D1 D0 0 0 0 0 0 0 RESULT4
070ADh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT5
070ADh D1 D0 0 0 0 0 0 0 RESULT5
070AEh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT6
070AEh D1 D0 0 0 0 0 00 0 RESULT6
070AFh
D9 D8 D7 D6 D5 D4 D3 D2
RESULT7
070AFh D1 D0 0 0 0 0 0 0 RESULT7
070B0h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT8
070B0h D1 D0 0 0 0 0 0 0 RESULT8
070B1h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT9
070B1h D1 D0 0 0 0 0 0 0 RESULT9
070B2h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT10
070B2h D1 D0 0 0 0 0 0 0 RESULT10
070B3h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT11
070B3h D1 D0 0 0 0 0 0 0 RESULT11
070B4h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT12
070B4h D1 D0 0 0 0 0 0 0 RESULT12
070B5h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT13
070B5h D1 D0 0 0 0 0 0 0 RESULT13
070B6h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT14
070B6h D1 D0 0 0 0 0 0 0 RESULT14
070B7h
D9 D8 D7 D6 D5 D4 D3 D2
RESULT15
070B7h D1 D0 0 0 0 0 0 0 RESULT15
070B8h Reserved
070B9h
to
070FFh
Illegal
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS
07100h
MDER
07100h MD3 MD2 ME5 ME4 ME3 ME2 ME1 ME0 MDER
07101h
TA5 TA4 TA3 TA2 AA5 AA4 AA3 AA2
TCR
07101h TRS5 TRS4 TRS3 TRS2 TRR5 TRR4 TRR3 TRR2 TCR
07102h
RFP3 RFP2 RFP1 RFP0 RML3 RML2 RML1 RML0
RCR
07102h RMP3 RMP2 RMP1 RMP0 OPC3 OPC2 OPC1 OPC0 RCR
07103h
SUSP CCR PDR DBO WUBA CDR
MCR
07103h ABO STM MBNR1 MBNR0 MCR
07104h
BCR2
07104h BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 BCR2
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
118 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
07105h
SBG SJW1 SJW0
BCR1
07105h SAM TSEG13 TSEG12 TSEG11 TSEG10 TSEG22 TSEG21 TSEG20BCR1
07106h
FER
ESR
07106h BEF SA1 CRCE SER ACKE BO EP EW ESR
07107h
GSR
07107h SMA CCE PDA RM TM GSR
07108h
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
CEC
07108h REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 CEC
07109h
MIF5 MIF4 MIF3 MIF2 MIF1 MIF0
CAN IFR
07109h RMLIF AAIF WDIF WUIF BOIF EPIF WLIF CAN_IFR
0710Ah
MIL MIM5 MIM4 MIM3 MIM2 MIM1 MIM0
CAN IMR
0710Ah EIL RMLIM AAIM WDIM WUIM BOIM EPIM WLIM CAN_IMR
0710Bh
LAMI LAM028 LAM027 LAM026 LAM025 LAM024
LAM0 H
0710Bh LAM023 LAM022 LAM021 LAM020 LAM019 LAM018 LAM017 LAM016 LAM0_H
0710Ch
LAM015 LAM014 LAM013 LAM012 LAM011 LAM010 LAM09 LAM08
LAM0 L
0710Ch LAM07LAM06 LAM05 LAM04 LAM03 LAM02 LAM01 LAM00LAM0_L
0710Dh
LAMI LAM128 LAM127 LAM126 LAM125 LAM124
LAM1 H
0710Dh LAM123 LAM122 LAM121 LAM120 LAM119 LAM118 LAM117 LAM116 LAM1_H
0710Eh
LAM115 LAM114 LAM113 LAM112 LAM111 LAM110 LAM19 LAM18
LAM1 L
0710Eh LAM17LAM16 LAM15 LAM14 LAM13 LAM12 LAM11 LAM10LAM1_L
0710Fh
to
071FFh
Illegal
Message Object #0
07200h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID0L
07200h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID0L
07201h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID0H
07201h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID0H
07202h
MSGCTRL0
07202h RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL0
07203h Reserved
07204h
D15 D14 D13 D12 D11 D10 D9 D8
MBX0A
07204h D7 D6 D5 D4 D3 D2 D1 D0 MBX0A
07205h
D15 D14 D13 D12 D11 D10 D9 D8
MBX0B
07205h D7 D6 D5 D4 D3 D2 D1 D0 MBX0B
07206h
D15 D14 D13 D12 D11 D10 D9 D8
MBX0C
07206h D7 D6 D5 D4 D3 D2 D1 D0 MBX0C
07207h
D15 D14 D13 D12 D11 D10 D9 D8
MBX0D
07207h D7 D6 D5 D4 D3 D2 D1 D0 MBX0D
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
119
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
Message Object #1
07208h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID1L
07208h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID1L
07209h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID1H
07209h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID1H
0720Ah
MSGCTRL1
0720Ah RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL1
0720Bh Reserved
0720Ch
D15 D14 D13 D12 D11 D10 D9 D8
MBX1A
0720Ch D7 D6 D5 D4 D3 D2 D1 D0 MBX1A
0720Dh
D15 D14 D13 D12 D11 D10 D9 D8
MBX1B
0720Dh D7 D6 D5 D4 D3 D2 D1 D0 MBX1B
0720Eh
D15 D14 D13 D12 D11 D10 D9 D8
MBX1C
0720Eh D7 D6 D5 D4 D3 D2 D1 D0 MBX1C
0720Fh
D15 D14 D13 D12 D11 D10 D9 D8
MBX1D
0720Fh D7 D6 D5 D4 D3 D2 D1 D0 MBX1D
Message Object #2
07210h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID2L
07210h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID2L
07211h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID2H
07211h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID2H
07212h
MSGCTRL2
07212h RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL2
07213h Reserved
07214h
D15 D14 D13 D12 D11 D10 D9 D8
MBX2A
07214h D7 D6 D5 D4 D3 D2 D1 D0 MBX2A
07215h
D15 D14 D13 D12 D11 D10 D9 D8
MBX2B
07215h D7 D6 D5 D4 D3 D2 D1 D0 MBX2B
07216h
D15 D14 D13 D12 D11 D10 D9 D8
MBX2C
07216h D7 D6 D5 D4 D3 D2 D1 D0 MBX2C
07217h
D15 D14 D13 D12 D11 D10 D9 D8
MBX2D
07217h D7 D6 D5 D4 D3 D2 D1 D0 MBX2D
Message Object #3
07218h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID3L
07218h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID3L
07219h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID3H
07219h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID3H
0721Ah
MSGCTRL3
0721Ah RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL3
0721Bh Reserved
0721Ch
D15 D14 D13 D12 D11 D10 D9 D8
MBX3A
0721Ch D7 D6 D5 D4 D3 D2 D1 D0 MBX3A
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
120 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
0721Dh
D15 D14 D13 D12 D11 D10 D9 D8
MBX3B
0721Dh D7 D6 D5 D4 D3 D2 D1 D0 MBX3B
0721Eh
D15 D14 D13 D12 D11 D10 D9 D8
MBX3C
0721Eh D7 D6 D5 D4 D3 D2 D1 D0 MBX3C
0721Fh
D15 D14 D13 D12 D11 D10 D9 D8
MBX3D
0721Fh D7 D6 D5 D4 D3 D2 D1 D0 MBX3D
Message Object #4
07220h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID4L
07220h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID4L
07221h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID4H
07221h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID4H
07222h
MSGCTRL4
07222h RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL4
07223h Reserved
07224h
D15 D14 D13 D12 D11 D10 D9 D8
MBX4A
07224h D7 D6 D5 D4 D3 D2 D1 D0 MBX4A
07225h
D15 D14 D13 D12 D11 D10 D9 D8
MBX4B
07225h D7 D6 D5 D4 D3 D2 D1 D0 MBX4B
07226h
D15 D14 D13 D12 D11 D10 D9 D8
MBX4C
07226h D7 D6 D5 D4 D3 D2 D1 D0 MBX4C
07227h
D15 D14 D13 D12 D11 D10 D9 D8
MBX4D
07227h D7 D6 D5 D4 D3 D2 D1 D0 MBX4D
Message Object #5
07228h
IDL15 IDL14 IDL13 IDL12 IDL11 IDL10 IDL9 IDL8
MSGID5L
07228h IDL7IDL6 IDL5 IDL4 IDL3 IDL2 IDL1 IDL0MSGID5L
07229h
IDE AME AAM IDH28 IDH27 IDH26 IDH25 IDH24
MSGID5H
07229h IDH23 IDH22 IDH21 IDH20 IDH19 IDH18 IDH17 IDH16 MSGID5H
0722Ah
MSGCTRL5
0722Ah RTR DLC3 DLC2 DLC1 DLC0 MSGCTRL5
0722Bh Reserved
0722Ch
D15 D14 D13 D12 D11 D10 D9 D8
MBX5A
0722Ch D7 D6 D5 D4 D3 D2 D1 D0 MBX5A
0722Dh
D15 D14 D13 D12 D11 D10 D9 D8
MBX5B
0722Dh D7 D6 D5 D4 D3 D2 D1 D0 MBX5B
0722Eh
D15 D14 D13 D12 D11 D10 D9 D8
MBX5C
0722Eh D7 D6 D5 D4 D3 D2 D1 D0 MBX5C
0722Fh
D15 D14 D13 D12 D11 D10 D9 D8
MBX5D
0722Fh D7 D6 D5 D4 D3 D2 D1 D0 MBX5D
07230h
to
073FFh
Illegal
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
121
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS EVA
07400h
T2STAT T1STAT T2TOADC T1TOADC(1)
GPTCONA
07400h T1TOADC(0) TCOMPOE T2PIN T1PIN GPTCONA
07401h
D15 D14 D13 D12 D11 D10 D9 D8
T1CNT
07401h D7 D6 D5 D4 D3 D2 D1 D0 T1CNT
07402h
D15 D14 D13 D12 D11 D10 D9 D8
T1CMPR
07402h D7 D6 D5 D4 D3 D2 D1 D0 T1CMPR
07403h
D15 D14 D13 D12 D11 D10 D9 D8
T1PR
07403h D7 D6 D5 D4 D3 D2 D1 D0 T1PR
07404h
FREE SOFT TMODE1 TMODE0 TPS2 TPS1 TPS0
T1CON
07404h TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR T1CON
07405h
D15 D14 D13 D12 D11 D10 D9 D8
T2CNT
07405h D7 D6 D5 D4 D3 D2 D1 D0 T2CNT
07406h
D15 D14 D13 D12 D11 D10 D9 D8
T2CMPR
07406h D7 D6 D5 D4 D3 D2 D1 D0 T2CMPR
07407h
D15 D14 D13 D12 D11 D10 D9 D8
T2PR
07407h D7 D6 D5 D4 D3 D2 D1 D0 T2PR
07408h
FREE SOFT TMODE1 TMODE0 TPS2 TPS1 TPS0
T2CON
07408h T2SWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR T2CON
07409h
to
07410h
Illegal
FULL AND SIMPLE COMPARE UNIT REGISTERS EVA
07411h CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE PDPINTA
STATUS COMCONA
07411h
COMCONA
07412h Illegal
07413h
SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0
ACTRA
07413h CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0 ACTRA
07414h
Illegal
07414h Illegal
07415h
DBT3 DBT2 DBT1 DBT0
DBTCONA
07415h EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 DBTCONA
07416h Illegal
07417h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR1
07417h D7 D6 D5 D4 D3 D2 D1 D0 CMPR1
07418h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR2
07418h D7 D6 D5 D4 D3 D2 D1 D0 CMPR2
07419h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR3
07419h D7 D6 D5 D4 D3 D2 D1 D0 CMPR3
0741Ah
to
0741Fh
Illegal
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
122 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
CAPTURE UNIT REGISTERS EVA
07420h
CAPRES CAPQEPN CAP3EN CAP3TSEL CAP12TSEL CAP3TOADC
CAPCONA
07420h CAP1EDGE CAP2EDGE CAP3EDGE CAPCONA
07421h Illegal
07422h
CAP3FIFO CAP2FIFO CAP1FIFO
CAPFIFOA
07422h CAPFIFOA
07423h
D15 D14 D13 D12 D11 D10 D9 D8
CAP1FIFO
07423h D7 D6 D5 D4 D3 D2 D1 D0 CAP1FIFO
07424h
D15 D14 D13 D12 D11 D10 D9 D8
CAP2FIFO
07424h D7 D6 D5 D4 D3 D2 D1 D0 CAP2FIFO
07425h
D15 D14 D13 D12 D11 D10 D9 D8
CAP3FIFO
07425h D7 D6 D5 D4 D3 D2 D1 D0 CAP3FIFO
07426h Illegal
07427h
D15 D14 D13 D12 D11 D10 D9 D8
CAP1FBOT
07427h D7 D6 D5 D4 D3 D2 D1 D0 CAP1FBOT
07428h
D15 D14 D13 D12 D11 D10 D9 D8
CAP2FBOT
07428h D7 D6 D5 D4 D3 D2 D1 D0 CAP2FBOT
07429h
D15 D14 D13 D12 D11 D10 D9 D8
CAP3FBOT
07429h D7 D6 D5 D4 D3 D2 D1 D0 CAP3FBOT
0742Ah
to
0742Bh
Illegal
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS
0742Ch
—————T1OFINT
ENA
T1UFINT
ENA
T1CINT
ENA
EVAIMRA
0742Ch T1PINT
ENA CMP3INT
ENA
CMP2INT
ENA
CMP1INT
ENA
PDPINTA
ENA
EVAIMRA
0742Dh T2OFINT
ENA
T2UFINT
ENA
T2CINT
ENA
T2PINT
ENA
EVAIMRB
0742Eh CAP3INT
ENA
CAP2INT
ENA
CAP1INT
ENA
EVAIMRC
0742Fh
—————T1OFINT
FLAG
T1UFINT
FLAG
T1CINT
FLAG
EVAIFRA
0742Fh T1PINT
FLAG CMP3INT
FLAG
CMP2INT
FLAG
CMP1INT
FLAG
PDPINTA
FLAG
EVAIFRA
07430h T2OFINT
FLAG
T2UFINT
FLAG
T2CINT
FLAG
T2PINT
FLAG
EVAIFRB
07431h CAP3INT
FLAG
CAP2INT
FLAG
CAP1INT
FLAG
EVAIFRC
07432h
to
074FFh
Illegal
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
123
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS EVB
07500h
T4STAT T3STAT T4TOADC T3TOADC(1)
GPTCONB
07500h T3TOADC(0) TCOMPOEB T4PIN T3PIN GPTCONB
07501h
D15 D14 D13 D12 D11 D10 D9 D8
T3CNT
07501h D7 D6 D5 D4 D3 D2 D1 D0 T3CNT
07502h
D15 D14 D13 D12 D11 D10 D9 D8
T3CMPR
07502h D7 D6 D5 D4 D3 D2 D1 D0 T3CMPR
07503h
D15 D14 D13 D12 D11 D10 D9 D8
T3PR
07503h D7 D6 D5 D4 D3 D2 D1 D0 T3PR
07504h
FREE SOFT TMODE1 TMODE0 TPS2 TPS1 TPS0
T3CON
07504h TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR T3CON
07505h
D15 D14 D13 D12 D11 D10 D9 D8
T4CNT
07505h D7 D6 D5 D4 D3 D2 D1 D0 T4CNT
07506h
D15 D14 D13 D12 D11 D10 D9 D8
T4CMPR
07506h D7 D6 D5 D4 D3 D2 D1 D0 T4CMPR
07507h
D15 D14 D13 D12 D11 D10 D9 D8
T4PR
07507h D7 D6 D5 D4 D3 D2 D1 D0 T4PR
07508h
FREE SOFT TMODE1 TMODE0 TPS2 TPS1 TPS0
T4CON
07508h T4SWT3 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT3PR T4CON
07509h
to
07510h
Reserved
FULL AND SIMPLE COMPARE UNIT REGISTERS EVB
07511h CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOEB PDPINTB
STATUS COMCONB
07511h
COMCONB
07512h Reserved
07513h
SVRDIR D2 D1 D0 CMP12ACT1 CMP12ACT0 CMP11ACT1 CMP11ACT0
ACTRB
07513h CMP10ACT1 CMP10ACT0 CMP9ACT1 CMP9ACT0 CMP8ACT1 CMP8ACT0 CMP7ACT1 CMP7ACT0 ACTRB
07514h
Reserved
07514h Reserved
07515h
DBT3 DBT2 DBT1 DBT0
DBTCONB
07515h EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 DBTCONB
07516h Reserved
07517h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR4
07517h D7 D6 D5 D4 D3 D2 D1 D0 CMPR4
07518h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR5
07518h D7 D6 D5 D4 D3 D2 D1 D0 CMPR5
07519h
D15 D14 D13 D12 D11 D10 D9 D8
CMPR6
07519h D7 D6 D5 D4 D3 D2 D1 D0 CMPR6
0751Ah
to
0751Fh
Reserved
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
124 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
CAPTURE UNIT REGISTERS EVB
07520h
CAPRES CAPQEPN CAP6EN CAP6TSEL CAP45SEL CAP6TOADC
CAPCONB
07520h CAP4EDGE CAP5EDGE CAP6EDGE CAPCONB
07521h Reserved
07522h
CAP6FIFO CAP5FIFO CAP4FIFO
CAPFIFOB
07522h CAPFIFOB
07523h
D15 D14 D13 D12 D11 D10 D9 D8
CAP4FIFO
07523h D7 D6 D5 D4 D3 D2 D1 D0 CAP4FIFO
07524h
D15 D14 D13 D12 D11 D10 D9 D8
CAP5FIFO
07524h D7 D6 D5 D4 D3 D2 D1 D0 CAP5FIFO
07525h
D15 D14 D13 D12 D11 D10 D9 D8
CAP6FIFO
07525h D7 D6 D5 D4 D3 D2 D1 D0 CAP6FIFO
07526h Reserved
07527h
D15 D14 D13 D12 D11 D10 D9 D8
CAP4FBOT
07527h D7 D6 D5 D4 D3 D2 D1 D0 CAP4FBOT
07528h
D15 D14 D13 D12 D11 D10 D9 D8
CAP5FBOT
07528h D7 D6 D5 D4 D3 D2 D1 D0 CAP5FBOT
07529h
D15 D14 D13 D12 D11 D10 D9 D8
CAP6FBOT
07529h D7 D6 D5 D4 D3 D2 D1 D0 CAP6FBOT
0752Ah
to
0752Bh
Reserved
EVENT MANAGER (EVB) INTERRUPT CONTROL REGISTERS
0752Ch
—————T3OFINT
ENA
T3UFINT
ENA
T3CINT
ENA
EVBIMRA
0752Ch T3PINT
ENA CMP6INT
ENA
CMP5INT
ENA
CMP4INT
ENA
PDPINTB
ENA
EVBIMRA
0752Dh T4OFINT
ENA
T4UFINT
ENA
T4CINT
ENA
T4PINT
ENA
EVBIMRB
0752Eh —————CAP6INT
ENA
CAP5INT
ENA
CAP4INT
ENA
EVBIMRC
0752Fh
—————T3OFINT
FLAG
T3UFINT
FLAG
T3CINT
FLAG
EVBIFRA
0752Fh T3PINT
FLAG CMP6INT
FLAG
CMP5INT
FLAG
CMP4INT
FLAG
PDPINTB
FLAG
EVBIFRA
07530h T4OFINT
FLAG
T4UFINT
FLAG
T4CINT
FLAG
T4PINT
FLAG
EVBIFRB
07531h —————CAP6INT
FLAG
CAP5INT
FLAG
CAP4INT
FLAG
EVBIFRC
07532h
to
0753Fh
Reserved
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
125
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
KEY REGISTERS
077F0h
High Word of the 64 Bit KEY Register
KEY3
077F0h High Word of the 64-Bit KEY Register KEY3
077F1h
Third Word of the 64 Bit KEY Register
KEY2
077F1h Third Word of the 64-Bit KEY Register KEY2
077F2h
Second Word of the 64 Bit KEY Register
KEY1
077F2h Second Word of the 64-Bit KEY Register KEY1
077F3h
Low Word of the 64 Bit KEY Register
KEY0
077F3h Low Word of the 64-Bit KEY Register KEY0
PROGRAM MEMORY SPACE FLASH REGISTERS
0xx00h
PMPC
0xx00h PWR DWN KEY1 KEY0 EXEC PMPC
0xx01h
WSVER EN PRECND
Mode1
CTRL
0xx01h PRECND
Mode0
ENG/R
Mode2
ENG/R
Mode1
ENG/R
Mode0 FCM3 FCM2 FCM1 FCM0
CTRL
0xx02h
WADDR
0xx02h WADDR
0xx03h
WDATA
0xx03h WDATA
0xx04h
TCR
0xx04h TCR
0xx05h
ENAB
0xx05h ENAB
0xx06h SECT 4
ENABLE
SECT 3
ENABLE
SECT 2
ENABLE
SECT 1
ENABLE
SECT
I/O MEMORY SPACE
0FF0Fh
FCMR
0FF0Fh FCMR
WAIT-STATE GENERATOR CONTROL REGISTER
0FFFFh
BVIS.1 BVIS.0 ISWS.2
WSGR
0FFFFh ISWS.1 ISWS.0 DSWS.2 DSWS.1 DSWS.0 PSWS.2 PSWS.1 PSWS.0 WSGR
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
Register shown with bits set in register mode.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
126 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
MECHANICAL DATA
Table 20 through Table 23 provide the typical thermal resistance characteristics for each mechanical
package.
Table 20. Typical Thermal Resistance Characteristics
for the PAG Package
PARAMETER DESCRIPTION °C/W
ΘJA Junction-to-ambient 42
ΘJC Junction-to-case 7
Ψjt Junction-to-top of package 0.5
Table 21. Typical Thermal Resistance Characteristics
for the PG Package
PARAMETER DESCRIPTION °C/W
ΘJA Junction-to-ambient 35
ΘJC Junction-to-case 11
Ψjt Junction-to-top of package 1.0
Table 22. Typical Thermal Resistance Characteristics
for the PGE Package
PARAMETER DESCRIPTION °C/W
ΘJA Junction-to-ambient 32
ΘJC Junction-to-case 8
Ψjt Junction-to-top of package 0.5
Table 23. Typical Thermal Resistance Characteristics
for the PZ Package
PARAMETER DESCRIPTION °C/W
ΘJA Junction-to-ambient 42
ΘJC Junction-to-case 8
Ψjt Junction-to-top of package 0.5
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
127
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
MECHANICAL DATA (CONTINUED)
The following mechanical package diagram(s) reflect the most current released mechanical data available
for the designated device(s).
PACKAGE OPTION ADDENDUM
www.ti.com 23-Sep-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320LF2402APGA NRND QFP PG 64 66 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 85 320LF2402APGA
TMS
TMS320LF2402APGAR NRND QFP PG 64 400 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 85 320LF2402APGA
TMS
TMS320LF2402APGS NRND QFP PG 64 66 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 125 320LF2402APGS
TMS
TMS320LF2403APAG4 NRND TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LF2403APAGA
TMS320
TMS320LF2403APAGA NRND TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LF2403APAGA
TMS320
TMS320LF2403APAGS NRND TQFP PAG 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 LF2403APAGS
TMS320
TMS320LF2406APZA NRND LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA
TMS
TMS320LF2406APZAG4 NRND LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA
TMS
TMS320LF2406APZAR NRND LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA
TMS
TMS320LF2406APZS NRND LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 320LF2406APZS
TMS
TMS320LF2407APGEA NRND LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 320LF2407APGEA
TMS
TMS320LF2407APGEG4 NRND LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 320LF2407APGEA
TMS
TMS320LF2407APGES NRND LQFP PGE 144 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 320LF2407APGES
TMS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Sep-2017
Addendum-Page 2
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MQFP008 – JULY 1998
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PG (R-PQFP-G64) PLASTIC QUAD FLATPACK
4040101/B 03/95
0,15 NOM
18,0014,20
13,80 17,20
32
33
20
19
12,00 TYP
0,25
1,10
0,70
0,10 MIN
Gage Plane
51
1
18,00 TYP
52
64
23,20
24,00
19,80
20,20
3,10 MAX
2,70 TYP
0,25
0,45
0°–10°
Seating Plane
0,10
1,00 M
0,20
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
MECHANICAL DATA
MTQF013AOCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,17
0,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,05
0,95
11,80
12,20
1,20 MAX
10,20 SQ
17
32
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF017AOCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
4040147/C 10/96
0,27
72
0,17
37
73
0,13 NOM
0,25
0,75
0,45
0,05 MIN
36
Seating Plane
Gage Plane
108
109
144
SQ
SQ
22,20
21,80
1
19,80
17,50 TYP
20,20
1,35
1,45
1,60 MAX
M
0,08
0°–7°
0,08
0,50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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