MK32VT1632-10YC (98.09.03)
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Semiconductor
MK32VT1632-10YC
16,777,216 Word x 32 Bit SYNCHRONOUS DYNA MIC RAM MODULE (2BANK):
DESCRIPTION
The Oki MK32VT1632-10YC is a fully decoded, 16,777,216 x 32bit synchronous
dynamic random access memory composed of eight 64Mb DRAMs (8Mx8) in TSOP
packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line
Package supports any appli cation where hi gh density and large capacity of storage
memory are required, like for example PCs or servers.
FEATURES
• 16-Meg Word x 32-bit (2Bank 4Byte) organization
• 100-pin Dual Inline Memory Module
• All DQ Pins have 10Ω Damping Resister
• Single 3.3V power supply, ±0.3V tolerance
• Input :LVTTL compatible
• Output :LVTTL com patible
• Refresh : 4,096 cycles/64 ms
• Programmable data transfer m ode
•/CAS latency (2, 3)
• B urst length (2, 4, 8)
•Data scramble (sequential, interleave)
• /CAS before /RA S auto-refresh, S elf-refresh capability
• Serial Presence Detect (SPD) With EEPROM
PRODUCT ORGANIZATION
Operation A ccess Time (M ax.)
Pr odu ct N am e Frequ en cy (M ax.) tAC2 tAC3
MK 32VT1632-10YC 100 MH z 9.0ns 9.0ns
Note. Specification are su bject to ch an ge with out n otice.
MK32VT1632-10YC (98.09.03)
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BLOCK DIAGRAM
/
CS0
CKE0
DQMB0
DQMB1
DQ0
DQ7
DQ0
DQ7
DQ8
DQ15
DQM CKE
/
CS
DQMB2
DQMB3
DQ0
DQ7
DQ16
DQ23
DQ0
DQ7
DQ24
DQ31
DQM CKE
/
CS
DQM CKE
/
CS
/
CS2
DQ0
DQ7
DQM CKE
/
CS DQ0
DQ7
DQM CKE
/
CS
DQ0
DQ7
DQM CKE
/
CS
DQ0
DQ7
DQM CKE
/
CS
DQ0
DQ7
DQM CKE
/
CS
/
CS1
/
CS3
CKE1
Vcc
Vss SDRAMs
0.22uF x8
/
RAS,/CAS,/WE
A0-A11,BA0,BA1
á
18
SCL SDA
A0 A1 A2
SA0 SA1 SA2
Serial PD
3
4
CLK0
1
2CLK1 6
8
7
5
6
3
4
57
8
1
2
9
Note. The Value of all resis tors is 10Ω.
MODULE OUTLINE
(Front)
(Back) 1
51 6
56 7
57 22
72 23
73 50
100
MK32VT1632-10YC (98.09.03)
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PIN CONFIGURAT ION
Fro nt side Back sid e Fro nt side Back sid e
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 VSS 51 VSS 26 VSS 76 VSS
2 DQ0 52 DQ8 27 CKE0 77 NC
3 DQ1 53 DQ9 28 /WE 78 NC
4 DQ2 54 DQ10 29 /CS0 79 /CS1
5 DQ3 55 DQ11 30 /CS2 80 /CS3
6 VCC 56 VCC 31 VCC 81 VCC
7 DQ4 57 DQ12 32 NC 82 NC
8 DQ5 58 DQ13 33 NC 83 NC
9 DQ6 59 DQ14 34 NC 84 NC
10 DQ7 60 DQ15 35 NC 85 NC
11 DQMB0 61 DQMB1 36 VSS 86 VSS
12 VSS 62 VSS 37 DQMB2 87 DQMB3
13 A0 63 A1 38 DQ16 88 DQ24
14 A2 64 A3 39 DQ17 89 DQ25
15 A4 65 A5 40 DQ18 90 DQ26
16 A6 66 A7 41 DQ19 91 DQ27
17 A8 67 A9 42 VCC 92 VCC
18 A10 68 BA0 43 DQ20 93 DQ28
19 BA1 69 A11 44 DQ21 94 DQ29
20 NC 70 NC 45 DQ22 95 DQ30
21 VCC 71 VCC 46 DQ23 96 DQ31
22 NC 72 /RAS 47 VSS 97 VSS
23 NC 73 /CAS 48 SDA 98 SA0
24 NC 74 NC 49 SCL 99 SA1
25 CLK0 75 CLK1 50 VCC 100 SA2
Pin Name Function Pin Name Function
Vcc Power Supply ( 3.3V) / WE Write Enable
Vss Ground (0V) DQMB # Data I nput / O utput Mask
CLK# S y stem Clock DQ# Data Input / O utput
/CS# Chip Select SDA Data I/O for SPD
CKE# Clock E nable SCL CLK input for S P D
A0-A11 Address SA# Socket Posi t ion Address f or SPD
BA0, B A 1 Bank Select A ddr ess N. C No Connection
/RAS Row Address St r obe
/CAS Col umn Addr ess Strobe
MK32VT1632-10YC (98.09.03)
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SERIAL PRESENCE DET ECT
Byte
No. SPD
Hex Value Remark Notes
080 Defines the number of by tes writt en into
SPD mem ory 128 byte
108 Tot al number of byt es of SPD memory 256 byte
204 Fundamental mem or y type S DRA M
30C Num ber of r ows 12 rows
409 Num ber of c olumns 9 col umns
502 Num ber of module banks 2 bank
620 Data widt h of this assembl y 32 bits
700 ... Data width continuation 0
801 Vol tage interface level LVTTL
9A0 Cycl e time (CL=3) CL=3 tCC3=10ns
10 90 Access ti me f rom CLK (CL=3) CL=3 tAC3=9ns
11 00 DIMM c onfigurat ion ty pe None Parity
12 80 Refresh rate / type Normal / Sel f
13 08 Pri mary SDRAM width x8
14 00 Error checking SDRAM width
15 01 Mi nimum CLK delay tCCD: 1 CLK
16 0E Burst l engths supported 2, 4, 8
17 04 Num ber of bank s on each SDRA M 4 banks
18 06 /CAS latenc y 2, 3
19 01 /CS latenc y 0
20 01 /WE l atency 0
21 00 SDRAM module att r ibutes
22 06 SDRAM devic e attributes : General
23 F0 Cy c le time (CL= 2) CL=2 tCC2=15ns
24 90 Access ti me f rom CLK (CL=2) CL=2 tAC2=9ns
25 00 Cycle tim e ( CL=1) Not support
26 00 Access tim e from CLK (CL= 1) Not support
27 1E Minimum ROW pulse width tRP=30ns
28 14 /RAS to /RAS bank delay tRRD=20ns
29 1E /RAS to /CAS delay tRCD=30ns
30 3C Mi nimum /RAS prec har ge time tRAS=60ns
31 08 Density of eac h bank on module 32MB
32 30 Command and addr ess signal input setup time 3ns
33 10 Com mand and address signal input hol d t im e 1ns
34 30 Data signal i nput setup tim e 3ns
35 10 Data signal i nput hold time 1ns
36-61 00-00 R.F.U
62 02 SPD dat a r evisi on c ode 0.2
63 33 Checksum for by te 0-62
64-71 41, 45, 20, 20, 20, 20, 20, 20 Manufact ur er ’s JEDE C ID code
72 01 / 06 Manufact ur ing l oc ation
73-90 4D,4B,33,32,56,54,31,36,33,
32
,
2D
,
31
,
30
,
59
,
43
,
20
,
20
,
20 Manufact ur er ’s part number MK32VT1632-10YC
91, 92 20, 20 Revision code
93-125 00-00 R.F.U
126 66 Int el specificat ion frequency 66MHz
127 06 Int el specificat ion /CA S latenc y CL=2, 3
128-255 F F-FF Unused storage locations
MK32VT1632-10YC (98.09.03)
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EL ECTRICAL CHARACTERI STICS
Absolute Ma ximum Ratings
Rating Symbol Value Unit
Vol tage on any pi n r elative to Vss VIN, VOUT -0.5 to Vcc+0.5 V
Vcc supply voltage Vcc, VccQ -0.5 to 4.6 V
Stor age tem per ature Tstg - 55 t o 125 °C
Power dissipation PD*8W
Short circuit current IOS 50 mA
Operating tem per ature Topr 0 t o 70 °C
*: Ta=25°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter Symbol Min. Typ. Max. Unit
Power supply voltage Vcc, VccQ 3.0 3.3 3.6 V
Input high voltage VIH 2.0 - Vcc+0.3 V
Input low voltage VIL -0.3 - 0.8 V
Capacitance
(Vcc = 3.3V ± 0.3V , Ta = 25°C f = 1M Hz )
Parameter Symbol Max. Unit
Input c apac itanc e ( A 0- A 11, BA0, B A 1, /RAS , /CAS , /WE) CIN1 40 pF
Input c apac itanc e ( /CS0, /CS1, /CS2, /CS3) CIN2 20 pF
Input c apac itanc e ( DQMB0-DQMB3) CIN3 10 pF
Input c apac itanc e ( CK E 0, CKE1) CIN4 20 pF
I/O capacitance (DQ 0- DQ31) CI/O 14 pF
Input c apac itanc e ( CLK 0, CLK1) CCLK 50 pF
MK32VT1632-10YC (98.09.03)
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DC CHARACTE RISTI CS
(Vcc = 3.3V ± 0. 3V , Ta = 0 to 70°C)
Condition Module Spec.
Parameter Symbol CKE Others Min. Max. Unit Note
Out put High V oltage VOH -IOH = -
2.0mA 2.4 -V
Out put Low Voltage VOL -IOL = 2.0mA -0.4V
Input Leak age Cur r ent ILI ---80 80 uA
Out put Leakage
Current ILO ---20 20 uA
Aver age P ower Supply
Current
(Operating) ICC1CKE ≥ VIH tCC=min.
tRC=min.
No Burst - 620 mA 1, 2
Power Supply Cur r ent
(St and by ) ICC2CKE ≥ VIH tCC=min. - 320 mA 3
Aver age P ower
Suppl y Cur r ent
(Cl oc k S uspension) ICC3S CKE ≤ VIL tCC=min. - 220 mA 2
Aver age P ower
Suppl y Cur r ent
(Acti ve Stand by) ICC3CKE ≥ VIH,
/CS ≥ VIH tCC=min. - 480 mA 3
Power Supply
Current
(Burst) ICC4CKE ≥ VIH tCC=min. - 780 mA 1, 2
Power Supply
Current
(Auto-Refresh) ICC5CKE ≥ VIH tCC=min.
tRC=min. - 900 mA 2
Aver age P ower
Suppl y Cur r ent
(Self-Refresh) ICC6CKE ≤ 0.2V tCC=min. -16mA
Aver age P ower
Suppl y Cur r ent
(Power down) ICC7CKE ≤ VIL tCC=min. -16mA
Notes: 1. Meas ur ed with the out put open.
2. Address and dat a can be changed once or not be changed during one cycle.
3. Address and dat a can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
/CAS Latency Burst Type Burst Length
A6 A5 A4 CL A3 BT A2 A1 A0 BT=0 BT=1
0 0 0 Reserved 0 Sequential 0 0 0 Reserved Reserved
0 0 1 Reserved 1 Interleave 0 0 1 2 2
010 2 010 4 4
011 3 011 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Reserved Reserved
Note: A7, A8, A10, A11, BA0, BA1 and All should stay " L" during mode set cycle.
MK32VT1632-10YC (98.09.03)
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POWER ON S EQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the Vcc voltage has reached the specified level, take a pause of 200µs or more
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
MK32VT1632-10YC (98.09.03)
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AC CHARACTERI STIC (Vcc = 3.3V ± 0.3V, Ta = 0 ~70° C)
NOTE 1, 2 .
Parameter Symbol Module Spec. Unit Note
Min. Max.
Cloc k Cy c le Time CL=3 tCC 10 - ns
CL=2 15 - ns
Access Time from Clock CL=3 tAC - 9 ns 3, 4
CL=2 - 9 ns 3, 4
Clock "H" Pulse Time tCH 3-ns
Clock "L" Pulse Time tCL 3-ns
Input S etup Tim e tSI 3-ns
Input Hold Time tHI 1-ns
Out put Low Impedanc e Time from Clock tOLZ 3-ns
Out put High Im pedanc e Time from Clock tOHZ -8ns
Out put Hold fr om Clock tOH 3-ns3
/RAS Cycle Time tRC 90 - ns
/RAS Precharge Ti me tRP 30 - ns
/RAS Active Tim e tRAS 60 100,000 ns
/RAS to /CAS Delay Time tRCD 30 - ns
Wr ite Rec overy T ime tWR 15 - ns
/RAS to /RAS Bank Activ e Delay Time tRRD 20 - ns
Refresh Ti me tREF -64ms
Power-down Exit Set-up Ti me tPDE tSI+1CLK - ns
Input Level Transit ion Time tT-3ns
/CAS to /CAS Delay Time (Min) ICCD 1 Cycle
Cloc k Disable T ime from CKE ICKE 1 Cycle
Data O utput High Impedance T ime from
DQMB IDOZ 2 Cycle
Data I nput Mask Tim e fr om DQ M B IDOD 0 Cycle
Data I nput Tim e fr om Wri te Com mand IDWD 0 Cycle
Data O utput High Impedance
Tim e fr om Pr ec har ge Command IROH 2 Cycle
Act ive Command Input Tim e fr om MODE
Register S et Com mand I nput (Min) IMRD 3 Cycle
Wr ite Command Input Tim e fr om O utput IOWD 2 Cycle
NOTES:
1) AC meas ur em ents assum e tT=1ns.
2) The r eference level for tim ing of input signals is 1.4V.
3) This param eter is meas ur ed with a load circuit equivalent to 1 TT L load and 50pF
(R
Load is 50ohm) .
4) An acc es s time is meas ur ed at 1.4V.
5) If tT is longer t han 1ns , the reference level for tim ing of input signals ar e VIH and VIL.
OUTPUT 50pF
OUTPUT LOAD
50Ω
1.4v
MK32VT1632-10YC (98.09.03)
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FUNCTION TRUTH TABLE (Table1) (1/2)
Current State /CS /RAS /CAS /WE BA ADDR Action
Idle H X X X X X NOP
LHHHXXNOP
L H H L BA X ILLEGAL 2
L H L X BA CA ILLEGAL 2
L L H H BA RA Row Active
L L H L BA A10 NOP 4
L L L H X X Auto-Re fresh or Self-Re fresh 5
L L L L L OP Code Mode Registe r write
Row Active H X X X X X NOP
LHHXXXNOP
L H L H BA CA, A10 Re ad
L H L L BA CA, A10 Write
L L H H BA RA ILLEGAL 2
L L H L BA A10 Precharge
LLLXXXILLEGAL
Re ad H X X X X X NOP (Continue Row Active after Burst e nds)
L H H H X X NOP (Continue Row Active after Burst e nds)
L H H L BA X Burst Stop
L H L H BA C A, A1 0 Te rm Burs t, s ta rt n ew B u rs t R ea d 3
L H L L BA CA, A 1 0 Term Burst, s ta rt n ew Burst Write 3
L L H H BA RA ILLEGAL 2
L L H L BA A10 Term Burst, execute Row Precharge
LLLXXXILLEGAL
Write H X X X X X NOP (Co n tin u e R o w Ac tiv e after B u rs t en d s)
L H H H X X NOP (Continue Row Active after Burst e nds)
L H H L BA X Burst Stop
L H L H BA C A, A1 0 Te rm Burs t, s ta rt n ew B u rs t R ea d 3
L H L L BA CA, A 1 0 Term Burst, s ta rt n ew Burst Write 3
L L H H BA RA ILLEGAL 2
L L H L BA A10 Term Burst, execute Row Precharge 3
LLLXXXILLEGAL
Re ad with H X X X X X NOP (Continue Burst to End and e nter Row Pre charge)
Auto Pre charge L H H H X X NOP (Continue Burst to End and enter Row Pre charge)
L H H L BA X ILLEGAL 2
L H L H BA CA, A10 ILLEGAL 2
L H L L X X ILLEGAL
L L H X BA RA, A10 ILLEGAL 2
LLLXXXILLEGAL
Write with H X X X X X NOP (Continue Burst to End and ente r Row Precharge )
Auto Pre charge L H H H X X NOP (Continue Burst to End and enter Row Pre charge)
L H H L BA X ILLEGAL 2
L H L H BA CA, A10 ILLEGAL 2
L H L L X X ILLEGAL
L L H X BA RA, A10 ILLEGAL 2
LLLXXXILLEGAL
MK32VT1632-10YC (98.09.03)
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FUNCTION TRUTH TABLE (Table1) (2/2)
Current State /CS /RAS /CAS /WE BA ADDR Action
Precharge H X X X X X NOP
Æ
Idle after tRP
LHHHXXNOP
Æ
Idle after tRP
L H H L BA X ILLEGAL 2
L H L X BA CA ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10 NOP 4
LLLXXXILLEGAL
Write H X X X X X NOP
Recovery L H H H X X NOP
L H H L BA X ILLEGAL 2
L H L X BA CA ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10 ILLEGAL 2
LLLXXXILLEGAL
Row Active H X X X X X NOP Row Active afte r tRCD
L H H H X X NOP Row Active after tRCD
L H H L BA X ILLEGAL 2
L H L X BA CA ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10 ILLEGAL 2
LLLXXXILLEGAL
Refresh H X X X X X NOP
Æ
Idle after tRC
LHHXXXNOP
Æ
Idle after tRC
L H L X X X ILLEGAL
L L H X X X ILLEGAL
LLLXXXILLEGAL
Auto Resister H X X X X X NOP
Access L H H H X X NOP
L H H L X X ILLEGAL
L H L X X X ILLEGAL
L L X X X X ILLEGAL
ABBREVIATIONS
RA = R ow Addres s BA = Bank Addr es s NOP = No Operati on c omm and
CA = Column Address AP = Auto Precharge
Notes:
1. All inputs will be enabled when CKE i s set hi gh for at least 1 cycl e pr ior to the i nputs.
2. I ll egal to bank i n spec i fied state, but m ay be l egal i n s ome c ases depending on the s tate of
bank sel ecti on.
3. Satisfy the tim i ng of tCCD and tWR to prev ent bus c ontention.
4. NOP to bank prec har ging or i n i dle s tate. Pr echar ges acti vated bank by BA or A10.
5. I ll egal if any bank i s not i dl e.
MK32VT1632-10YC (98.09.03)
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FUNCTION TRUTH TABLE (CKE ) (Tabl e2)
Current State (n) CKEn-1 CKEn /CS /RAS /CAS /WE ADDR Action
Self R efresh H X X X X X X INV A L ID
L H H X X X X Exit Self R efresh
Æ
ABI
L H L H H H X Ex it S elf R efresh
Æ
ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self Refresh)
Power Down H X X X X X X INVALID
L H H X X X X Exit Power Down
Æ
ABI
L H L H H H X Ex it Power Down
Æ
ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L X X X X ILLEGAL 6
L L X X X X X NOP (Continue powe r down mode)
All Ban k s idle 6H H X X X X X Refer to Table 1
(ABI) H L H X X X X Ente r Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H L X ILLEGAL
H L L L L H X Enter Self Re fres h
H L L L L L X ILLEGAL
LLXXXXXNOP
Any State H H X X X X X Refer to Ope rations in Table 1
Other than H L X X X X X Begin Clock Suspe nd N ex t Cycle
Liste d Above L H X X X X X Enable Clock of Ne x t Cycle
L L X X X X X Continue Clock Suspe nsion
Notes:
6. Power - dow n and sel f refresh c an be enter ed only w hen all the bank s ar e i n an i dl e state.
