January 2007
HYB25DC256163CE-4
HYB25DC256163CE-5
HYB25DC256163CE-6
256-Mbit Double-Data-Rate SGRAM
Green Product
Internet Data Sheet
Rev. 1.1
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 2
03292006-SR4U-HULB
HYB25DC256163CE-4, HYB25DC256163CE-5, HYB25DC256163CE-6
Revision History: 2007-01, Rev. 1.1
Page Subjects (major changes since last revision)
All Adapted internet edition
All Added new speedsort -4
Previous Revision: 2007-01, Rev. 1.0
Internet Data Sheet
Rev. 1.1, 2007-01 3
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
1Overview
This chapter lists all main features of the product family HYB25DC256163CE and the ordering information.
1.1 Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
•7.8µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400, DDR500)
VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400, DDR500)
PG-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code –4 –5 –6 Unit
Speed Grade DDR500 DDR400B DDR333
Max. Clock Frequency @CL3 fCK3 250 200 166 MHz
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
1.1.1 Description
The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the 256-Mbit Double-Data-Rate SGRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR SGRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for Writes.
The 256-Mbit Double-Data-Rate SGRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and
CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every
positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as
well as to both edges of CK.Read and write accesses to the DDR SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the
Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or
Write command are used to select the bank and the starting column location for the burst access.
The DDR SGRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs,
the pipelined, multibank architecture of DDR SGRAMs allows for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
TABLE 2
Ordering Information for Lead free Products
Product Type Organisation Clock (MHz) Package Note
HYB25DC256163CE-4 ×16 250 PG-TSOPII-66-2 1)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
HYB25DC256163CE-5 200
HYB25DC256163CE-6 166
Internet Data Sheet
Rev. 1.1, 2007-01 5
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
2 Chip Configuration
The chip configuration of a DDR SGRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column
are explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1.
TABLE 3
Chip Configuration
Ball# Name Pin
Type
Buffer
Type
Function
Clock Signals
45 CK I SSTL Clock Signal
46 CK I SSTL Complementary Clock Signal
44 CKE I SSTL Clock Enable
Control Signals
23 RAS I SSTL Row Address Strobe
22 CAS I SSTL Column Address Strobe
21 WE I SSTL Write Enable
24 CS I SSTL Chip Select
Address Signals
26 BA0 I SSTL Bank Address Bus 2:0
27 BA1 I SSTL
29 A0 I SSTL Address Bus 11:0
30 A1 I SSTL
31 A2 I SSTL
32 A3 I SSTL
35 A4 I SSTL
36 A5 I SSTL
37 A6 I SSTL
38 A7 I SSTL
39 A8 I SSTL
40 A9 I SSTL
28 A10 I SSTL
AP I SSTL
41 A11 I SSTL
42 A12 I SSTL Address Signal 12
Note: Module based on 256 Mbit or larger dies
NC NC Note: Module based on 128 Mbit or smaller dies
17 A13 I SSTL Address Signal 13
Note: 1 Gbit based module
NC NC Note: Module based on 512 Mbit or smaller dies
Internet Data Sheet
Rev. 1.1, 2007-01 6
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Data Signals ×16 Organization
2DQ0 I/O SSTL Data Signal 15:0
4DQ1 I/O SSTL
5DQ2 I/O SSTL
7DQ3 I/O SSTL
8DQ4 I/O SSTL
10 DQ5 I/O SSTL
11 DQ6 I/O SSTL
13 DQ7 I/O SSTL
54 DQ8 I/O SSTL
56 DQ9 I/O SSTL
57 DQ10 I/O SSTL
59 DQ11 I/O SSTL
60 DQ12 I/O SSTL
62 DQ13 I/O SSTL
63 DQ14 I/O SSTL
65 DQ15 I/O SSTL
Data Strobe ×16 Organization
51 UDQS I/O SSTL Data Strobe Upper Byte
16 LDQS I/O SSTL Data Strobe Lower Byte
Data Mask ×16 Organization
47 UDM I SSTL Data Mask Upper Byte
20 LDM I SSTL Data Mask Lower Byte
Power Supplies
49 VREF AI I/O Reference Voltage
3, 9, 15, 55, 61 VDDQ PWR I/O Driver Power Supply
1, 18, 33 VDD PWR Power Supply
6, 12, 52, 58, 64 VSSQ PWR Power Supply
34 VSS PWR Power Supply
Not Connected ×16 Organization
14, 17, 19, 25,
42, 43, 50, 53
NC NC Not Connected
Ball# Name Pin
Type
Buffer
Type
Function
Internet Data Sheet
Rev. 1.1, 2007-01 7
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 4
Abbreviations for Pin Type
TABLE 5
Abbreviations for Buffer Type
Abbreviation Description
IStandard input-only pin. Digital levels
OOutput. Digital levels
I/O I/O is a bidirectional input/output signal
AI Input. Analog levels
PWR Power
GND Ground
NC Not Connected
Abbreviation Description
SSTL Serial Stub Terminalted Logic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS CMOS Levels
OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
Internet Data Sheet
Rev. 1.1, 2007-01 8
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
FIGURE 1
Chip Configuration PG-TSOPII-66
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Internet Data Sheet
Rev. 1.1, 2007-01 9
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
3 Functional Description
Field Bits Type1)
1) W = write only register bit
Description
BL [2:0] W Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001 2
010 4
010 8
BT 3Burst Type
See Table 6 for internal address sequence of low order address bits.
0 Sequential
1 Sequential
CL [6:4] CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
011 3
MODE [12:7] Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
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Internet Data Sheet
Rev. 1.1, 2007-01 10
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 6
Burst Definition
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data-element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Length Starting Column Address Order of Accesses Within a Burst
A2 A1 A0 Type = Sequential Type = Interleaved
200-10-1
11-0 1-0
4 0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Internet Data Sheet
Rev. 1.1, 2007-01 11
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 7
Truth Table 1a: Commands
Field Bits Type1)
1) W = write only register bit
Description
DLL 0WDLL Status
0B Enabled
1B Disabled
DS 1Drive Strength
0B Normal
1B Weak
MODE [12:2] Operating Mode
Note: All other bit combinations are RESERVED.
00000000000B Normal Operation
Name (Function) CS RAS CAS WE Address MNE Note
Deselect (NOP) H X X X X NOP 1)2)
1) CKE is HIGH for all commands shown except Self Refresh. VREF must be maintained during Self Refresh operation
2) Deselect and NOP are functionally interchangeable.
No Operation (NOP) L H H H X NOP 1)2)
Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1)3)
3) BA0-BA1 provide bank address and A0-A12 provide row address.
Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1)4)
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16);A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1)4)
Burst Terminate L H H L X BST 1)5)
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1)6)
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR/SR 1)7)8)
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
Mode Register Set L L L L Op-Code MRS 1)9)
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
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Internet Data Sheet
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03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 8
Truth Table 1b: DM Operation
TABLE 9
Truth Table 2: Clock Enable (CKE)
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SGRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Name (Function) DM DQs Note
Write Enable LValid
1)
1) Used to mask write data; provided coincident with the corresponding data.
Write Inhibit HX
Current State CKE n-1 CKEn Command n Action n Note
Previous Cycle Current Cycle
Self Refresh L L X Maintain Self-Refresh 1)
1) VREF must be maintained during Self Refresh operation
Self Refresh L H Deselect or NOP Exit Self-Refresh 2)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Power Down L L X Maintain Power-Down
Power Down L H Deselect or NOP Exit Power-Down
All Banks Idle H L Deselect or NOP Precharge Power-Down Entry
All Banks Idle H L AUTO REFRESH Self Refresh Entry
Bank(s) Active H L Deselect or NOP Active Power-Down Entry
HHSee Table 10 ––
Internet Data Sheet
Rev. 1.1, 2007-01 13
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 10
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State CS RAS CAS WE Command Action Note
Any H X X X Deselect NOP. Continue previous operation. 1)2)3)4)5)6)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9 and after tXSNR/tXSRD has been met (if the previous state was
self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active”
state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued
on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according
to Table 11.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SGRAM is in the
“all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met,
the DDR SGRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
L H H H No Operation NOP. Continue previous operation. 1) to 6)
Idle L L H H Active Select and activate row 1) to 6)
L L L H AUTO REFRESH 1) to7)
7) Not bank-specific; requires that all banks are idle.
LLLLMODE REGISTER
SET
1) to 7)
Row Active L H L H Read Select column and start Read burst 1) to 6),8)
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
L H L L Write Select column and start Write burst 1) to 6),8)
L L H L Precharge Deactivate row in bank(s) 1) to 6),9)
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
Read (Auto
Precharge
Disabled)
L H L H Read Select column and start new Read burst 1) to 6),8)
L L H L Precharge Truncate Read burst, start Precharge 1) to 6),9)
L H H L BURST
TERMINATE
BURST TERMINATE 1) to 6),10)
Write (Auto
Precharge
Disabled)
L H L H Read Select column and start Read burst 1) to 6), 8),11)
L H L L Write Select column and start Write burst 1) to 6),8)
L L H L Precharge Truncate Write burst, start Precharge 1) to 6),9),11)
Internet Data Sheet
Rev. 1.1, 2007-01 14
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 11
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
Current State CS RAS CAS WE Command Action Note
Any HXXXDeselect NOP. Continue previous operation. 1)2)3)4)5)6)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if
the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See 10).
Write with Auto Precharge Enabled: See 10).
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
L HHHNo Operation NOP. Continue previous operation. 1) to 6)
Idle XXXXAny Command
Otherwise Allowed to
Bank m
1) to 6)
Row Activating,
Active, or
Precharging
L L H H Active Select and activate row 1) to 6)
L H L H Read Select column and start Read burst 1) to7)
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
L H L L Write Select column and start Write burst 1) to 7)
LLHLPrecharge 1) to 6)
Read (Auto
Precharge
Disabled)
L L H H Active Select and activate row 1) to 6)
L H L H Read Select column and start new Read burst 1) to 7)
LLHLPrecharge 1) to 6)
Write (Auto
Precharge
Disabled)
L L H H Active Select and activate row 1) to 6)
L H L H Read Select column and start Read burst 1) to 8)
L H L L Write Select column and start new Write burst 1) to 7)
LLHLPrecharge 1) to 6)
Read (With Auto
Precharge)
L L H H Active Select and activate row 1) to 6)
L H L H Read Select column and start new Read burst 1) to 7),9)
L H L L Write Select column and start Write burst 1) to 7),9),10)
LLHLPrecharge 1) to 6)
Write (With Auto
Precharge)
L L H H Active Select and activate row 1) to 6)
L H L H Read Select column and start Read burst 1) to 7),9)
L H L L Write Select column and start new Write burst 1) to 7),9)
LLHLPrecharge 1) to 6)
Internet Data Sheet
Rev. 1.1, 2007-01 15
03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 12
Truth Table 5: Concurrent Auto Precharge
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 12.
10) A Write command may be applied after the completion of data output.
From Command To Command (different bank) Minimum Delay with Concurrent Auto
Precharge Support
Unit
WRITE w/AP Read or Read w/AP 1 + (BL/2) + tWTR tCK
Write to Write w/AP BL/2 tCK
Precharge or Activate 1 tCK
Read w/AP Read or Read w/AP BL/2 tCK
Write or Write w/AP CL (rounded up) + BL/2 tCK
Precharge or Activate 1 tCK
Internet Data Sheet
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03292006-SR4U-HULB
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4 Electrical Characteristics
4.1 Operating Conditions
TABLE 13
Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
TABLE 14
Input and Output Capacitances
Parameter Symbol Values Unit Note/ Test
Condition
Min. Typ. Max.
Voltage on I/O pins relative to VSS VIN, VOUT –0.5 VDDQ + 0.5 V
Voltage on inputs relative to VSS VIN –1 +3.6 V
Voltage on VDD supply relative to VSS VDD –1 +3.6 V
Voltage on VDDQ supply relative to VSS VDDQ –1 +3.6 V
Operating temperature (ambient) TA0—+70 °C—
Storage temperature (plastic) TSTG –55 +150 °C—
Power dissipation (per SDRAM component) PD—1 W
Short circuit output current IOUT —50 mA
Parameter Symbol Values Unit Note/ Test Condition
Min. Typ. Max.
Input Capacitance: CK, CK CI1 2.0 3.0 pF 1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
Delta Input Capacitance CdI1 0.25 pF 1)
Input Capacitance: All other input-only pins CI2 2.0 3.0 pF 1)
Delta Input Capacitance: All other input-only pins CdIO —— 0.5pF
1)
Input/Output Capacitance: DQ, DQS, DM CIO 4.0 5.0 pF 1)2)
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Delta Input/Output Capacitance: DQ, DQS, DM CdIO —— 0.5pF
1)
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 15
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note1)/Test Condition
1) 0 °C TA 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V.
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK 166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK > 166 MHz 2)
2) DDR400 conditions apply for all clock frequencies above 166 MHz.
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK 166 MHz 3)
3) Under all conditions, VDDQ must be less than or equal to VDD.
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz
2)3)
Supply Voltage, I/O Supply
Voltage
VSS, VSSQ 00V
Input Reference Voltage VREF 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V4)
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ.
I/O Termination Voltage
(System)
VTT VREF – 0.04 VREF + 0.04 V 5)
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 6)
6) Inputs are not recognized as valid until VREF stabilizes.
Input Low (Logic0) Voltage VIL(DC) 0.3 VREF – 0.15 V 6)
Input Voltage Level, CK and
CK Inputs
VIN(DC) 0.3 VDDQ + 0.3 V 6)
Input Differential Voltage,
CK and CK Inputs
VID(DC) 0.36 VDDQ + 0.6 V 6)7)
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.
VI-Matching Pull-up Current
to Pull-down Current
VIRatio 0.71 1.4 8)
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Input Leakage Current II–2 2 µA Any input 0 V VIN VDD; All
other pins not under test = 0 V9)
9) Values are shown per pin.
Output Leakage Current IOZ –5 5 µA DQs are disabled; 0 V VOUT
VDDQ 9)
Output High Current, Normal
Strength Driver
IOH –16.2 mA VOUT = 1.95 V
Output Low Current, Normal
Strength Driver
IOL 16.2 mA VOUT = 0.35 V
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4.2 AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 2 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SGRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest Industry specification
for DDR components.
FIGURE 2
AC Output Load Circuit Diagram / Timing Reference Load
50
Timing Reference Point
Output
(VOUT)
30 pF
VTT
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HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 16
AC Operating Conditions
TABLE 17
AC Timing - Absolute Specifications
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
Input High (Logic 1) Voltage, DQ, DQS and DM Signals VIH(AC) VREF + 0.31 V 1)2)3)
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V (DDR400); 0 °C TA 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals VIL(AC) VREF – 0.31 V 1)2)3)
Input Differential Voltage, CK and CK Inputs VID(AC) 0.7 VDDQ + 0.6 V 1)2)3)4)
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
Input Closing Point Voltage, CK and CK Inputs VIX(AC) 0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2 V 1)2)3)5)
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
Parameter Symbol –4 –5 –6 Unit Note1)/ Test
Condition
DDR500 DDR400B DDR333
Min. Max. Min. Max. Min. Max.
DQ output access
time from CK/CK
tAC –0.6 +0.6 –0.65 +0.65 –0.7 +0.7 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
Clock cycle time tCK 4 12 5 12 6 12 ns CL = 3.0
2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
Auto precharge
write recovery +
precharge time
tDAL 28 35 (tWR/tCK)+(tRP/tCK)tCK
2)3)4)5)6)
DQ and DM input
hold time
tDH 0.4 0.4 0.45 ns 2)3)4)5)
DQ and DM input
pulse width (each
input)
tDIPW 1.75 1.75 1.75 ns 2)3)4)5)6)
DQS output access
time from CK/CK
tDQSCK –0.65 +0.65 –0.65 +0.65 –0.6 +0.6 ns 2)3)4)5)
DQS input low
(high) pulse width
(write cycle)
tDQSL,H 0.35 0.35 0.35 tCK
2)3)4)5)
DQS-DQ skew
(DQS and
associated DQ
signals)
tDQSQ 0.5 0.5 0.45 ns TSOPII
2)3)4)5)