ACPL-570XL, ACPL-573XL, ACPL-177XL, 5962-08227
Hermetically Sealed 3.3V, Low IF, Wide VCC, High Gain Optocouplers
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
These devices are single, dual, and quad channel, hermeti-
cally sealed optocouplers. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from DSCC Drawing 5962-08227. All devices are manufac-
tured and tested on a MIL-PRF-38534 certied line and are
included in the DSCC Qualied Products Database Sup-
plemental Information Sheets QPDSIS-38534 as Hybrid
Microcircuits.
Each channel contains a GaAsP light emitting diode which
is optically coupled to an integrated high gain photon
detector. The high gain output stage features an open
collector output providing both lower saturation voltage
and higher signaling speed than possible with conven-
tional photo-Darlington optocouplers.
The supply voltage can be operated as low as 3.0 V without
adversely aecting the parametric performance.
These devices have a 300% minimum CTR at an input
current of only 0.5 mA making them ideal for use in low
input current applications such as MOS, CMOS, low power
logic interfaces or line receivers.
The connection of a 0.1
µ
F bypass capacitor between VCC and GND is recommended.
Features
• Low power consumption
• 3.3V Supply voltages
• Dual marked with device part number and DSCC
drawing number
• Manufactured and tested on a MIL-PRF-38534 Certied
Line
• QPDSIS-38534, Class H and K
• Three hermetically sealed package congurations
• Performance guaranteed over full military temperature
range: -55°C to +125°C
• Low input current requirement: 0.5 mA
• High current transfer ratio: 1500% typical @ IF = 0.5 mA
• Low output saturation voltage: 0.11 V typical
• 1500 Vdc withstand test voltage
• HCPL-4701/31, -070A/31 function compatibility
Applications
• Military and aerospace
• High reliability systems
• Telephone ring detection
• Microprocessor system interface
• Transportation, medical, and life critical systems
• Isolated input line receiver
• EIA RS-232-C line receiver
• Voltage level shifting
• Isolated input line receiver
• Isolated output line driver
• Logic ground isolation
• Harsh industrial environments
• Current loop receiver
• System test equipment isolation
• Process control input/output isolation
2
Functional Diagram
Multiple Channel Devices Available
Package styles for these parts are 8 and 16 pin DIP through
hole (case outlines P and E respectively). Devices may be
purchased with a variety of lead bend and plating options.
See Selection Guide table for details. Standard Military
Drawing (SMD) parts are available for each package and
lead style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specications, and perfor-
mance characteristics shown in the gures are similar for
all parts except as noted. Additionally, the same package
assembly processes and materials are used in all devices.
These similarities justify the use of a common data base for
die related reliability.
Truth Table
(Positive Logic)
Input Output
On (H) L
O (L) H
7
5
6
8
2
3
4
1
Selection Guide – Package Styles and Lead Conguration Options
Package 16 Pin DIP 8 Pin DIP 8 Pin DIP
Lead Style Through Hole Through Hole Through Hole
Channels 4 1 2
Common Channel Wiring VCC, GND None VCC, GND
Avago Part # & Options
Commercial ACPL-1770L ACPL-5700L ACPL-5730L
MIL-PRF-38534, Class H ACPL-1772L ACPL-5701L ACPL-5731L
MIL-PRF-38534, Class K ACPL-177KL ACPL-570KL ACPL-573KL
Standard Lead Finish Gold Plate Gold Plate Gold Plate
Solder Dipped* Option -200 Option -200 Option -200
Butt Cut/Gold Plate Option -100 Option -100 Option -100
Gull Wing/Soldered* Option -300 Option -300 Option -300
Class H SMD Part #
Prescript for all below 5962- 5962- 5962-
Either Gold or Solder 0822703HEX 0822701HPX 0822702HPX
Gold Plate 0822703HEC 0822701HPC 0822702HPC
Solder Dipped* 0822703HEA 0822701HPA 0822702HPA
Butt Cut/Gold Plate 0822703HUC 0822701HYC 0822702HYC
Butt Cut/Soldered* 0822703HUA 0822701HYA 0822702HYA
Gull Wing/Soldered* 0822703HTA 0822701HXA 0822702HXA
Class K SMD Part #
Prescript for all below 5962- 5962- 5962-
Either Gold or Solder 0822703KEX 0822701KPX 0822702KPX
Gold Plate 0822703KEC 0822701KPC 0822702KPC
Solder Dipped* 0822703KEA 0822701KPA 0822702KPA
Butt Cut/Gold Plate 0822703KUC 0822701KYC 0822702KYC
Butt Cut/Soldered* 0822703KUA 0822701KYA 0822702KYA
Gull Wing/Soldered* 0822703KTA 0822701KXA 0822702KXA
* Solder contains lead.
3
Outline Drawings
16 Pin DIP Through Hole, 4 Channels
Device Marking
Functional Diagrams
16 pin DIP 8 pin DIP 8 pin DIP
Through Hole Through Hole Through Hole
4 Channels 1 Channel 2 Channels
16
11
10
9
7
5
6
8
2
1
3
4
12
14
15
13
7
5
6
8
2
3
4
1
7
5
6
8
2
3
4
1
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
Avago LOGO
Avago P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
*QUALIFIED PARTS ONLY
s
8 Pin DIP Through Hole, 1 and 2 Channel
Note: Dimensions in Millimeters (Inches).
3.81 (0.150)
MIN.
4.32 (0.170)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
4.45 (0.175)
MAX.
20.06 (0.790)
20.83 (0.820)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.89 (0.035)
1.65 (0.065)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
3.81 (0.150)
MIN.
4
Hermetic Optocoupler Options
Option Description
100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on com-
mercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
200 Lead nish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and
16 pin DIP. DSCC Drawing part numbers contain provisions for lead nish.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on
commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped
leads.
Solder contains lead.
Note: Dimensions in Millimeters (Inches).
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
Note: Dimensions in Millimeters (Inches).
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
5° MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
5
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Notes
Storage Temperature TS -65 +150 °C
Operating Temperature TA -55 +125 °C
Case Temperature TC +170 °C
Junction Temperature TJ +175 °C
Lead Solder Temperature 260 for 10 sec °C
Output Current (each channel) IO 40 mA
Output Voltage (each channel) VO -0.5 20 V 1
Supply Voltage VCC -0.5 20 V 1
Output Power Dissipation (each channel) 50 mW 2
Peak Input Current (each channel, <1 ms duration) 20 mA
Average Input Current (each channel) IF 10 mA 3
Reverse Input Voltage (each channel) VR 5 V
Package Power Dissipation (each channel) PD 200 mW
ESD Classication
(MIL-STD-883, Method 3015)
ACPL-5700L/01L/0KL ( ), Class 2
ACPL-5730L/31L/3KL ( A), Class 3A
ACPL-1770L/2L/KL ( B), Class 3B
8 Pin Ceramic DIP Single Channel Schematic
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Current, Low Level (Each Channel) IF(OFF) 2.0 µA
Input Current, High Level (Each Channel) IF(ON) 0.5 5 mA
Supply Voltage VCC 3.0 7.0 V
Output Voltage VO 3.0 7.0 V
ANODE
3
CATHODE 6
5
V
CC
V
O
I
CC
GND
I
O
I
F
2
+
–
V
F
8
6
Electrical Characteristics, TA = -55°C to +125°C, unless otherwise specied
Parameter Symbol Test Conditions
Group A[13]
Subgroup
Limits
Units Fig. Note Min. Typ.* Max.
Current Transfer
Ratio
CTR IF = 0.5 mA, VO = 0.4 V,
VCC = 3.0 V
1, 2, 3 300 1500 % 3 4, 5
IF = 1.6 mA, VO = 0.4 V,
VCC = 3.0 V
300 1300
IF =5 mA, VO = 0.4 V,
VCC = 3.0 V
200 800
Logic Low Output
Voltage
VOL IF = 0.5 mA, IOL = 1.5 mA,
VCC = 3.0 V
1, 2, 3 0.05 0.4 V 2 4
IF = 1.6 mA, IOL = 4.8 mA,
VCC = 3.0 V
0.06 0.4 4
IF =5 mA, IOL = 10 mA,
VCC = 3.0 V
0.09 0.4 4
Logic High Output
Current
IOH IF =2 µA, VO = 7 V,
VCC = 7 V
1, 2, 3 1.0 100 µA 4
IOHX 100 µA4, 6
Logic
Low
Supply
Current
ICCL IF =1.6 mA, VCC = 7 V
IF1 =IF2 = 1.6 mA,
VCC = 7 V
1, 2, 3
0.8
0.8
2
4
mA
4
IF1 = IF2 =IF3 =IF4 =1.6 mA,
VCC = 7 V
1.3 4
Logic
High
Supply
Current
ICCH IF =0 mA, VCC = 7 V
IF1 =IF2 = 0 mA,
VCC = 7 V
1, 2, 3 0.01 20
40
µA
IF1 = IF2 =IF3 =IF4 =0 mA,
VCC = 7 V
40
Input
Forward
Voltage
VF IF = 1.6 mA 1, 2, 3 1.0 1.4 1.8 V
1 4
Input Reverse
Breakdown
Voltage
BVR IR = 10 µA 1, 2, 3 5 V 4
Input-Output
Insulation Leakage
Current
II-O ≤65% Relative Humidity
TA =25°C, t = 5 s,
VI-O = 1500 VDC
1 1.0 µA 7, 12
Capacitance
Between
Input-Output
CI-O f = 1 MHz, TA =25°C 4 4 pF 4, 8, 14
* All typical values are at VCC = 3.3 V, TA = 25°C.
Single
Channel
Dual
Channel
Quad
Channel
Single
Channel
Dual
Channel
Quad
Channel
7
Typical Characteristics, TA = 25°C
Parameter Sym. Typ. Units Test Conditions Note
Input Capacitance CIN 60 pF VF =0 V, f = 1 MHz 4
Input Diode Temperature
Coecient
ΔVF/ΔTA -1.8 mV/°C IF = 1.6 mA 4
Resistance (Input-Output) RI-O 1012 Ω VI-O = 500 V 4, 8
Capacitance (Input-Output) CI-O 2.0 pF f = 1 MHz 4, 8
Dual and Quad Channel Product Only
Input-Input Leakage Current II-I 0.5 nA Relative Humidity = ≤65%,
VI-I = 500 V, t = 5 s
9
Resistance (Input-Input) RI-I 1012 Ω VI-I = 500 V 9
Capacitance (Input-Input) CI-I 1.0 pF f = 1 MHz 9
Electrical Characteristics (cont), TA = -55°C to +125°C, unless otherwise specied
Parameter Symbol Test Conditions
Group A[13]
Subgroup
Limits
Units Fig. Note Min. Typ.* Max.
Propagation Delay
Time to Logic Low
at Output
tPHL IF = 0.5 mA, RL = 2.2 kΩ,
VCC = 3.3 V
9, 10, 11 40 100 µs 5, 6,
7, 8
4
tPHL IF = 1.6 mA, RL = 680 Ω,
VCC = 3.3 V
9, 10, 11 9 30 4
tPHL IF =5 mA, RL = 330 Ω,
VCC = 3.3 V
9 2 5 4
10, 11 10
Propagation Delay
Time to Logic High
at Output
tPLH IF = 0.5 mA, RL = 2.2 kΩ,
VCC = 3.3 V
9, 10, 11 10 60 µs 5, 6,
7, 8
4
tPLH IF = 1.6 mA, RL = 680 Ω,
VCC = 3.3 V
9, 10, 11 8 50 4
tPLH IF =5 mA, RL = 330 Ω,
VCC = 3.3 V
9 6 20 4
10, 11 30
Common Mode
Transient
Immunity at Low
Output Level
|CML| VCC = 3.3 V, IF = 1.6 mA
RL = 680 kΩ
|VCM|= 50 VP-P
9, 10, 11 500 1000 V/µs9 4, 10
11, 14
Common Mode
Transient
Immunity at High
Output Level
|CMH| VCC = 3.3 V , IF =0 mA
RL = 680 kΩ
|VCM|= 50 VP-P
9, 10, 11 500 1000 V/µs 9 4, 10
11, 14
* All typical values are at VCC = 3.3 V, TA = 25°C.
8
Notes:
1. GND Pin should be the most negative voltage at the detector side.
Keeping VCC as low as possible, but greater than 2.0 V, will provide
lowest total IOH over temperature.
2. Output power is collector output power plus total supply power for
the single channel device. For the dual channel device, output power
is collector output power plus one half the total supply power. For
the quad channel device, output power is collector output power
plus one fourth of total supply power. Derate at 1.66 mW/°C above
110°C.
3. Derate IF at 0.33 mA/°C above 110°C.
4. Each channel.
5. CURRENT TRANSFER RATIO is dened as the ratio of output collector
current, IO, to the forward LED input current, IF, times 100%.
6. IOHX is the leakage current resulting from channel to channel optical
crosstalk. IF = 2 µA for channel under test. For all other channels,
IF = 10 mA.
7. All devices are considered two-terminal devices; measured between
all input leads or terminals shorted together and all output leads or
terminals shorted together.
8. Measured between each input pair shorted together and all output
connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each
multi-channel device.
10. CML is the maximum rate of rise of the common mode voltage that
can be sustained with the output voltage in the logic low state
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode
voltage that can be sustained with the output voltage in the logic
high state (VO > 2.0 V).
11. In applications where dV/dt may exceed 50,000 V/µs (such as
a static discharge) a series resistor, RCC, should be included to
protect the detector ICs from destructively high surge currents. The
recommended value is:
1 (V)
RCC = ————— kΩ
0.15 IF (mA)
for single channel;
1 (V)
RCC = ————— kΩ
0.3 IF (mA)
for dual channel;
1 (V)
RCC = ————— kΩ
0.6 IF (mA)
for quad channel.
12. This is a momentary withstand test, not an operating condition.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and
9). SMD and 883B parts receive 100% testing at 25,125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters tested as part of device initial characterization and
after design and process changes. Parameters guaranteed to limits
specied for all lots not specically tested.
9
Figure 2. Normalized DC Transfer Characteristics.
Figure 3. Normalized Current Transfer Ratio vs. Input Diode Forward Current.
Figure 1. Input Diode Forward Current vs. Forward Voltage.
Figure 4. Normalized Supply Current vs. Input Diode Forward Current.
Figure 5. Propagation Delay to Logic Low vs. Input Pulse Period.
10
Figure 8. Switching Test Circuit. Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.
IF
RL
RCC*56 Ω
1.0 µF
+3 V
VO
* SEE NOTE 11
Rm
IF MONITOR
PULSE GEN.
ZO = 50 Ω
tr, tf = 5.0 ns
f = 100 Hz
tPULSE = 0.5ms
CL**
** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
7
5
6
8
2
3
4
1
VFF
IF
VCM
RL
RCC* 56 Ω
1.0 µF
+3 V
VO
+ –
PULSE GEN.
* SEE NOTE 11
A
B
7
5
6
8
2
3
4
1
Figure 6. Propagation Delay vs. Temperature. Figure 7. Propagation Delay vs. Input Diode Forward Current.
0
10
20
30
40
50
60
-80 -60 -40 -20 0 20 40 60 80 100 120 140 160
TA - TEMPERATURE°C
tp - PROPAGATION DELAY µs
IF = 0.5mA, RL = 2.2kohm
IF = 1.6mA, RL = 680ohm
IF = 5.0mA, RL=330ohm
0
5
10
15
20
25
30
35
40
45
0 2 4 6 8 10 12
IF - INPUT DIODE FORWARD CURRENT mA
tp - PROPAGATION DELAY µs
tPHL, RL = 330ohm TO 2.2Kohm
tPLH, RL = 2.2Kohm
tPLH, RL = 680ohm
tPLH, RL = 330ohm
VCC = 3.2V
TA = 25°C
PULSE WIDTH = 50 µs
PERIOD = 10ms
TPHL
TPLH
TPLH
TPLH
TPHL
TPHL
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1819EN - March 25, 2009
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Avago’s Hi-Rel Optocouplers are in compliance with MIL-
PRF-38534 Class H and K. Class H and Class K devices are
also in compliance with DSCC drawing 5962-08227.
Testing consists of 100% screening and quality confor-
mance inspection to MIL-PRF-38534.
Figure 11. Operating Circuit for Burn-In and Steady State Life Tests.
* ALL CHANNELS TESTED SIMULTANEOUSLY.
V
OC
CONDITIONS: I
F
= 5 mA
I
O
= 10 mA
T
A
= +125°C
V
CC
+ 18 V
V
IN
+ –
(EACH OUTPUT)
(EACH INPUT)
0.01 µF
2
3
4
1
7
5
6
8
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.
ILEAK
R2MAY BE OMITTED
IF ADDITIONAL FANOUT
IS NOT USED.
R
1
R
2
VCC
R
2
≥2.4  VF
IF
7
5
6
8
2
3
4
1
R
1
≤VCC  VF  IF
R
2
IF + ILEAK