Description
The A1174 is a micro-power, Hall-effect latch for use in portable
devices that employ rotational detection systems, and have a
power supply voltage between 1.65 and 3.5 V. The device has
a single push-pull output structure and requires no external
pull-up resistor for reliable operation.
When a sufficient positive magnetic field is present on the
device, the device output transitions to the low state and is
latched in this state until a negative field of sufficient strength
latches the device output into the high state. The latched output
is ideal when using multiple sensors in rotational speed and
direction sensing systems (for example, track ball and scroll
bar systems in portable devices).
The device includes an innovative clocking scheme that
satisfies the micro-power needs of almost any application,
including track balls for PDAs and cell phones. Using the
EXTERNAL_CLK and DUAL_CLK pins as described in this
datasheet, the device can be set into various working modes.
In Dual Clock mode, the device switches between predefined
slow and fast sampling rates. The average current consumption
of the device is extremely low when rotation is not detected.
In External Clock mode, the user sets the clock rate for the
device to achieve the required on and off times for controlling
average power. This user-determined clocking also helps to
A1174-DS, Rev. 7
Features and Benefits
▪ Micro-power latch operation
▪ 1.65 to 3.5 V battery operation
▪ Push-pull output eliminates the need for an external pull-
up resistor
▪ User configured, internally or externally controlled sample
and sleep periods
▫ Floating the two clock pins results in the use of a fixed
sampling clock internal to the device
▫ Toggling the clock pins allows the user to control the
sampling and sleep times of the device for extreme low
power operation
▪ External control of the clock pins allows the user to
implement synchronous sampling of multiple sensors in
direction detection systems
▪ Chopper stabilization
▫ Superior temperature stability
▫ Extremely low switchpoint drift
▫ Insensitive to physical stress
▪ Solid state reliability
▪ Small size
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
Continued on the next page…
Package: 6-contact MLP/DFN (suffix EW)
Not to scale
A1174
1.5 mm × 2 mm × 0.40 mm
0
Magnetic Flux
Density
A1174 Output
On OffOffOn On
+B
BOP BOP BOP
BRP
BRP
BRP
+V
–B
Figure 1. Timing diagram for output switching
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Description (continued)
VDD
NC
VOUT
DUAL_CLK
GND
EXTERNAL_CLK
PAD
6
5
4
1
2
3
Pin-out Diagram
Terminal List
Number Name Function
1 VDD Supply Voltage
2 NC No connect
3 VOUT Output
4 EXTERNAL_CLK In combination with DUAL_CLK , allows external control of the device
sampling period and duty cycle
5 GND Ground
6 DUAL_CLK In combination with EXTERNAL_CLK , drives the part in Dual Clock mode
Selection Guide
Part Number Package Packing1
A1174EEWLT-P2DFN/MLP 1.5×2 mm; 0.40 mm maximum height 3000 pieces per 7-inch reel
1Contact Allegro® for additional packing options.
2Allegro products sold in DFN package types are not intended for automotive applications.
achieve synchronous clocking of multiple devices. This allows a
defined phase relationship between the output transitions of each
device in direction detection systems.
Improved stability is made possible through dynamic offset
cancellation using chopper stabilization, which reduces the residual
offset voltage normally caused by device overmolding, temperature
dependencies, and thermal stress. Solid state reliability is provided
by integrating, on a single silicon chip, a Hall-voltage generator,
a small-signal amplifier, chopper stabilization, a latch, and a
MOSFET output.
The device package is a 6-contact, 1.5 mm × 2 mm, 0.40 mm nominal
overall height MLP/DFN, with exposed pad for enhanced thermal
dissipation. It is lead (Pb) free, with NiPdAu leadframe plating.
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Forward Supply Voltage VDD 5.0 V
Reverse Supply Voltage VRDD –0.3 V
Output Voltage VOUT 5.0 V
Reverse Output Voltage VROUT –0.3 V
EXTERNAL_CLK and DUAL_CLK
Pins Input Voltage VIN 5.0 V
EXTERNAL_CLK and DUAL_CLK
Pins Reverse Input Voltage VRIN –0.3 V
Continuous Output Current IOUT(sink) –1 mA
IOUT(source) 1mA
Magnetic Flux Density* B Unlimited G
Operating Ambient Temperature TARange E –40 to 85 °C
Maximum Junction Temperature TJ(MAX) 165 °C
Storage Temperature Tstg –65 to 170 °C
*1G = 0.1 mT (millitesla)
(Top View)
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
VDD
GND
Amp
VOUT
Input
Decoder
Sample Control
Block
Internal
Clock
Latch
EXTERNAL_CLK
DUAL_CLK
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified)
Characteristic Symbol Test Conditions Min. Typ.1 Max. Unit
Electrical Characteristics
Supply Voltage2VDD
TA = 25°C 1.65 – 3.5 V
–40°C ≥ TA ≥ 85°C 1.8 – 3.5 V
Output On Voltage VOUT(SAT) NMOS on, IOUT = 1 mA – 100 300 mV
VOUT(HIGH) PMOS on, IOUT = 1 mA VDD
– 300 VDD
– 100 – mV
Supply Current
IDD(EN) Chip in awake state (enabled) – – 2.0 mA
IDD(DIS) Chip in sleep state (disabled) – – 8.0 μA
IDD(AV) Normal Clock mode, VDD = 2.5 V – – 71 μA
Normal Clock mode, VDD = 3.0 V – – 82 μA
Internal Chopper Stabilization Clock Frequency fC– 200 – kHz
EXTERNAL_CLK and DUAL_CLK Pins Input Current IIN VEXTERNAL
_
CLK
= VDD, VDUAL
_
CLK = VDD – 0.5 – μA
EXTERNAL_CLK and DUAL_CLK Pins Leakage Current IOFF VEXTERNAL
_
CLK
= 0 V, VDUAL
_
CLK = 0 V – 0.02 – μA
Supply Slew Rate3SR tOFF = 100 ms 0.1 – – V/ms
Normal Clock Mode Characteristics4
Normal Mode Awake Duration tawake_norm –2546μs
Normal Mode Period tperiod_norm – 0.7 1.05 ms
External Clock Mode Characteristics4
EXTERNAL_CLK and DUAL_CLK Pins Threshold Vth(HIGH) – – 0.75 × VDD V
Vth(LOW) 0.25 × VDD ––V
External Clock Mode Awake Duration tawake_ext VEXTERNAL_CLK > Vth(HIGH) 46 – – μs
External Clock Mode Period tperiod_ext VEXTERNAL_CLK > Vth(HIGH) 80 – – μs
State Transition Delay5tdelay_ext –2546μs
Dual Clock Mode Characteristics4
Dual Clock Mode Awake Duration tawake_dual –2546μs
Dual Clock Mode Fast Sampling Period tperiod_fast –8 ×
tawake_dual –μs
Dual Clock Mode Slow Sampling Period tperiod_slow –28–ms
Dual Clock Mode Timeout6ttimeout –100 ×
tperiod_slow –ms
Magnetic Characteristics2
Operate Point BOP South pole to device branded side 5 36 55 G
Release Point BRP North pole to device branded side –55 –36 –5 G
Hysteresis BHYS BOP – BRP – 72 110 G
1Typical values are at TA = 25°C and VDD = 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits.
2Magnetic operate and release points vary with supply voltage.
3If the device power supply is chopped, power-up slew rate dVDD / dt has to be adjusted to ensure correct functioning of the device. tOFF is the time of
the power cycle when VDD < VDD(min).
4Defined in the Functional Description section of this datasheet.
5Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section.
6If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Performance
Saturation Voltage versus Supply Voltage
0
50
100
150
200
250
300
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD (V)
V
OUT(SAT)
(mV)
1.0 2.0 3.0 4.0
1.0 2.0 3.0 4.0
Saturation Voltage versus Temperature
0
50
100
150
200
250
300
-60 -40 -20 0 20 40 60 80 100
T
A
(°C)
V
OUT(SAT)
(mV)
Average Supply Current versus Temperature
0
10
20
30
40
50
60
70
80
90
100
-60 -40 -20 0 20 40 60 80 100
TA (°C)
I
DD(AV)
(μA)
Average Supply Current versus Supply Voltage
0
10
20
30
40
50
60
70
80
90
100
1.5 2.5 3.5
VDD (V)
I
DD(AV)
(μA)
Normal Mode Period versus Temperature
0
100
200
300
400
500
600
700
800
900
1000
-60 -40 -20 0 20 40 60 80 100
TA (°C)
t
period
(μs)
Normal Mode Period versus Supply Voltage
0
100
200
300
400
500
600
700
800
900
1000
1.5 2.5 3.5
VDD (V)
t
period
(μs)
1.65
1.8
2.5
2.75
3.0
3.5
1.65
1.8
2.5
3.0
3.5
V
DD
(V)
I
OUT
= 1 mA
V
DD
(V) T
A
(°C)
1.65
1.8
2.5
3.0
3.5
V
DD
(V)
I
OUT
= 1 mA
85°C
-40°C
25°C
T
A
(°C)
85°C
-40°C
25°C
T
A
(°C)
85°C
-40°C
25°C
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dual Mode Fast Period versus Temperature
0
50
100
150
200
250
300
350
400
-60 -40 -20 0 20 40 60 80 100
TA (°C)
tfast_period
(μs)
tfast_period
(μs)
Dual Mode Fast Period versus Supply Voltage
0
50
100
150
200
250
300
350
400
1.0 1.5 2.0 2.5 3.0 3.5 4.0
V
DD
(V)
Dual Mode Slow Period versus Temperature
0
5
10
15
20
25
30
35
40
45
50
-60
-40
-20
0
20
40
60
80
100
T
A
(°C)
t
slow_period
(ms)
t
slow_period
(ms)
Dual Mode Slow Period versus Supply Voltage
0
5
10
15
20
25
30
35
40
45
50
1.0 2.0 3.0 4.0
1.5
2.5
3.5
1.0 2.0 3.0 4.0
1.5
2.5
3.5
V
DD
(V)
Operate Point versus Temperature
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
-60 -40 -20 0 20 40 60 80 100
T
A
(°C)
BOP (G)
Operate Point versus Supply Voltage
0
5
10
15
20
25
30
35
40
45
50
55
VCC (V)
BOP (G)
1.65
1.8
2.5
3.0
3.5
3.5
1.65
1.8
2.5
3.0
3.5
V
DD
(V)
V
DD
(V) T
A
(°C)
85°C
-40°C
25°C
T
A
(°C)
85°C
-40°C
25°C
T
A
(°C)
85°C
-40°C
25°C
1.65
1.8
2.5
2.75
3.0
3.5
V
DD
(V)
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Release Point versus Temperature
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
B
RP
(G)
Release Point versus Supply Voltage
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
BRP (G)
Hysteresis versus Temperature
0
10
20
30
40
50
60
70
80
90
100
110
-60 -40 -20 0 20 40 60 80 100
T
A
(°C)
-60 -40 -20 0 20 40 60 80 100
T
A
(°C)
B
HYS
(G)
Hysteresis versus Supply Voltage
0
10
20
30
40
50
60
70
80
90
100
110
B
HYS
(G)
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD (V)
1.5 2.5 3.5
1.0 2.0 3.0 4.0
VDD (V)
1.65
1.8
2.5
2.75
3.0
3.5
V
DD
(V)
T
A
(°C)
1.65
1.8
2.5
2.75
3.0
3.5
V
DD
(V)
85°C
-40°C
25°C
T
A
(°C)
85°C
-40°C
25°C
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Output State Operation
The output state (VOUT pin) of this device switches to low (on)
when an incident magnetic field, perpendicular to the Hall ele-
ment, exceeds the operate point threshold, BOP
. After turn-on,
the output voltage is VOUT(SAT) (see figure 2). When the magnetic
field is reduced below the release point, BRP , the device output
goes high (off), VOUT(HIGH)
. The difference in the magnetic oper-
ate and release points is the hysteresis, BHYS, of the device. This
built-in hysteresis allows clean switching of the output even in
the presence of external mechanical vibration and electrical noise.
Removal of the magnetic field leaves the device output latched
low (on) if the last crossed switchpoint is BOP , or latched high
(off) if the last crossed switchpoint is BRP .
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) gives an indeterminate output state. The correct
state is attained after the first excursion beyond BOP or BRP .
Micro-power Operation
Micro-power operation of the device involves duty cycle control
achieved by:
• powering all circuits in the chip and latching the device output
state at the end of awake state periods, and
• turning off the bias current to most circuits in the chip and
maintaining the device output state through sleep state periods.
This is illustrated in figure 3. The awake state duration, tawake_x
,
is common in all defined modes of operation. The sleep state
duration is set at a longer duration than the awake period in order
to conserve power. During the sleep state, current consumption
is insignificant (equal to IDD(DIS)), but the device output does not
switch in response to changing incident magnetic fields.
The device shows maximum current consumption, IDD(EN)
, dur-
ing the awake state and minimal current consumption, IDD(DIS)
,
during the sleep state. Average current, IDD(AV) , for micro-power
operation is derived from following formula:
IDD(AV) .
IDD(EN) × tawake_x + IDD(DIS) × tsleep_x
=tperiod_x
Three micro-power control modes are available:
• Normal Clock mode
• External Clock mode
• Dual Clock mode
Selection of clock mode is determined by the configuration of
the EXTERNAL_CLK pin and the DUAL_CLK pin, and applied
voltages as illustrated in figure 4 and table 1.
Normal Clock Mode When both device clock pins are left
floating or are grounded, the internal timing circuitry activates
the device for tawake_norm and deactivates it for the remainder,
tsleep
, of the duty cycle period, tperiod_norm. The short awake time
Figure 2. Device output switching logic
BOP
BRP
BHYS
VOUT(HIGH) (off)
VOUT
VOUT(SAT)(on)
Switch to Low
Switch to High
B+B– 0
V+
Figure 3. Micro-power behavior of the device
0
t
tperiod_x
tawake_x
tsleep_x
I
DD(EN)
I
DD
I
DD(DIS)
Sample and
output latched
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
allows stabilization prior to the IC sampling and data latching on
the falling edge of the timing pulse. The output during the sleep
time, tsleep , is latched in the last sampled state.
External Clock Mode Applying a voltage greater than
Vth(HIGH) to both clock pins puts the device into the awake state
(without automatic cycling through the sleep state). The device
uses the maximum defined supply current, reaching maximum
power consumption.
Applying a voltage greater than Vth(HIGH) to the EXTERNAL_
CLK pin and a voltage lower than Vth(LOW) to the DUAL_CLK
pin puts the device into the sleep state (without automatic cycling
through the awake state), and latches the device output in the
output state determined during the prior awake state.
The duration of the awake and sleep periods can be controlled
externally by applying a voltage greater than Vth(HIGH) to the
EXTERNAL_CLK pin and applying an external clock to the
DUAL_CLK pin. The user can define the input sampling time
and frequency to reach a target consumption current level, but the
minimum sample time must remain longer than tawake_ext. Note
that the device should be periodically put into the awake state in
order to update the device output state.
State Transition Delay, text_delay , appears as the time between
an external clock transition and the resulting transition of the
device between the awake and the sleep state. This is illustrated
in figure 5.
Dual Clock Mode When the EXTERNAL_CLK pin is left
floating, or is grounded, and the DUAL_CLK pin is pulled to
a voltage greater than Vth(HIGH) , the device enters Dual Clock
mode. Figure 6 gives an overview of the device operation algo-
rithm in Dual Clock mode.
Figure 5. External Clock mode clocking; tdelay_ext corresponding to the
device transition delay into the awake or sleep states after an external
clock transition
External
Clocking
Internal
Clocking
t
delay_ext
t
sleep_ext
t
awake_ext
t
delay_ext
Device Awake State Device Sleep State
Supply
Current
I
DD(EN)
I
DD(DIS)
Table 1. Clock Mode Selection Options
Connection Mode Description
EXTERNAL_CLK Pin DUAL_CLK Pin
Low / NC Low / NC Normal Clock Awake and sleep state durations
defined by device internal clock
High High External Clock, Awake State Awake and sleep state durations
defined by external clock
Low External Clock, Sleep State
Low / NC High Dual Clock Awake and sleep state durations
defined by internal fast or slow clock
High = V ≥ Vth(HIGH)
, Low = V ≤ Vth(LOW)
, NC = no connect (float or connect to ground)
Figure 4. Clock mode selection algorithm; determined by clock pins
connections in the application
Power on
EXTERNAL_CLK
pin high?
YES
NO
External Clock Mode
Awake State
External Clock Mode
Sleep State
Dual Clock Mode
Normal Clock Mode
YES
DUAL_CLK
pin high?
DUAL_CLK
pin high?
NO NO
YES
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Initially, the device operates in the slow sampling state with a
typical sleep time duration, tsleep_slow . The awake time duration,
tawake , is common in all defined modes of operation. After the
first output state transition, the device switches into the fast sam-
pling state, with a sleep time duration, tsleep_fast , of 8 × tawake_dual.
Fast input sampling ensures that the device does not miss any
subsequent transitions of the incident magnetic field. This is
advantageous in applications such as track ball monitoring, when
the track ball can be rotated at very high speeds. If there is no
output switching for the duration of the specified timeout, ttimeout,
then the device switches back into the slow sampling state to
conserve battery life in handheld devices.
Figure 7 shows the case in which the field does not change within
the ttimeout period. The behavior of the device in the presence of a
rapidly changing magnetic field is shown in figure 8.
Has
SleepTimer
expired?
Magnetic
field change?
ReturnTimer
expired ?
Reset
ReturnTimer
to t
timeout
Sample magnetic field
during t
awake_dual
YES
NO
Update device
output
Dual Clock Mode
Initial State
Set SleepTimer
to t
sleep_slow
Set SleepTimer
to t
sleep_slow
Set SleepTimer
to t
sleep_fast
NO
YES
YES
NO
Figure 6. Dual Clock mode operation algorithm
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
01000 2000 3000 4000 5000 6000
-50
0
50
01000 2000 3000 4000 5000 6000
01000 2000 3000 4000 5000 6000
01000 2000 3000 4000 5000 6000
0
200
400
(ms)
(ms)
(ms)
(ms)
Magnetic Field (G)
Off
On
Output
High
Low
Clock
Supply Current (μA)
01000 2000 3000
(ms)
(ms)
(ms)
(ms)
4000 5000 6000
-50
0
50
Magnetic Field (G)
01000 2000 3000 4000 5000 6000
Off
On
Output
01000 2000 3000 4000 5000 6000
High
Low
Clock
01000 2000 3000 4000 5000 6000
0
100
200
300
Supply Current (μA)
Figure 8. Device output response in Dual Clock mode with a rapid change of the
magnetic field
Figure 7. Device output response in Dual Clock mode with no change of the
magnetic field for the duration of ttimeout
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to reduce both external noise and
noise generated by the chopper stabilization technique (0.1 μF
is a typical value). Additionally, it is recommended that, when
possible, pins be tied to either the VDD pin or ground potential in
order to improve the EMC performance of the device. However,
it is feasible to float the EXTERNAL_CLK and DUAL_CLK
pins in the application. In the case where these pins are floating,
care should be taken to locate the device as far as possible from
system antennas and transceivers.
The schematics on this page represent typical application circuits.
(A) Device is working in Normal Clock mode. Power consump-
tion is determined by device internal clock.
(B) Device is working in Dual Clock mode. Power consumption
is determined by device internal clock; frequent usage of device
in fast sampling state.
(C) Device is working in External Clock mode; externally-con-
trolled power consumption.
(D) Device is working in External Clock mode; high power con-
sumption.
A1174
DUAL_CLK
VDD
GND
VOUT
EXTERNAL_CLK V
bat
C
bypass
A1174
DUAL_CLK
VDD
GND
VOUT
EXTERNAL_CLK
V
bat
C
bypass
A1174
DUAL_CLK
VDD
GND
VOUT
EXTERNAL_CLK
V
bat
C
bypass
A1174
DUAL_CLK
VDD
GND
VOUT
EXTERNAL_CLK
V
bat
C
bypass
(A)
(B)
(C)
(D)
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SEATING
PLANE
0.38 ±0.02
0.70 ±0.10 1.25 ±0.05
0.25 ±0.05
1.10 ±0.10
1.10
0.30
0.70 1.575
0.50
0.325
2.00 ±0.15
1.50 ±0.15
C0.08
7X
0.325 +0.055
–0.045
0.50 BSC
A
1
1
6
6
1
6
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Active Area Depth 0.15 mm REF
E
E
C
B
Hall Element (not to scale)
F
F
F
F
0.75
1.00
PCB Layout Reference View
C
Branding scale and appearance at supplier discretion
G
G
D
DCoplanarity includes exposed thermal pad and terminals
Standard Branding Reference View
N = Last two digits of device part number
Y = Last digit of year of manufacture
W = Week of manufacture
NN
YWW
1
Package EW 6-Contact MLP/DFN
Ultrasensitive Hall Ef fect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for T rack Ball and Scroll Wheel Applications
A1174
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2008-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Rev. 7 October 26, 2011 Update Selection Guide
