RT8086B
11
DS8086B-02 February 2016 www.richtek.com
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Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Voltage rating and current rating are the key parameters
when selecting an input ca pacitor . Generally , selecting an
input capa citor with voltage rating 1.5 tim es greater tha n
the maximum input voltage is a conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be a pproximately calculated using the
following equation :
OUT OUT
IN_RMS LOAD IN IN
VV
I = I 1
VV
The next step is selecting a proper capacitor for RMS
current rating. One good design uses more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor ba nk.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the f ollowing equation :
OUT(MAX) OUT OUT
IN IN SW IN IN
IVV
V = 1
Cf V V
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the Buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
P_P LOAD(MAX) OUT SW
1
V= LIRI ESR + 8C f
When load tra nsient occurs, the output ca pacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
ca n be calculated by the f ollowing equation :
SAG LOAD
V = I ESR
For a given output voltage sag specification, the ESR value
can be determined.
Another para meter that has influence on the output voltage
sag is the equivalent series inducta nce (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a ca pacitor with low ESL ca n obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
tha n using a single capa citor f or the same total ESR.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the a mbient temperature, and θJA is the junction to a mbient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
a mbient thermal resistance, θJA, is layout dependent. For
UQF N-12L 2x2(FC) package, the thermal resistance, θJA,
is 80°C/W on a sta ndard JEDEC 51-7 four-layer thermal
test board. The maxi mum power dissipation at TA = 25°C
ca n be calculated by the f ollowing formula :
PD(MAX) = (125°C − 25°C) / (80°C/W) = 1.25W for
UQF N-12L 2x2 (FC) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 2 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 2. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 25 50 75 100 125
Ambient Tem pera ture (°C)
Maxi mum Power Di ssipation (W ) 1
Four-Layer PCB