Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
http://www.cirrus.com DECEMBER '07
DS646F2
108 dB, 192 kHz 6-In, 8-Out TDM CODEC
FEATURES
Six 24-bit A/D, Eight 24-bit D/A Converters
ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
DAC Sampling Rates up to 192 kHz
ADC Sampling Rates up to 96 kHz
Programmable ADC High-Pass Filter for DC
Offset Calibration
Logarithmic Digital Volume Control
Hardware Mode or Software I²C® & SPI™
Supports Logic Levels Between 5 V and 1.8 V
GENERAL DESCRIPTION
The CS42438 CODEC provides six multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of oper ation with ei-
ther differential or single -e nded inp uts and outputs, in a
52-pin MQFP package.
Six fully differential, or single-ended, inputs are avail-
able on stereo ADC1, ADC2, and ADC3. When
operating in Single-Ended Mode, an internal MUX be-
fore ADC3 allows selection from up to four single-ended
inputs. Digital volume control is provided for each ADC
channel, with selectable overflow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42438 is available in a 52-pin MQFP package in
Commercial (-10°C to +70°C) and Automotive (-40°C to
+105°C) grades. The CDB42438 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 61 for complete ordering
information.
The CS42438 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Register
Configuration Internal Vo ltage
Reference
Reset
TDM Serial
Interface
Level TranslatorLevel Translator
TDM Serial Audio
Input
Digital Supply =
3.3 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Analog Supply =
3.3 V to 5 V
Differen tial or
Single-Ended
Outputs
8
Input Master
Clock
8
TDM Serial Audio
Output
Multibit
Oversampling
ADC1&2
High Pass
Filter Differential or
Single-Ended
Analog Inputs
4
Digital
Filters 4
*Optional MUX allows selection from up to 4 single-ended inputs.
Multibit
Oversampling
ADC3
High Pass
Filter 2
Digital
Filters 2
4:2*
Auxilliary Serial
Audio Input
Volume
Controls Digital
Filters
Multibit
DAC1-4 and
Analog Filters
ΔΣ
Modulators
CS42438
2DS646F2
CS42438
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE MODE ......................................................................................... 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. PIN DESCRIPTIONS - HARDWARE MODE ....................................................................................... 9
3. TYPICAL CONNECTION DIAGRAMS .................................................................................................11
4. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13
RECOMMENDED OPERATING CONDITIONS ................................................................................... 13
ABSOLUTE MAXIMUM RATINGS .......................................................................................................13
ANALOG INPUT CHARACTERISTICS (COMMERCIAL) .................................................................... 14
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) ..................................................................... 15
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 16
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) ................................................................ 17
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) ................................................................. 18
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20
SWITCHING SPECIFICATIONS - ADC/DAC PORT ............................................................................ 21
SWITCHING CHARACTERISTICS - AUX PORT ................................................................................. 22
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE ....................................................... 23
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................................. 24
DC ELECTRICAL CHARA CTERISTIC S ..................................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 25
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 25
5. APPLICATIONS ................................................................................................................................... 26
5.1 Overview ......................................................................................................................................... 26
5.2 Analog Inputs .................................................................................................................................. 27
5.2.1 Line-Level Inputs ................ ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ...................... 27
5.2.1.1 Hardware Mode ......................................................................................................... 27
5.2.1.2 Software Mode .............. ... ... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... ... 27
5.2.2 ADC3 Analog Input ................................................................................................................ 28
5.2.3 Hardware Mode .............. .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................... 29
5.2.4 Software Mode ............... .... ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ............ 29
5.2.5 High-Pass Filter and DC Offset Calibration ........................................................................... 29
5.2.5.1 Hardware Mode ......................................................................................................... 29
5.2.5.2 Software Mode .............. ... ... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... ... 29
5.3 Analog Outputs ............................................................................................................................... 30
5.3.1 Initialization .. ................ ... .... ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ............................ 30
5.3.2 Line-Level Outputs and Filtering ........................................................................................... 30
5.3.3 Digital Volume Control . ... .... ... ... ............................................................................................. 32
5.3.3.1 Hardware Mode ......................................................................................................... 32
5.3.3.2 Software Mode .............. ... ... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... ... 32
5.3.4 De-Emphasis Filter ...... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ......................... 32
5.4 System Clocking ............................................................................................................................. 33
5.4.1 Hardware Mode .............. .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................... 33
5.4.2 Software Mode ............... .... ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ............ 33
5.5 CODEC Digital Interface ................................................................................................................. 33
5.5.1 TDM ................................................................................................................................. 33
5.5.2 I/O Channel Allocation ........................................................................................................... 34
5.6 AUX Port Digital Interface Formats ................................................................................................ 34
5.6.1 Hardware Mode .............. .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................... 34
5.6.2 Software Mode ............... .... ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ............ 34
5.6.3 I²S ...... ... .... ... ................ ... .... ... ................ ... ... ................. ... ... ... ................ .... ... ......................... 34
5.6.4 Left-Justified .......... ... ... ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ... ................. ... ... ... ................... 35
5.7 Control Port Description and Timing ............................................................................................... 35
5.7.1 SPI Mode ........... .... ................ ... ... ... .... ... ................ ... .... ... ... ... ................ .... ... ... ... ... ................ 35
5.7.2 I²C Mode ...................... ... .... ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ............................ 36
DS646F2 3
CS42438
5.8 Recommended Power-Up Sequence ............................................................................................. 37
5.8.1 Hardware Mode ..................................................................................................................... 37
5.8.2 Software Mode ...................................................................................................................... 38
5.9 Reset and Power-Up ...................................................................................................................... 38
5.10 Power Supply, Grounding, and PCB Layout ................................................................................ 38
6. REGISTER QUICK REFERENCE ........................................................................................................ 39
7. REGISTER DESCRIPTION .................................................................................................................. 41
7.1 Memory Address Pointer (MAP) ..................................................................................................... 41
7.1.1 Increment (INCR) .................................................................................................................. 41
7.1.2 Memory Address Pointer (MAP[6:0]) .. ......... .......... .......... ......... .......... .......... ......... .......... ...... 41
7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 41
7.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41
7.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41
7.3 Power Control (Address 02h) ......................................................................................................... 42
7.3.1 Power Down ADC Pairs (PDN_ADCX) ........... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
7.3.2 Power Down DAC Pairs (PDN_DACX) ....... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
7.3.3 Power Down (PDN) ............ ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ...................... 42
7.4 Functional Mode (Address 03h) .............. .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 43
7.4.1 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43
7.5 Miscellaneous Control (Address 04h) ................ ................ ................ ................. ................ ............ 43
7.5.1 Freeze Controls (FREEZE) ................................................................................................... 43
7.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 43
7.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 44
7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 44
7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 44
7.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 44
7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 44
7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 44
7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 45
7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 45
7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 45
7.7 Transition Control (Address 06h) . ... ... ... .......................................................................................... 45
7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 45
7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 46
7.7.3 Auto-Mute (AMUTE) .............................................................................................................. 46
7.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 47
7.8 DAC Channel Mute (Address 07h) ................................................................................................. 47
7.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 47
7.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 47
7.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 47
7.10 DAC Channel Invert (Address 10h) .............................................................................................. 48
7.10.1 Invert Signal Polarity (INV_AOUTX) .... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ... ... ... ... 48
7.11 AINX Volume Control (Address 11h-16h) .. ...................................................................................48
7.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 48
7.12 ADC Channel Invert (Address 17h) .............................................................................................. 49
7.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 49
7.13 Status (Address 19h) (Read Only) ............... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 49
7.13.1 CLOCK ERROR (CLK ERROR) ............. ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 49
7.13.2 ADC Overflow (ADCX_OVFL) .......... ...... ... .......................................................................... 49
7.14 Status Mask (Address 1Ah) .......................................................................................................... 49
8. EXTERNAL FILTERS ........................................................................................................................... 50
8.1 ADC Input Filter .............................................................................................................................. 50
8.1.1 Passive Input Filter ............................................................................................................. 51
8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 52
4DS646F2
CS42438
8.2 DAC Output Filter ........................................................................................................................... 53
9. ADC FILTER PLOTS ............................................................................................................................ 54
10. DAC FILTER PLOTS .......................................................................................................................... 56
11. PARAMETER DEFINITIONS .............................................................................................................. 58
12. REFERENCES .................................................................................................................................... 59
13. PACKAGE INFORMATION ................................................................................................................ 60
13.1 Thermal Characteristics ............................................................................................................... 60
14. ORDERING INFORMATION .............................................................................................................. 61
15. REVISION HISTORY .......................................................................................................................... 61
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 11
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 12
Figure 3.Output Test Circuit for Maximum Load ....................................................................................... 19
Figure 4.Maximum Loading ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ................... 19
Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 21
Figure 6.Serial Audio Interface Slave Mode Timing .................................................................................. 22
Figure 7.Control Port Timing - I²C Format . ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ............ 23
Figure 8.Control Port Timing - SPI Format ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 24
Figure 9.Full-Scale Input .... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ......................... 28
Figure 10.ADC3 Input Topology ... ... ... .... ... ... ... .......................................................................................... 28
Figure 11.Audio Output Initialization Flow Chart ....................................................................................... 31
Figure 12.Full-Scale Output ............... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 32
Figure 13.De-Emphasis Curve ..................... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... ................ 33
Figure 14.TDM Serial Audio Format ......................................................................................................... 34
Figure 15.AUX I²S Format ......................................................................................................................... 34
Figure 16.AUX Left-Justified Format ............... ... .... ... ... ................ .... ... ... ... ... .... ... ... ... .... ............................ 35
Figure 17.Control Port Timing in SPI Mode .............................................................................................. 36
Figure 18.Control Port Timing, I²C Write ................................................................................................... 36
Figure 19.Control Port Timing, I²C Read ................................................................................................... 37
Figure 20.Single to Differential Active Input Filter ..................................................................................... 50
Figure 21.Single-Ended Active Input Filter ................................................................................................ 50
Figure 22.Passive Input Filter ................................................................................................................... 51
Figure 23.Passive Input Filter w/Attenuation ............. ............. ............. ............. ............. ............ ................ 52
Figure 24.Active Analog Output Filter ....................................................................................................... 53
Figure 25.Passive Analog Output Filter ....... ............................................................................................. 53
Figure 26.SSM Stopband Rejection .......................................................................................................... 54
Figure 27.SSM Transition Band ................................................................................................................ 54
Figure 28.SSM Transition Band (Detail) ................................................................................................... 54
Figure 29.SSM Passband Ripple ........... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ................ 54
Figure 30.DSM Stopband Rejection ....... ... ... ... ... ................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 54
Figure 31.DSM Transition Band ... ... ... .... ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ... ......................... 54
Figure 32.DSM Transition Band (Detail) ................................................................................................... 55
Figure 33.DSM Passband Ripple . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... ................ 55
Figure 34.SSM Stopband Rejection .......................................................................................................... 56
Figure 35.SSM Transition Band ................................................................................................................ 56
Figure 36.SSM Transition Band (detail) .................................................................................................... 56
Figure 37.SSM Passband Ripple ........... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ................ 56
Figure 38.DSM Stopband Rejection ....... ... ... ... ... ................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 56
Figure 39.DSM Transition Band ... ... ... .... ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ... ......................... 56
Figure 40.DSM Transition Band (detail) . ................................................................................................... 57
Figure 41.DSM Passband Ripple . ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... ................ 57
Figure 42.QSM Stopband Rejection ......................................................................................................... 57
DS646F2 5
CS42438
Figure 43.QSM Transition Band ................................................................................................................ 57
Figure 44.QSM Transition Band (detail) .......... ................ ................. ................ ................ ......................... 57
Figure 45.QSM Passband Ripple .............................................................................................................. 57
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Hardware Configurable Settings ................................................................................................. 26
Table 3. AIN5 Analog Input Selection ....................................................................................................... 29
Table 4. AIN6 Analog Input Selection ....................................................................................................... 29
Table 5. MCLK Frequency Settings .......................................................................................................... 33
Table 6. Serial Audio Interface Channel Allocations ................................................................................. 34
Table 7. MCLK Frequency Settings .......................................................................................................... 43
Table 8. Example AOUT Volume Settings ................................................................................................ 47
Table 9. Example AIN Volume Settings .................................................................................................... 48
6DS646F2
CS42438
1. PIN DESCRIPTIONS - SOFTWARE MODE
Pin Name # Pin Description
SCL/CCLK 1 Serial Control Port Clock (Input) - Seria l clock for the control port interface.
SDA/CDOUT 2 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data.
AD0/CS 3Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select
the chip in SPI Mode.
AD1/CDIN 4 Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data.
RST 5Reset (Input) - The device enters a low-power mode and all internal registers are reset to their
default settings when low.
VLC 6 Control Port Power (Input) - Determines the required signal level for the control port interface.
See “Digital I/O Pin Characteristics” on page 8.
FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.
VD 8 Digital Power (Input) - Positive power supply for the di g i tal sectio n.
DGND 9,18 Digital Ground (Input) -
VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-
faces. See “Digital I/O Pin Characteristics” on page 8.
SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs.
MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filte r s.
ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.
DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.
AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active
on the Auxiliary serial audi o data line.
SCL/CCLK
6
2
4
8
10
1
3
5
7
9
11
12
14 15 16 17 18 19 20 21 22 23 24 25
33
37
35
31
29
38
36
34
32
30
28
27
52 51 50 49 48 47 46 45 44 43 42 41
VLS
FS
MCLK
VLC
AD1/CDIN
AOUT7-
AOUT5+
AOUT3+
AGND
VA
AUX_SDIN
DAC_SDIN
ADC_SDOUT
AUX_SCLK
AUX_LRCK
AD0/CS
AOUT4+
RST
AOUT6+
AOUT3-
AOUT2+
AOUT2-
AOUT1-
AOUT1+
DGND
VD
SCLK
DGND
VQ
AOUT6-
AOUT4-
13
SDA/CDOUT
26
39
AOUT5-
40
AOUT7+
AOUT8+
AOUT8-
FILT+
VA
AGND
AIN6+/AIN6A
AIN6-/AIN6B
AIN3+
AIN4-
AIN4+
AIN5-/AIN5B
AIN3-
AIN5+/AIN5A
AIN2-
AIN2+
AIN1+
AIN1-
CS42438
DS646F2 7
CS42438
AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
AUX_SDIN 17 Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-
ment serial audio data.
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
AOUT7 +,-
AOUT8 +,-
20,19
21,22
24,23
25,26
28,27
29,30
31,32
33,34
Differential Analog Output (Output) - The full-scale differential analog output level is specified in
the Analog Characteristics specificatio n table. Each positive leg of the differential outputs may
also be used single-ended.
AGND 35,48 Analog Ground (Input) - Ground reference for the analog section.
VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
VA 37,46 Analog Power (Input) - Positive power sup ply for the analog section.
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
AIN5 +,-
AIN6 +,-
39,38
41,40
43,42
45,44
50,49
52,51
Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-
ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.
Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to
common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.
AIN5 A,B
AIN6 A,B 50,49
52,51
Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows
selection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6. 6-7.6.8
for details). The unused leg of each input is internally connected to common mode. The full-scale
input level is specified in the Analog Characteristics specification table.
FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits.
8DS646F2
CS42438
1.1 Digital I/O Pin Characteristics
Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input
should adhere to the correspon ding power rail and should not exceed th e maximum ratings.
Power
Rail Pin Name
SW/(HW) I/O Driver Receiver
VLC RST Input - 1.8 V - 5.0 V, CMOS
SCL/CCLK
(AIN5_MUX) Input - 1.8 V - 5.0 V, CMOS, with Hysteresis
SDA/CDOUT
(AIN6_MUX) Input/
Output 1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS, with Hysteresis
AD0/CS
(MFREQ) Input - 1.8 V - 5.0 V, CMOS
AD1/CDIN
(ADC3_HPF) Input - 1.8 V - 5.0 V, CMOS
VLS MCLK Input - 1.8 V - 5.0 V, CMOS
LRCK Input -1.8 V - 5.0 V, CMOS
SCLK Input -1.8 V - 5.0 V, CMOS
ADC_SDOUT3
(ADC3_SINGLE) Input/
Output 1.8 V - 5.0 V, CMOS -
DAC_SDIN Input - 1.8 V - 5.0 V, CMOS
AUX_LRCK Output 1.8 V - 5.0 V, CMOS -
AUX_SCLK Output 1.8 V - 5.0 V, CMOS -
AUX_SDIN Input - 1.8 V - 5.0 V, CMOS
Table 1. I/O Power Rails
DS646F2 9
CS42438
2. PIN DESCRIPTIONS - HARDWARE MODE
Pin Name # Pin Description
AIN5_MUX
AIN6_MUX 1
2Analog Input Multiple xer (Input) - Allows selection between the A and B single-ended inputs of
ADC3.
MFREQ 3 MCLK F requency (Input) - Sets the required frequency range of the input Master Clock.
ADC3_HPF 4 ADC3 High-Pass Filter Freeze (Input) - When this pin is driven hi gh, the internal high-pass filter
will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted
from the conversion result.
RST 5Reset (Input) - The device enters a low-power mode and all intern al registers are reset to their
default settings when low.
VLC 6 Control Port Power (Input) - Determines the required signal level for the control port interface.
See “Digital I/O Pin Characteristics” on page 8.
FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.
VD 8 Digital Power (Input) - Positive power supply for the digital section.
DGND 9,18 Digital Ground (Input) - Ground reference for the digital section.
VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-
faces. See “Digital I/O Pin Characteristics” on page 8.
SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs.
MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.
ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.
DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.
AIN5_MUX
6
2
4
8
10
1
3
5
7
9
11
12
14 15 16 17 18 19 20 21 22 23 24 25
33
37
35
31
29
38
36
34
32
30
28
27
52 51 50 49 48 47 46 45 44 43 42 41
VLS
FS
MCLK
VLC
ADC3_HPF
FILT+
AOUT7-
AOUT5+
AOUT3+
AGND
VA
AUX_SDIN
DAC_SDIN
ADC_SDOUT/
ADC3_SINGLE
AUX_SCLK
AUX_LRCK
MFREQ
AOUT4+
RST
AOUT6+
AOUT3-
VA
AGND
AOUT2+
AOUT2-
AOUT1-
AOUT1+
DGND
VD
SCLK
DGND
VQ
AIN6+/AIN6A
AIN6-/AIN6B
AOUT6-
AOUT4-
13
AIN6_MUX
26
39
AOUT5-
40
AOUT7+
AOUT8+
AOUT8-
AIN3+
AIN4-
AIN4+
AIN5-/AIN5B
AIN3-
AIN5+/AIN5A
AIN1+
AIN2-
AIN2+
AIN1-
CS42438
10 DS646F2
CS42438
AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active
on the Auxiliary serial audi o data line.
AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
AUX_SDIN 17 Auxiliary Serial Input (Input) - The 42438 provi des an additional serial input for two’s comple-
ment serial audio data.
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
AOUT7 +,-
AOUT8 +,-
20,19
21,22
24,23
25,26
28,27
29,30
32,31,
33,34
Differential Ana log Output (Output) - The full-scale differential analog output level is specified in
the Analog Characteristics specification table. Each positive leg of the differential outputs may
also be used single-ended.
AGND 35,48 Analog Ground (Input) - Ground reference for the analog section.
VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescen t referen ce voltage.
VA 37,46 Analog Power (Input) - Positive power supply for the analog section.
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
AIN5 +,-
AIN6 +,-
39,38
41,40
43,42
45,44
50,49
52,51
Differential Analog Inpu t (Input) - Signals are presented differentially to the delta-sigma modula-
tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-
ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.
Once in Single-Ended Mode, the neg ative terminal of AIN1-AIN4 must be externally driven to
common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.
AIN5 A,B
AIN6 A,B 50,49
52,51
Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal ana log mux allows
selection between two channels for both analog inp uts AIN5 and AIN6 (see Sections 7.6.6-7.6.8
for details). The unused leg of each input is internally connected to common mode. The full-scale
input level is specified in the Analog Characteristi c s specification table.
FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits.
DS646F2 11
CS42438
3. TYPICAL CONNECTION DIAGRAMS
100 µF 0.1 µF
++
VQ
FILT+
0.1 µF 4.7 µF
VA
0.01 µF
DGND
Digital A udio
Processor
CS5341
A/D
Converter
VAVD
AGNDAGND
AIN1+
AIN1-
Connect DGND and AGND at Codec
0.01 µF
+10 µF
0.01 µF
+3.3 V +
10 µF 0.01 µF
+1.8 V
to +5.0 V
Analog Input 1
Input
Filter 1
1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.
Analog Input 2
Analog Input 3
Analog Input 4
AIN5+/AIN5A
+3.3 V to +5 V
DGND
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
AIN5-/AIN5B
AIN6+/AIN6A
AIN6-/AIN6B
Analog Input 5
Analog Input 6
Analog Input 5A
Analog Input 5B
Analog Input 6A
Analog Input 6B
Input
Filter 1
AOUT1+
AOUT1-
AOUT2+
AOUT2-
AOUT3+
AOUT3-
AOUT4+
AOUT4-
Analog Output F i l ter 2
Analog Output F i l ter 2
Analog Output F i l ter 2
AOUT5+
AOUT5-
AOUT6+
AOUT6-
AOUT7+
AOUT7-
AOUT8+
AOUT8-
Analog Output F i l ter 2
Analog Output F i l ter 2
Analog Output F i l ter 2
Analog Output F i l ter 2
Analog Output F i l ter 2
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
0.1 µF
+1.8 V
to +5 V
Micro-
Controller
2 kΩ2 kΩ
** **
** Resistors are required for
I2C control port operation
3
4
2
1
5
13
14
7
11
12
17
16
10
15
6
9483518
47
37
51
52
49
50
44
45
42
43
40
41
38
39
34
33
31
32
30
29
27
28
26
25
23
24
22
21
19
20
46378
VLC
SCL/CCLK
RST
AD0/CS
SDA/CDOUT
AD1/CDIN
MCLK
AUX_SDIN
DAC_SDIN
FS
SCLK
AUX_SCLK
AUX_LRCK
ADC_SDOUT
VLS
Figure 1. Typical Connection Diagram (Software Mode)
12 DS646F2
CS42438
100 µF 0.1 µF
++
VQ
FILT+
0.1 µF 4.7 µF
VA
0.01 µF
DGND
0.1 µF
Digital Audio
Processor
CS5341
A/D
Converter
VAVD
AGND
AGND
AIN1+
AIN1-
Connect DGND and AGND at Codec
0.01 µF
+10 µF
0.01 µF
+3.3 V +
10 µF 0.01 µF
+1.8 V
to +5.0 V
Analog Input 1
Input
Filter 1
1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.
Analog Input 2
Analog Input 3
Analog Input 4
AIN5+/AIN5A
+3.3 V to +5 V
DGND
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
AIN5-/AIN5B
AIN6+/AIN6A
AIN6-/AIN6B
Analog Input 5
Analog Input 6
Analog Input 5A
Analog Input 5B
Analog Input 6A
Analog Input 6B
VLS
*
*
* MUX configuration settings for AIN5-AIN6. See
the ADC Input MUX section.
Input
Filter 1
AOUT1+
AOUT1-
AOUT2+
AOUT2-
AOUT3+
AOUT3-
AOUT4+
AOUT4-
Analog Output Filter 2
Analog Output Filter 2
Analog Output Filter 2
AOUT5+
AOUT5-
AOUT6+
AOUT6-
AOUT7+
AOUT7-
AOUT8+
AOUT8-
Analog Output Filter 2
Analog Output Filter 2
Analog Output Filter 2
Analog Output Filter 2
Analog Output Filter 2
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
Input
Filter 1
3
4
2
1
5
13
14
7
11
12
17
16
10
15
6
9483518
47
37
51
52
49
50
44
45
42
43
40
41
38
39
34
33
31
32
30
29
27
28
26
25
23
24
22
21
19
20
46378
VLC
AIN5_MUX
AIN6_MUX
ADC3_HPF
RST
MFREQ
VLS
MCLK
AUX_SDIN
DAC_SDIN
FS
SCLK
AUX_SCLK
AUX_LRCK
ADC_SDOUT/
ADC3_SINGLE
Figure 2. Typical Connection Diagram (Hardware Mode)
DS646F2 13
CS42438
4. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
WARNING:Operation at or beyond these limit s may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes: 1. Typical Analog input/output performance will slightly degrade at VA = 3.3 V.
2. The ADC_SDOUT may not meet timing requirements in Double-Speed Mode.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
4. The maximum over/unde r voltage is limited by the input current.
Parameters Symbol Min Max Units
DC Power Supply
Analog (Note 1) VA 3.14 5.25 V
Digital VD 3.14 3.47 V
Serial Audio Interface (Note 2) VLS 1.71 5.25 V
Control Port Interface VLC 1.71 5.25 V
Ambient Temperature
Commercial -CMZ
Automotive -DMZ TA-10
-40 +70
+105 °C
°C
Parameters Symbol Min Max Units
DC Power Supply Analog
Digital
Serial Port Interface
Control Port Interface
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
6.0
6.0
6.0
V
V
V
V
Input Current (Note 3) Iin -±10mA
Analog Input Voltage (Note 4) VIN AGND-0.7 VA+0.7 V
Digital Input Voltage Serial Port Interface
(Note 4) Control Port Interface VIND-S
VIND-C
-0.3
-0.3 VLS+ 0.4
VLC+ 0.4 V
V
Ambient Operating Temperature
(power applied) TA-50 +125 °C
Storage Temperature Tstg -65 +150 °C
14 DS646F2
CS42438
ANALOG INPUT CHARACTERISTICS (COMMERCIAL)
(Test Conditions (unless otherwise specified): TA=-10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%;
Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50;
Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential Single-Ended
Parameter Min Typ Max Min Typ Max Unit
Fs=48 kHz, 96 kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighte d
99
96
-
105
102
99
-
-
-
96
93 102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise -1 dB
(Note 5) -20 dB
-60 dB
40 kHz bandwidth -1 dB
-
-
-
-
-98
-82
-42
-90
-92
-
-
-
-
-
-
-
-95
-79
-39
-90
-89
-
-
-
dB
dB
dB
dB
ADC1-3 Interchannel Isolation - 90 - - 90 - dB
ADC3 MUX Interchannel Isolation - 90 - - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Gain Drift - ±100 - - ±100 - ppm/°C
Analog Input
Full-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp
Differential In pu t Imp edance (Notes 6 & 8 ) 23 29 32 kΩ
Single-Ended Input Impedance
(Notes 7 & 8) ---232932kΩ
Common Mode Rejection Ratio (CMRR) - 82 - - - - dB
DS646F2 15
CS42438
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE)
(Test Conditions (unless otherwise specified): TA= -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%;
Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50;
Measurement Bandwidth is 10 Hz to 20 kHz.)
Notes: 5. Referred to the typical full-scale voltage.
6. Measured between AINx+ and AINx-.
7. Measured between AINxx and AGND.
8. The input impedance scales inversely proportionate to the sample rate of the ADC modulato r
Differential Single-Ended
Parameter Min Typ Max Min Typ Max Unit
Fs=48 kHz, 96 kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
97
94
-
105
102
99
-
-
-
94
91
-
102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise -1 dB
(Note 5) -20 dB
-60 dB
40 kHz bandwidth -1 dB
-
-
-
-
-98
-82
-42
-87
-90
-
-
-
-
-
-
-
-95
-79
-39
-87
-87
-
-
-
dB
dB
dB
dB
ADC1-3 Interchannel Isolation - 90 - - 90 - dB
ADC3 MUX Interchannel Isolation - 85 - - 85 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Gain Drift - ±100 - - ±100 - ppm/°C
Analog Inpu t
Full-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp
Differential Input Impedance (Notes 6 & 8) 23 29 32 kΩ
Single-Ended Input Impedance
(Notes 7 & 8) ---232932kΩ
Common Mode Rejection Ratio (CMRR) - 82 - - - - dB
16 DS646F2
CS42438
ADC DIGITAL FILTER CHARACTERISTICS
Notes: 9. Filter response is guaranteed by design.
10. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 33) have
been normalized to Fs and can be de-normalized by multiplying the X- axis scale by Fs.
Parameter (Notes 9, 10) Min Typ Max Unit
Single-Speed Mode (Note 10)
Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs
Passband Ripple - - 0.08 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay - 12/Fs - s
Double-Speed Mode (Note 10)
Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs
Passband Ripple - - 0.16 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay - 9/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB -1
20 -
-Hz
Hz
Phase Deviation @ 20 Hz - 10 - Deg
Passband Ripple - - 0 dB
Filter Settling Time - 105/Fs 0 s
DS646F2 17
CS42438
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL)
(Test Conditions (unless otherwise specified): TA= -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%;
Full-scale 997 Hz output sine wave (see Note 12) into passive filter in Figure 26 on pa ge 54 and active filter in Fig-
ure 26 on page 54; Measurement Bandwidth is 10 Hz to 20 kHz.)
Parameter Differential
Min Typ Max Single-Ended
Min Typ Max Unit
Fs = 48 kHz, 96 kHz, 192 kHz
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
102
99
-
-
108
105
99
96
-
-
-
-
99
96
-
-
105
102
96
93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-98
-85
-45
-93
-76
-36
-92
-
-
-
-
-
-
-
-
-
-
-95
-82
-42
-90
-73
-33
-89
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
Analog Output
Full-Scale Output 1.235•VA 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA Vpp
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
Output Impedance - 100 - - 100 - Ω
DC Current draw from an AOUT pin
(Note 11) --10--10μA
AC-Load Resistance (RL)(Note 13) 3--3--kΩ
Load Capacit ance (CL)(Note 13) - - 100 - - 100 pF
18 DS646F2
CS42438
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE)
(Test Conditions (unless otherwise specified): TA=-40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%;
Full-scale 997 Hz output sine wave (see Note 12) in Fig ure 26 on page 54 and Figure 26 on page 54; Measure-
ment Bandwidth is 10 Hz to 20 kHz.)
Notes: 11. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the elec trolytic DC-blocking capacitor s.
12. One-half LSB of triangular PDF dither is added to data.
13. Guaranteed by design. See Figure 3. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit to-
pology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing
this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See
“External Filters” on page 50 for a recommended output filter.
Parameter Differential
Min Typ Max Single-Ended
Min Typ Max Unit
Fs = 48 kHz, 96 kHz, 192 kHz
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
100
97
-
-
108
105
99
96
-
-
-
-
97
94
-
-
105
102
96
93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-98
-85
-45
-93
-76
-36
-90
-
-
-
-
-
-
-
-
-
-
-
-95
-82
-42
-90
-73
-33
-87
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
Analog Output
Full-Scale Output 1.210•VA 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
Output Impedance - 100 - - 100 - Ω
DC Current draw from an AOUT pin
(Note 11) - - 10 - - 10 μA
AC-Load Resistance (RL) (Note 13) 3--3--kΩ
Load Capacitance (CL)(Note 13) - - 100 - - 100 pF
20 DS646F2
CS42438
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Notes: 14. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 34 to 45) have
been normalized to Fs and can be de-normalized by multiplying the X- axis scale by Fs.
15. Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs.
Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs.
16. De-emphasis is only available in Single-Speed Mode.
Parameter (Notes 9, 14) Min Typ Max Unit
Single-Speed Mode
Passband (Frequency Response) to -0.05 dB corner
to -3 dB corner 0
0-
-0.4780
0.4996 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.2 - +0.08 dB
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 15) 50 - - dB
Group Delay - 10/Fs - s
De-emphasis Error (Note 16) Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
Double-Speed Mode
Passband (Frequency Respon se) to -0.1 dB corner
to -3 dB corner 0
0-
-0.4650
0.4982 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.2 - +0.7 dB
StopBand 0.5770 - - Fs
StopBand Attenuation (Note 15) 55 - - dB
Group Delay - 5/Fs - s
Quad-Speed Mode
Passband (Frequency Respon se) to -0.1 dB corner
to -3 dB corner 0
0-
-0.397
0.476 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.2 - +0.05 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 15) 51 - - dB
Group Delay - 2.5/Fs - s
DS646F2 21
CS42438
SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.)
Notes: 17. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.
18. See Table 7 on page 43 for suggested MCLK frequencies.
19. VLS is limited to nominal 2.5 V to 5.0 V operation only.
20. ADC does not meet timing specification for Quad-Speed Mode.
Parameters Symbol Min Max Units
Slave Mode
RST pin Low Pulse Width (Note 17) 1-ms
MCLK Frequency 0.512 50 MHz
MCLK Duty Cycle (Note 18) 45 55 %
Input Sample Rate (FS pin) Single-Speed Mode
Double-Speed Mode (Note 19)
Quad-Speed Mode (Note 20)
Fs
Fs
Fs
4
50
100
50
100
200
kHz
kHz
kHz
SCLK Duty Cycle 45 55 %
SCLK High Time tsckh 8-ns
SCLK Low Time tsckl 8-ns
FS Rising Edge to SCLK Rising Edge tfss 5-ns
SCLK Rising Edge to FS Falling Edge tfsh 16 - ns
DAC_SDIN Setup Time Before SCLK Rising Edge tds 3-ns
DAC_SDIN Hold Time After SCLK Rising Edge tdh 5-ns
DAC_SDIN Hold Time After SCLK Rising Edge tdh1 5-ns
ADC_SDOUT Hold Time After SCLK Rising Edge tdh2 10 - ns
ADC_SDOUT Valid Before SCLK Rising Edge tdval 15 - ns
ADC_SDOUT
DAC_SDIN
tds
SCLK
(input)
FS
(input)
MSB
tdh1
tsckh tsckl
tdval
MSB-1
MSB MSB-1
tfsh
tfss
tdh2
Figure 5. TDM Serial Audio Interface Timing
22 DS646F2
CS42438
SWITCHING CHARACTERISTICS - AUX PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS.)
Parameters Symbol Min Max Units
Master Mode
Output Sample Rate (AUX_LRCK) All Speed Modes Fs- LRCK kHz
AUX_SCLK Frequency - 64·LRCK kHz
AUX_SCLK Duty Cycle 45 55 %
AUX_LRCK Edge to SCLK Rising Edge tlcks -5ns
AUX_SDIN Setup Time Before SCLK Rising Edge tds 3-ns
AUX_SDIN Hold Time After SCLK Rising Edge tdh 5-ns
AUX_SDIN
AUX_SCLK
AUX_LRCK
tsckh tsckl
tlcks
tds
MSB
tdh
MSB-1
Figure 6. Serial Audio Interface Slave Mode Timing
DS646F2 23
CS42438
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL=30pF)
Notes: 21. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
22. Guaranteed by design.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RST Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 21) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA (Note 22) trc -1µs
Fall Time SCL and SDA (Note 22) tfc -300ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling tack 300 1000 ns
tbuf thdst
tlow thdd
thigh
tsud
Stop Start
SDA
SCL
tirs
RST
thdst
trc
tfc
tsust
tsus
p
Start Stop
Repeated
trd tfd
tack
Figure 7. Control Port Timing - I²C Format
24 DS646F2
CS42438
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL=30pF)
Notes: 23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. Fo r fsck <1 MHz.
Parameter Symbol Min Max Units
CCLK Clock Frequency fsck 06.0MHz
RST Rising Edge to CS Falling tsrs 20 - ns
CS Falling to CCLK Edge tcss 20 - ns
CS High Time Between Transmissions tcsh 1.0 - μs
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 23) tdh 15 - ns
CCLK Falling to CDOUT Stable tpd -50ns
Rise Time of CDOUT tr1 -25ns
Fall Time of CDOUT tf1 -25ns
Rise Time of CCLK and CDIN (Note 24) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 24) tf2 - 100 ns
CS
CCLK
CDIN
CDOUT
RST tsrs
tscl
tsch
tcss tr2
tf2
tcsh
tdsu tdh
MSB
MSB
tpd
Figure 8. Control Port Timing - SPI Format
DS646F2 25
CS42438
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Notes: 25. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to th e DAC an d AUX por t, and a
1 kHz, -1 dB analog input to the ADC port sample d at the highest Fs for each spee d mode. DAC outputs
are open, unless otherwise specified.
26. IDT measured with no external loading on pin 2 (SDA).
27. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the c apacitance will also
increase the PSRR.
28. Power-Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input.
29. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due
to typical leakage through the electrolytic de-coupling capacitors.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Notes: 30. See “Digital I/O Pin Characteri stics” on page 8 for serial and control port power rails.
Parameters Symbol Min Typ Max Units
Normal Operation (Note 25)
Power Supply Curren t VA = 5.0 V
VLS = VLC = VD = 3.3 V
(Note 26)
IA
IDT
-
-
80
60.6
-
-
mA
mA
Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 600 850 mW
Power Supply Rejection Ratio 1 kHz
(Note 27) 60 Hz PSRR -
-60
40 -
-dB
dB
Power-Down Mod e (Note 28)
Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 1.25 - mW
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 29)
-
-
-
0.5•VA
23
-
-
-
10
V
kΩ
μA
FILT+ Nominal Voltage - VA - V
Parameters (Note 30) Symbol Min Typ Max Units
High-Level Output Voltage at Io=2 mA Serial Port
Control Port VOH
VLS-1.0
VLC-1.0 -
--
-V
V
Low-Level Output Voltage at Io=2 mA Serial Port
Control Port VOL
-
--
-0.4
0.4 V
V
High-Level Input Voltage Serial Port
Control Port VIH
0.7xVLS
0.7xVLC -
--
-V
V
Low-Level In put Voltage Serial Port
Control Port VIL -
--
-0.2xVLS
0.2xVLC V
V
Leakage Current Iin --±10μA
Input Capacitance (Note 22 ) - - 10 pF
26 DS646F2
CS42438
5. APPLICATIONS
5.1 Overview
The CS42438 is a highly integr ated mixed signal 24-bi t audio CODEC comprised of 6 analog-to-dig ital con-
verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)
also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-
ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass
filters, and an on-chip voltage reference,.
The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multi-
plexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an additional
two channels of PCM data on the ADC_SDOUT da ta line in the TDM digital interface form at. See “AUX Port
Digital Interface Formats” on page 34 for details.
The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined automatically base d on the MCLK frequ ency setting. Single-Spee d Mode (SSM) supports in-
put sample rates up to 50 kHz and uses a 128 x oversamp ling ratio. Dou ble-Speed Mo de (DSM) su pports
input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is
only supported in the I²S, Left-Justified, Right-Justified interface formats. QSM is not supported for the
ADC). Note: QSM is only available in Software Mode (see “System Clocking” on page 33 for details).
All functions can be configured through software via a serial control port operable in SPI Mode or in I²C
Mode. A Hardware, Stand-Alone Mode is also available, allowing configuration of the CODEC on a more
limited basis. See Table 2 for the default configuration in Hardware Mode.
Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42438 in
Software and Hardware Mode, respectively. See “Register Description” on page 41 for the default register
settings and options in Software Mode.
Hardware Mode Feature Summary
Function Default Configuration Hardware Control Note
Power Down ADC All ADC’s are enabled - -
Power Down DAC All DAC’s are enabled - -
Power Down Device Device is powered up - -
MCLK Frequency Select Selectable between 256Fs and
512Fs “MFREQ” pin 3 see Section 5.4
Freeze Control N/A - -
AUX Serial Port Interface Format Left-Justified - -
ADC1/ADC2 High Pass Filter Freeze High Pass Filter is always
enabled --
ADC3 High Pass Filter Freeze High Pass Filter can be
enabled/disabled “ADC3_HPF” pin 4 see Section 5.2.5
DAC De-Emphasis No De-Emphasis applied - -
ADC1/ADC2 Single-Ended Mode Disabled - -
ADC3 Single-Ended Mo de Selectable between Differential
and Single-Ended “ADC_SDOUT/
ADC3_SINGLE” pin 13 see Section 5.2.2
AIN5 Multiplexer Selects between AIN5A and
AIN5B when ADC3 in Single-
Ended Mode “AIN5_MUX” pin 1 see Section 5.2.2
Table 2. Hardware Configurable Settings
DS646F2 27
CS42438
5.2 Analog Inputs
5.2.1 Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs in tern ally bia sed to VQ, appr oxima tely VA/2.
Figure 9 on page 28 shows the full-scale analog input levels. The CS42438 also accommodates single-
ended signals on all inputs, AIN1-AIN6. See “ADC Input Filter” on page 50 for the recommended input
filters.
5.2.1.1 Hardware Mode
AIN Volume Control and ADC Ove rflow status are no t acce ssible in Har dware Mod e. Single-end ed op er-
ation is only supporte d fo r A DC3 . See Section 5.2.2.
5.2.1.2 Software Mode
For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the register “ADC
Control & DAC De-Emphasis (Address 05h)” on page 44 must be set appropriately (see Figure 21 on
page 50 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume
Control (Address 1 1h-16h)” on page 48. The ADC output data is in 2’s complement b inary forma t. For in-
puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-
spectively, and cause the ADC Ov erflow bit in the register “Status (Address 19h) (Read Only)” on page 49
to be set to a ‘1’.
AIN6 Multiplexer Selects between AIN6A and
AIN6B when ADC3 in Single-
Ended Mode “AIN6_MUX” pin 2 see Section 5.2.2
DAC Volume Control/Mute/Invert All DAC Volume = 0 dB, un-
muted, not inverted --
ADC Volume Control All ADC Volume = 0 dB - -
DAC Soft Ramp/Zero Cross Immediate Change - -
ADC Soft Ramp/Zero Cross Immediate Change - -
DAC Auto-Mute Enabled - -
Status Interrupt N/A - -
Hardware Mode Feature Summary
Function Default Configuration Hardware Control Note
Table 2. Hardware Configurable Settings (Continued)
28 DS646F2
CS42438
5.2.2 ADC3 Analog Input
ADC3 accommodates differential as well as single-ended inputs. In Single-End ed Mode, an internal MUX
selects from up to four single-ended inputs.
Full-Scale Differential Input Level =
(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
AINx+
AINx-
3.9 V
2.5 V
1.1 V
5.0 V
3.9 V
2.5 V
1.1 V
VA
Figure 9. Full-Scale Input
AIN5
+
-
AIN5_MUX
VQ
AIN6_MUX
VQ
ADC3
Single-E nded Input Filter
Single-Ended Input Filter
Single-Ende d Inp ut Filter
Single-Ended Input Filter
Differential
Input Filter
50
49
52
51
ADC3 SINGLE
Differential
Input Filter
AIN5A
AIN5B
AIN5+/-
AIN6+/-
AIN6A
AIN6B
1
0
1
0
1
0
0
1
AIN6
+
-
1
0
0
1
Figure 10. ADC3 Input Topology
DS646F2 29
CS42438
5.2.3 Hardware Mode
Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup.
Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 for ADC3 set-up options.
Refer to Figure 10 on page 28 for the internal ADC3 analog input topology.
5.2.4 Software Mode
Single-Ended Mode is selecte d using the ADC3_SINGL E bit. Analog input selection is then made via the
AINx_MUX bits. See register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44 for all bit se-
lections. Refer to Figure 12 on page 32 for the intern al ADC3 analog input topology.
5.2.5 High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the o utpu t of the decim ation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS42438 with the high-pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the sto red DC offset.
5.2.5.1 Hardware Mode
The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode. The high pass
filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.
5.2.5.2 Software Mode
The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3 can
be independently enabled a nd disabled. Th e high-pass filters are control led using the HPF_FREEZE
bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44.
Configuration Setting
AIN5 Input Selection
ADC_SDOUT
(pin 13) AIN5_MUX
(pin 1)
47 kΩ Pull-down X Differential Input (pins 50 & 49)
47 kΩ Pull-up Low AIN5A Input (pin 50)
47 kΩ Pull-up High AIN5B Input (pin 49)
Table 3. AIN5 Analog Input Selection
Configuration Setting
AIN6 Input Selection
ADC_SDOUT
(pin 13) AIN6_MUX
(pin 2)
47 kΩ Pull-down X Differential Input (pins 52 & 51)
47 kΩ Pull-up Low AIN5A Input (pin 52)
47 kΩ Pull-up High AIN5B Input (pin 51)
Table 4. AIN6 Analog Input Selection
30 DS646F2
CS42438
5.3 Analog Outputs
5.3.1 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 311. The CS42438
enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma
modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog
and analog-to-digital converters and switched-capacitor low-pass filters are powered down.
The device remains in the power-down state until the RST pin is brought high. The control port is acces-
sible once RST is high, and the desired register settings can be loaded per the interface descriptions in
the “Control Port Description and Timing ” on page 35. In Hardware Mode operation, the Hardware Mode
pins must be set up before RST is brought high. All features will default to the Hardware Mode defaults
as listed in Table 2.
VQ will quickly charge to VA/2 upon initial power up. Once MCLK is valid and the PDN bit is set to ‘0’b,
the internal voltage reference, FILT+, will ramp up to approximately VA. Power is applied to the D/A con-
verters and switched-capacitor filters, and the analog outputs are clamped to the quiescent volta ge , VQ.
Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK
frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
5.3.2 Line-Level Outputs and Filtering
The CS42438 contai ns on-chip buffer amplifiers ca pable of producing line-leve l differential as well as sin-
gle-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approxi-
mately VQ.
The delta-sigma conve rsion process produces high- frequency noise beyo nd the audio passban d, most of
which is removed by the on-chi p analog filters. The remaining out-of-ban d noise can be a ttenuated using
an off-chip low-pass filter.
See “DAC Output Filter” on page 53 for recommended output filter. The active filter configuration accounts
for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a
passive filter conf igu ratio n wh ich minim ize s cos ts an d th e nu m be r of compo ne n ts.
Figure 12 shows th e full-scale analog output levels. All outputs are internally biased to VQ, appr oximately
VA/2.
DS646F2 31
CS42438
No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Control Port
Accessed
Control Port
Access Detected ?
Valid MC L K
Applied? Valid MCLK
Applied?
No
PDN bit = '1'b?
Sub-C loc ks A p p lied
1. LRCK valid.
2. SCLK valid.
3. Audio sa mples
processed.
Valid
MCLK/LRCK
Ratio?
No
YesYes
No
YesNo
Yes
No
Yes
Yes
No
Norm al O p eratio n
1. VQ = VA/2.
2. Aout bias = VA /2.
3. Audio signal gener ate d p er reg ister setting s.
Analog Output Freeze
1. VQ = VA/2.
2. Aout bias = VA/2 + last audio sample.
3. No audio sign al ge nerate d.
Analog Output Mute
1. VQ = VA/2.
2. Aout bias = VA/2.
3. No audio signal ge nerate d.
ERRO R: MC LK /LR CK ratio ch ang e ERROR: MCLK removed
RST = Low
ERROR: Power removed
PDN bit set
to '1'b
Software Mode
Registers setup to
desired settings.
Hardware Mo de
H/W pin s setu p to
desired settings.
RST = Low?
2000 LRC K delay
Power-Up
1. VQ = VA/2.
2. Aout bias = VQ.
Power-Down
1. VQ = VA/2.
2. Aout bias = Hi-Z .
3. No audio signal gen er ated.
4. Control Port Registers retain
settings.
Power-Down (Power Applied)
1. VQ = VA/2.
2. Aout = H I-Z.
3. No audio signa l gene ra ted .
4. Control P ort R egiste rs r eset
to default.
Figure 11. Audio Output Initialization Flow Chart
32 DS646F2
CS42438
5.3.3 Digital Volume Control
5.3.3.1 Hardware Mode
DAC Volume Control and Mute are not accessible in Hardware Mode.
5.3.3.2 Software Mode
Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to
-127.5 dB attenuation with 0.5 dB resolution. See “AOUTX Volume Control (Addresses 08h- 0Fh)” on
page 47. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate con-
trolled by the SZC[1:0] bits in the Digital Volume Control register. See “Transition Control (Address 06h)”
on page 45.
Each output can be independently muted via mute control bits in the register “DAC Channel Mute (Ad-
dress 07h)” on page 47. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its
maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the corresponding DAC returns to
the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the
rate specified by the SZC[1:0] bits.
5.3.4 De-Emphasis Filter
The CS42438 includes on-chi p digital de-emphasis op timized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 13. The de-emphasis feature is included to accommodate audio recordings
that utilize 50/15 μs pre-emphasis equalization as a means of noise reduction.
De-emphasis is only available in Single-Speed Mode. Please see “DAC De-Emphasis Control
(DAC_DEM)” on page 44 for de-emphasis control.
AOUTx+
AOUTx-
Full-Scale Differential Output Level =
(AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS
4.125 V
2.5 V
0.875 V
5.0 V
4.125 V
2.5 V
0.875 V
VA
Figure 12. Full-Scale Output
DS646F2 33
CS42438
5.4 System Clocking
The CODEC serial au d io inte r face ports operat e as a sla ve an d ac c ep t ex te rn ally ge n er at ed c lock s.
The CODEC requires exter nal gene ratio n of the ma ster clo ck (MCLK). The freq uency of this clock must be
an integer multiple of, and synchron ous with, the system sample rate, Fs.
5.4.1 Hardware Mode
The allowable ratio s include 256Fs and 51 2Fs in Single-Speed Mode and 256Fs in Doub le-Speed Mode.
The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 5 for the required frequen-
cy range.
5.4.2 Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFREQ[2:0])” on page 43.
5.5 CODEC Digital Interface
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with varying
bit depths from 16 to 32 as shown in . Data is clocked out of the ADC on the falling edge of SCLK and
clocked into the DAC on the rising edge.
TDM is the only interface supported in Hardware and Software Mode.
5.5.1 TDM
TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring
after a a n FS rising edge. All dat a is valid on the rising edge of SCLK. The AIN1 MSB is tr ansmitted early,
but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling
edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot.
Valid data lengths are 16, 18 , 20 , or 24 .
SCLK must operate at 256Fs. FS iden tifies the sta rt of a new fram e and is equal to the sample rate, Fs.
Ratio (xFs)
MFREQ Description SSM DSM QSM
01.5360 MHz to 12.8000 MHz 256 N/A N/A
12.0480 MHz to 25.6000 MHz 512 256 N/A
Table 5. MCLK Frequency Settings
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183kHz 10.61kHz
Figure 13. De-Emphasis Curve
34 DS646F2
CS42438
FS is sampled as valid on the rising SCLK edge precedi ng the most significan t bit of the first data sample
and must be held valid for at least 1 SCLK period.
Note: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
5.5.2 I/O Channel Allocation
5.6 AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate
at 64xFs, where F s is equal to the ADC sa mple rat e (FS on th e TDM inte rface ). If the AUX_ SDIN sign al is
not being used, it should be tied to AGND via a pull-down resistor.
5.6.1 Hardware Mode
The AUX port will only operate in the Left-Justified digital interface format and supports bit depths ranging
from 16 to 24 bits (see Figure 18 on page 36 for timing relationship between AUX_LRCK and
AUX_SCLK).
5.6.2 Software Mode
The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Miscellaneous Control (Ad-
dress 04h)” on page 43.
5.6.3 I²S
Digital Input/Output Interface
Format Analog Output/Input Channel Allocation
from/to Digital I/O
DAC_SDIN TDM AOUT 1,2,3,4,5,6,7,8
ADC_SDOUT TDM ,5,6AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)
Table 6. Serial Audio Interface Channel Allo cations
SCLK
FS 256 clks
Bit or Word Wide
AOUT6
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB
DAC_SDIN AOUT1 AOUT4AOUT2 AOUT5AOUT3
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
AOUT8
LSBMSB LSBMSB
AOUT7
32 clks 32 clks
MSB
LSB
AIN6
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB
ADC_SDOUT AIN1 AIN4AIN2 AIN5AIN3
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
AUX2
LSBMSB LSBMSB
AUX1
32 clks 32 clks
MSB
Figure 14. TDM Serial Audio Format
AUX_LRCK
AUX_SCLK
MSB LSB MSB LSB
AUX1
Left Channel Right Channel
AUX_SDIN
AUX2
MSB
Figure 15. AUX I²S Format
DS646F2 35
CS42438
5.6.4 Left-Justified
5.7 Control Port Description and Timing
The control port is used to access the registers, in Software Mode, allowing the CS42438 to be configured
for the desired operational modes and formats. The operation of the control port may be completely asyn-
chronous with respect to the audio sample rates. However, to avoid potential interference problems, the
control port pins should remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS42438 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
5.7.1 SPI Mode
In SPI Mode, CS is the CS42438 chip-select signal, CCLK is the control port bit clock (input into the
CS42438 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.
Figure 17 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulle d high or low with a 47 kΩ resistor, if desired.
There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
To read a reg ister , the M AP ha s to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not,
as desired. To begin a r ead, bring CS low, send out the chip address an d set the read/write bit (R/ W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively.
AUX_LRCK
AUX_SCLK
MSB LSB MSB LSB
AUX1
Left Channel Right Channel
AUX_SDIN
AUX2
MSB
Figure 16. AUX Left-Justified Format
36 DS646F2
CS42438
5.7.2 I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the tw o le ast-significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS42438 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop c ondition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42438 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42438,
the chip address field, which is the first byte sent to the CS42438, should match 10010 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Addr ess Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. Th e ACK bit is output from the CS42438 after each input byte is read, and is input to the
CS42438 from the microcontroller after each transmitted byte.
MAP
MSB LSB
DATA
byte 1 byte n
R/W R/W
ADDRESS
CHIP
ADDRESS
CHIP
CDIN
CCLK
CS
CDOUT MSB LSB MSB LSB
1001111
1001111
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 17. Control Port Timing in SPI Mode
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK STOP
ACKACKACK
1 0 0 1 0 AD1 AD0 0
SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
26
DATA +n
Figure 18. Control Port Timing, I²C Write
DS646F2 37
CS42438
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 19, the write operation is aborted after the ackn owledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, conte nts of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
5.8 Recommended Power-Up Sequence
5.8.1 Hardware Mode
1. Hold RST low until the po wer supply, clocks and hardware control pins are stable. In this state, the
control port is reset to its default settings and VQ will remain low.
2. Bring RST high. The device will initially be in a low power state with VQ low.
3. The device will initiate the Hardware Mode power up sequence. All features will default to the
Hardware Mode defaults as listed in Table 2 on page 26 according to the Hardware Mode control
pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.
4. Following approximately 2000 sample periods, the device is initialized and ready for normal operation.
Note: During the Hardware Mode power-up sequence, th ere must be no transitions on any of the hard-
ware control pins.
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 AD1 AD0 0
SDA 1 0 0 1 0 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 19. Control Port Timing, I²C Read
38 DS646F2
CS42438
5.8.2 Software Mode
1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will initially be in a low power state with VQ low. All features will default as
described in the “Register Quick Reference” on page 39.
3. Perform a write operation to the Power Control register (“Power Control (Address 02h)” o n pa ge 42) to
set bit 0 to a ‘1’b. This will place the device in a power down state.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Mute all DACs. Muting the DACs suppresses any noise associated with the CODEC's first initialization
after power is applied.
6. Set the PDN bit in the power control register to ‘0’b .Following approximately 2000 LRCK cycles, the de-
vice is initialized and ready for normal operation.
7. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and th en unmute th e DACs.
8. Normal operation begins.
5.9 Reset and Power-Up
It is recommende d that reset be activated if the analog or digital supp lies drop below the re commended op-
erating condition to prevent power-glitch-related issues.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 400 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
5.10 Power Supply, Grounding, and PCB Layout
As with any high-resolution conve rter, the CS4243 8 require s careful attention to po wer supply and ground-
ing arrangements if its potential performance is to be realized. Figures 1 and 2 show the recommended
power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be
run from the system logic supply.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommend ed. Decoupling capacitor s should be as near to the pins of the CS42438 as pos-
sible. The low value ceramic cap acitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42438 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ pins in order to avoid unwanted co upling into the modulators. The FILT+ and
VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from
FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and power supply
arrangements.
For optimal heat dissipation from the package, it is recommended that the area directly under the part be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back-
side ground is also recommended.
DS646F2 39
CS42438
6. REGISTER QUICK REFERENCE
Software Mode register defaults are as shown. Note: The default value in all “Reserved” registers must be pre-
served.
Addr Function 76543210
01h ID Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0
p41 default 0 0 0 0 0 0 0 1
02h Power Con-
trol PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN
p42 default 0 0 0 0 0 0 0 0
03h Functional
Mode Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved
p43 default 1 1 1 1 0 0 0 0
04h Misc Control FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved
p43 default 0 0 1 1 0 110
05h ADC Control
(w/DAC_DEM) ADC1-2_HPF
FREEZE ADC3_HPF
FREEZE DAC_DEM ADC1
SINGLE ADC2
SINGLE ADC3
SINGLE AIN5_MUX AIN6_MUX
p44 default 0 0 0 0 0 0 0 0
06h Transition
Control DAC_SNG
VOL DAC_SZC1 DAC_SZC0 AMUTE MUTE
ADC_SP ADC_SNG
VOL ADC_SZC1 ADC_SZC0
p45 default 0 0 0 1 0 0 0 0
07h Channel
Mute AOUT8 MUTE AOUT7
MUTE AOUT6
MUTE AOUT5
MUTE AOUT4
MUTE AOUT3
MUTE AOUT2
MUTE AOUT1
MUTE
p47 default 0 0 0 0 0 0 0 0
08h Vol. Control
AOUT1 AOUT1
VOL7 AOUT1
VOL6 AOUT1
VOL5 AOUT1
VOL4 AOUT1
VOL3 AOUT1
VOL2 AOUT1
VOL1 AOUT1
VOL0
p47 default 0 0 0 0 0 0 0 0
09h Vol. Control
AOUT2 AOUT2
VOL7 AOUT2
VOL6 AOUT2
VOL5 AOUT2
VOL4 AOUT2
VOL3 AOUT2
VOL2 AOUT2
VOL1 AOUT2
VOL0
p47 default 0 0 0 0 0 0 0 0
0Ah Vol. Control
AOUT3 AOUT3
VOL7 AOUT3
VOL6 AOUT3
VOL5 AOUT3
VOL4 AOUT3
VOL3 AOUT3
VOL2 AOUT3
VOL1 AOUT3
VOL0
p47 default 0 0 0 0 0 0 0 0
0Bh Vol. Control
AOUT4 AOUT4
VOL7 AOUT4
VOL6 AOUT4
VOL5 AOUT4
VOL4 AOUT4
VOL3 AOUT4
VOL2 AOUT4
VOL1 AOUT4
VOL0
p47 default 0 0 0 0 0 0 0 0
0Ch Vol. Control
AOUT5 AOUT5
VOL7 AOUT5
VOL6 AOUT5
VOL5 AOUT5
VOL4 AOUT5
VOL3 AOUT5
VOL2 AOUT5
VOL1 AOUT5
VOL0
p47 default 0 0 0 0 0 0 0 0
0Dh Vol. Control
AOUT6 AOUT6
VOL7 AOUT6
VOL6 AOUT6
VOL5 AOUT6
VOL4 AOUT6
VOL3 AOUT6
VOL2 AOUT6
VOL1 AOUT6
VOL0
p47 default 0 0 0 0 0 0 0 0
0Eh Vol. Control
AOUT7 AOUT7
VOL7 AOUT7
VOL6 AOUT7
VOL5 AOUT7
VOL4 AOUT7
VOL3 AOUT7
VOL2 AOUT7
VOL1 AOUT7
VOL0
p47 default 0 0 0 0 0 0 0 0
0Fh Vol. Control
AOUT8 AOUT8
VOL7 AOUT8
VOL6 AOUT8
VOL5 AOUT8
VOL4 AOUT8
VOL3 AOUT8
VOL2 AOUT8
VOL1 AOUT8
VOL0
p47 default 0 0 0 0 0 0 0 0
10h DAC Chan-
nel Invert INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1
p48 default 0 0 0 0 0 0 0 0
40 DS646F2
CS42438
11h Vol. Control
AIN1 AIN1
VOL7 AIN1
VOL6 AIN1
VOL5 AIN1
VOL4 AIN1
VOL3 AIN1
VOL2 AIN1
VOL1 AIN1
VOL0
p47 default 0 0 0 0 0 0 0 0
12h Vol. Control
AIN2 AIN2
VOL7 AIN2
VOL6 AIN2
VOL5 AIN2
VOL4 AIN2
VOL3 AIN2
VOL2 AIN2
VOL1 AIN2
VOL0
p48 default 0 0 0 0 0 0 0 0
13h Vol. Control
AIN3 AIN3
VOL7 AIN3
VOL6 AIN3
VOL5 AIN3
VOL4 AIN3
VOL3 AIN3
VOL2 AIN3
VOL1 AIN3
VOL0
p47 default 0 0 0 0 0 0 0 0
14h Vol. Control
AIN4 AIN4
VOL7 AIN4
VOL6 AIN4
VOL5 AIN4
VOL4 AIN4
VOL3 AIN4
VOL2 AIN4
VOL1 AIN4
VOL0
p48 default 0 0 0 0 0 0 0 0
15h Vol. Control
AIN5 AIN5
VOL7 AIN5
VOL6 AIN5
VOL5 AIN5
VOL4 AIN5
VOL3 AIN5
VOL2 AIN5
VOL1 AIN5
VOL0
p47 default 0 0 0 0 0 0 0 0
16h Vol. Control
AIN6 AIN6
VOL7 AIN6
VOL6 AIN6
VOL5 AIN6
VOL4 AIN6
VOL3 AIN6
VOL2 AIN6
VOL1 AIN6
VOL0
p48 default 0 0 0 0 0 0 0 0
17h ADC Chan-
nel Invert Reserved Reserved INV_A6 INV_A5 INV_A4 INV_A3 INV_A2 INV_A1
p48 default 0 0 0 0 0 0 0 0
18h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 0 0 0 0 0 0 0 0
19h Status Reserved Reserved Reserved Reserved CLK
Error ADC3
OVFL ADC2
OVFL ADC1
OVFL
p49 default 0 0 0 X X X X X
1Ah Status Mask Reserved Reserved Reserved Reserved CLK
Error_M ADC3
OVFL_M ADC2
OVFL_M ADC1
OVFL_M
p49 default 0 0 0 0 0 0 0 0
Addr Function 76543210
DS646F2 41
CS42438
7. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read
only. See the following bit-definition tables for bit assignment information. The default state of each bit a fter a power-
up sequence or reset is listed in each bit description.
7.1 Memory Address Pointer (MAP)
Not a register
7.1.1 Increment (INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
7.1.2 Memory Address Pointer (MAP[6:0])
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
7.2 Chip I.D. and Revision Register (Address 01h) (Read Only)
7.2.1 Chip I.D. (CHIP_ID[3:0])
Default = 0000
Function:
I.D. code for the CS42438. Permanently set to 0000.
7.2.2 Chip Revision (REV_ID[3:0])
Default = 0001
Function:
CS42438 revision level. Revision A is coded as 0001.
76543210
INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0
76543210
Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0
42 DS646F2
CS42438
7.3 Power Control (Address 02h)
7.3.1 Power Down ADC Pairs (PDN_ADCX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3 -
AIN5/AIN6) will remain in a reset state.
7.3.2 Power Down DAC Pairs (PDN_DACX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; DAC3
- AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that any change
of these bits b e made while the DACs ar e muted or the power down bit (PDN) is enabled to eliminate the
possibility of audible artifacts.
7.3.3 Power Down (PDN)
Default = 0
0 - Disable
1 - Enable
Function:
The entire device will enter a low-power state when this function is enabled. The contents of the control
registers are retained in this mode.
76543210
PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN
DS646F2 43
CS42438
7.4 Functional Mode (Address 03h)
7.4.1 MCLK Frequency (MFREQ[2:0])
Default = 000
Function:
Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs.
MCLK can be equal to or greater than SCLK.
7.5 MISCELLANEOUS CONTROL (Address 04h)
7.5.1 Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to the channel mutes,
the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the
FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously,
enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
7.5.2 Auxiliary Digital Interface Format (AUX_DIF)
Default = 0
0 - Left Justified
1 - I²S
Function:
This bit selects the digital interface format used for the AUX Serial Port. The required relationship between
the Left/Right clock, serial clock and seria l da t a i s d e fi n e d b y t he D i g i tal In t e r f ace F orma t a nd t h e o ptio n s
are detailed in Figures 17-18.
76543210
Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved
Ratio (xFs)
MFreq2 MFreq1 MFreq0 Description SSM DSM QSM
000
1.0290 MHz to 12.8000 MHz 256 N/A N/A
001
1.5360 MHz to 19.2000 MHz 384 N/A N/A
010
2.0480 MHz to 25.6000 MHz 512 256 N/A
011
3.0720 MHz to 38.4000 MHz 768 384 N/A
1XX
4.0960 MHz to 51.2000 MHz 1024 512 256
Table 7. MCLK Frequency Settings
76543210
FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved
44 DS646F2
CS42438
7.6 ADC Control & DAC De-Emphasis (Address 05h)
7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset
value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter
Characteristics” on page 16.
7.6.2 A DC3 High Pass Filter Freeze (ADC3_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will
be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteris-
tics” on page 16.
7.6.3 D AC De-Emphasis Control (DAC_DEM)
Default = 0
0 - No De-Emphasis
1 - De-Emphasis Enabled (Auto-Detect Fs)
Function:
Enables the digital filter to maintain the standard 15μs/50μs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of
this register setting, at any other sample rate.
7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC1
1 - Enabled; Single-Ended input to ADC1
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. A
+6 dB digital gain is autom atically applied to the serial audio data of ADC1. The nega tive leg must be driv-
en to the common mode of the ADC. See Figure 21 on page 50 for a graphical description.
7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC2
1 - Enabled; Single-Ended input to ADC2
76543210
ADC1-2_HPF
FREEZE ADC3_HPF
FREEZE DAC_DEM ADC1
SINGLE ADC2
SINGLE ADC3
SINGLE AIN5_MUX AIN6_MUX
DS646F2 45
CS42438
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. A
+6 dB digital gain is automatically applied to the serial au dio data of ADC2. The negative leg must be driv-
en to the common mode of the ADC. See Figure 21 on page 50 for a graphical description.
7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC
1 - Enabled; Single-Ended input to ADC
Function:
When disabled, th is bit removes the 4:2 multiplex er from the signal path of ADC3 allowing a dif ferential
input. When enable d, this bit allows the u ser to choose b etween four sing le-ended inputs to ADC3, using
the AIN5_MUX and AIN6_MUX bits. See Figure 12 on page 32 and Figure 21 on page 50 for graphical
descriptions.
7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX)
Default = 0
0 - Single-Ended In put AIN5A
1 - Single-Ended In put AIN5B
Function:
ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit
selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in Sing le-Ended Mode. This bit
is ignored when the ADC3_SINGLE bit is disabled. See Figur e 12 on page 32 for a graphical description.
7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX)
Default = 0
0 - Single-Ended In put AIN6A
1 - Single-Ended In put AIN6B
Function:
ADC3 can accept a single-ended inpu t signal when th e ADC3 SINGLE bit is e nabled. The AIN6 _MUX bit
selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in Sing le-Ended Mode. This bit
is ignored when the ADC3_SINGLE bit is disabled. See Figur e 12 on page 32 for a graphical description.
7.7 Transition Control (Address 06h)
7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL)
Default = 0
Function:
76543 210
DAC_SNGVOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNGVOL ADC_SZC1 ADC_SZC0
46 DS646F2
CS42438
The individual channel volume levels are independently controlled by their respective Volume Control reg-
isters when this function is disabled. When enabled, the volume on all channels is determined by the
AOUT1 and AIN1 Volume Control regi ster and the other Volume Control registers are ignored.
7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0])
Default = 00
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Ch an ge
When Immediate Change is selected, all volume-level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or mut-
ing, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will oc-
cur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing . The zero cross function is independently monitored
and implemented for each cha nnel.
Soft Ramp
Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implement-
ed by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per
8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain cha nges, attenuation
changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB
level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is inde -
pendently monitored and implemented for each channel.
7.7.3 Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converters of the CS42438 will mute the output following the reception of 8192 con-
secutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection
and muting is done independently for each channel. The quiescent voltage on the output will be retained
during the mute period. The muting function is affected, similar to volume control changes, by the Soft and
Zero Cross bits (SZC[1:0]).
DS646F2 47
CS42438
7.7.4 Mute ADC Serial Port (MUTE ADC_SP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the ADC Serial Port will be muted.
7.8 DAC Channel Mute (Address 07h)
7.8.1 Independent Channel Mute (AOUTX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The respective Digital-to-Analog converter outputs of the CS42438 will mute when enabled. The quies-
cent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero
Cross bits (DAC_SZC[1:0]).
7.9 AOUTX Volume Control (Addresses 08h- 0Fh)
7.9.1 Volume Control (AOUTX_VOL[7:0])
Default = 00h
Function:
The AOUTx Volume Control registers allow in depend en t settin g of the signa l levels in 0.5 dB increments
from 0 dB to -127.5 dB. Volume settings are decoded as show n in Table 8. The volume chang es are im-
plemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0] ). All volume settings less than -
127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel.
76543210
AOUT8_MUTE AOUT7_MUTE AOUT6_MUTE AOUT5_MUTE AOUT4_MUTE AOUT3_MUTE AOUT2_MUTE AOUT1_MUTE
76543210
AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
Binary Code Volume Setting
00000000 0 dB
00101000 -20 dB
01010000 -40 dB
01111000 -60 dB
1011 01 00 -90 dB
Table 8. Example AOUT Volume Settings
48 DS646F2
CS42438
7.10 DAC Channel Invert (Address 10h)
7.10.1 Invert Signal Polarity (INV_AOUTX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
7.11 AINX Volume Control (Address 11h-16h)
7.11.1 AINX Volume Control (AINX_VOL[7:0])
Default = 00h
Function:
The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross
bits (ADC_SZC[1:0]) fr om +24 to -64 dB. Levels are deco ded in two’s complement, as shown in Table 9.
76543210
INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1
76543210
AINx_VOL7 AINx_VOL6 AINx_VOL5 AINx_VOL4 AINx_VOL3 AINx_VOL2 AINx_VOL1 AINx_VOL0
Binary Code Volume Setting
0111 1111 +24 dB
··· ···
0011 0000 +24 dB
··· ···
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1 dB
··· ···
1000 0000 -64 dB
Table 9. Example AIN Volume Settings
DS646F2 49
CS42438
7.12 ADC Channel Invert (Address 17h)
7.12.1 Invert Signal Polarity (INV_AINX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
7.13 Status (Address 19h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occu rred sin c e t he last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
7.13.1 CLOCK ERROR (CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active
during the error condition. See “System Clocking” on page 33 for valid clock ratios.
7.13.2 ADC Overflow (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of the
associated ADC’s.
7.14 Status Mask (Address 1Ah)
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (Address 19h)
(Read Only)” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its oc currence will
affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not
affect status register. The bit positions align with the corresponding bits in the Status register.
76543210
Reserved Reserved INV_AIN6 INV_AIN5 INV_AIN4 INV_AIN3 INV_AIN2 INV_AIN1
765 4 3 2 1 0
Reserved Reserved Reserved Reserved CLK Error ADC3_OVFL ADC2_OVFL ADC1_OVFL
765 4 32 1 0
Reserved Reserved Reserved Reserved CLK Error_M ADC3_OV
FL_M ADC2_OVFL_M ADC1_OVFL_M
50 DS646F2
CS42438
8. EXTERNAL FILTERS
8.1 ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for in put signals which are mul-
tiples of the digital passband frequency (n ×6.144 MHz), where n=0,1,2,... Refer to Figures 20 and 21 for
a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to providing
the optimum source impedance for the modulators. Refer to Figures 22 and 23 for low-cost, low-component-
count passive input filters. The use of capacitors that have a large voltage coefficie nt (such as general-pur-
pose ceramics) must be avoided since these can degrade signal linearity
VA
+
+
-
-
4.7 μF
100 kΩ10 kΩ
100 kΩ
100 kΩ
0.1 μF 100 μF
470 pF
470 pF
C0G
C0G
634 Ω
634 Ω
634 Ω
91 Ω
91 Ω
2700 pF
C0G
332 Ω
AINx+
AINx-
ADC1-3
Figure 20. Single to Differential Active Input Filter
-
+
470 pF
C0G
634 Ω
91 Ω
2700 pF
C0G
4.7 μF
100 kΩ
100 kΩ
100 kΩ
VA
4.7 μF
AIN1+,2+,3+,4+
AIN1-,2-,3-,4-
ADC1-2
ADC3
-
+
470 pF
C0G
634 Ω
91 Ω
2700 pF
C0G
4.7 μF
100 kΩ
100 kΩ
100 kΩ
VA
AIN5A,6A
-
+
470 pF
C0G
634 Ω
91 Ω
2700 pF
C0G
4.7 μF
100 kΩ
100 kΩ
100 kΩ
VA
AIN5B,6B
Figure 21. Single-Ended Active Input Filter
DS646F2 51
CS42438
8.1.1 Passive Input Filter
The passive filter implementation shown in Figure 22 will attenuate any noise energy at 6.144 MHz but
will not provide optimum source impedance for the ADC modulators. Full analog performance will there-
fore not be realized using a passive filter. Figure 22 illustrates the unity gain, passive input filter solution.
In this topology the distortion performance is affected, but the dynamic range performance is not limited.
2700 pF
C0G
10 μF
100 kΩ
150 ΩAIN1+,2+,3+,4+
AIN1-,2-,3-,4-
ADC1-2
4.7 μF
AIN5A,6A
AIN5B,6B
ADC3
2700 pF
C0G
10 μF
100 kΩ
150 Ω
2700 pF
C0G
10 μF
100 kΩ
150 Ω
Figure 22. Passive Input Filter
52 DS646F2
CS42438
8.1.2 Passive Input Filter w/Attenuation
Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale
with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately
2.8 Vpp, or 1 Vrms (most consumer audio line-leve l outputs range from 1.5 to 2 Vrms).
Figure 23 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high input im-
pedance on the analog in puts, the full distortion performance canno t be realized. Also, the resistor divider
circuit will determine the input impedance into the input filter. In the circuit shown in Figure 23, the input
impedance is approximately 5 kΩ. By doubling the resistor values, the input impedance w ill increase to
10 kΩ. However, in this case the distortion performance will drop due to the increase in series resistance
on the analog inputs.
2700 pF
C0G
10 μF
2.5 kΩAIN1+,2+,3+,4+
AIN1-,2-,3-,4-
ADC1-2
4.7 μF
2700 pF
C0G
10 μF
2.5 kΩAIN5A,6A
AIN5B,6B
ADC3
2700 pF
C0G
10 μF
2.5 kΩ
Ω
2.5 k
Ω
2.5 k
Ω2.5 k
Figure 23. Passive Input Filter w/Attenuation
DS646F2 53
CS42438
8.2 DAC Output Filter
The recommended active and passive output filters are shown below.
AOUTx +
AOUTx - -
+
390 pF
C0G 562 Ω
22 μF
4.75 kΩ
1800 pF
C0G
887 Ω
2.94 kΩ
5.49 kΩ
1.65 kΩ
1.87 kΩ22 μF
1200 pF
C0G
5600 pF
C0G
47.5 kΩ
DAC1-4
Figure 24. Active Analog Output Filter
AOUTx+
3.3 µF
C
560 Ω
+
10 kΩRext
Rext
+ 560
C= 4πFSRext
560
DAC1-4
Figure 25. Passive Analog Output Filter
54 DS646F2
CS42438
9. ADC FILTER PLOTS
Figure 26. SSM Stopband Rejection Figure 27. SSM Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (norma lized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)
Amplitude (dB)
Figure 28. SSM Transition Band (Detail) Figure 29. SSM Passband Ripple
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Am p li tu d e (d B)
Figure 30. DSM Stopband Rejection Figure 31. DSM Transition Band
DS646F2 55
CS42438
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr equency (normalized to Fs)
Ampli tude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB
)
Figure 32. DSM Transition Band (Detail) Figure 33. DSM Passband Ripple
56 DS646F2
CS42438
10.DAC FILTER PLOTS
Figure 34. SSM Stopband Rejection Figure 35. SSM Transition Ba nd
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.25
-0. 2
-0.15
-0. 1
-0.05
0
0.05
Frequency (normalized to Fs)
Amplitude dB
Figure 36. SSM Transition Band (detail) Figure 37. SSM Passband Ripple
Figure 38. DSM Stopband Rejection Figure 39. DSM Transition Band
DS646F2 57
CS42438
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0. 2
-0. 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Frequency (normalized to Fs)
Amplitude dB
Figure 40. DSM Transition Band (detail) Figure 41. DSM Passband Ripple
0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
Figure 42. QSM Stopband Rejection Figure 43. QSM Transition Band
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
0.4 0.45 0.5 0.55 0.6 0.65 0.7
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Amplitude (dB)
Frequency(normalized to Fs)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1. 5
-1
-0. 5
0
Frequency (normalized to Fs)
Amplitude dB
Figure 44. QSM Transition Band (detail) Figure 45. QSM Passband Ripple
58 DS646F2
CS42438
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Ran ge is a signal-to-noise ra tio measurement over the specified b and width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the me asure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of th e am p litu de r es po ns e varia tio n f ro m 1 0 Hz to 20 kHz r ela tiv e to th e am p litu de response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert-
er's output with no signal to the input under test and a full-scale signal ap plied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS646F2 59
CS42438
12.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter
Integrated Circuit, by Steven Harris, Steven Green an d Ka Leung. Presented at th e 103rd Convention of th e
Audio Engineering Society, September 1997.
3. Cirrus Logic, A Stereo 1 6-bit Delta-Sigma A/D Converter fo r Digital Audio, by D.R. Welland, B.P. Del Signo-
re, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention
of the Audio Engineering Society, November 1988.
4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and
on Oversampling Delta Sigma ADC's , by Steven Harris. Paper presented at the 87th Convention of the Au-
dio Engineering Society, October 1989.
5. Cirrus Logic, An 18-Bit Dual-Channel Oversamp ling Delta-Sigma A/D Conver ter, with 19-Bit Mono Applica-
tion Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society,
October 1989.
6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven
Harris. Presented at the 93rd Conve ntion of the Audio Engineering Society, October 1992.
7. Cirrus Logic, A Fifth-Orde r Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Ha-
mashita and E.J. Swanson. Paper p resented at the 93rd Convention of the Audio Engineer ing Society, Oc-
tober 1992.
8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, Janu ar y 20 00 .
http://www.semiconductors.philips.com
60 DS646F2
CS42438
13.PACKAGE INFORMATION
13.1 Thermal Characteristics
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- --- 0.096 --- --- 2.45
A1 0.000 --- 0.010 0.00 --- 0.25
B 0.009 --- 0.016 0.22 --- 0.40
D --- 0.519 --- --- 13.20 BSC ---
D1 --- 0.394 --- --- 10.00 BSC ---
E --- 0.519 --- --- 13.20 BSC ---
E1 --- 0.394 --- --- 10.00 BSC ---
e* --- 0.026 --- --- 0.65 BSC ---
L 0.029 0.035 0.041 0.73 0.88 1.03
∝0.00° 4° 7.00° 0.00° 4° 7.00°
* Nominal pin pitch is 0.65 mm
Controlling dimension is mm.
JEDEC Designation: MS022
Parameter Symbol Min Typ Max Units
Junction to Ambient Ther mal Impedance 2 Layer Board
4 Layer Board qJA
θJA
-
-47
38 -
-°C/Watt
°C/Watt
E1
E
D1
D
1
e
L
∝
B
A1
A
52L MQFP PACKAGE DRAWING
DS646F2 61
CS42438
14.ORDERING INFORMATION
15.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS42438 6-in, 8-out, TDM CODEC
for
Surround Sound Apps 52L-MQFP YES Commercia l -10°C to +70°C Rail CS42438-CMZ
Tape & Reel CS42438-CMZR
Automotive -40°C to +105°C Rail CS42438-DMZ
Tape & Reel CS42438-DMZR
CDB42438 CS42438 Evaluation Board - - - - - CDB42438
Revision Changes
F1 Updated temperature and voltage specifications in “Recommended Operating Conditions” on page 13.
Added test conditions to the Analog Input and Analog Output Characteristics tables.
F2 Updated input impedance specification for Differential and Single-Ended Inputs in “Analog Input Characteris-
tics (Commercial)” on page 14 and “Analog Input Characteristics (Automotive)” on page 15.
Contacting Cirrus Logic Support
For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringemen t of patent s or other r ights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any paten ts, mask wo rk rights,
copyrights, tradem arks, trade secrets or oth er intellectual prop erty rights. Cirrus ow ns the copyrights a ssociated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POT ENTIAL RISKS OF DEATH, PERSONAL I NJURY, OR SEVERE P RO P-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERM ITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATI ONS, CUSTO MER AGREES, BY SUCH US E, TO FULL Y INDEMNIF Y CIRRUS, ITS OF FICE RS, DIRE CTORS, EMPLOYEES, DISTRI BUTORS AND
OTHER AGENTS FROM ANY AND ALL LIA BILITY, INCLUDING ATTORNE YS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a registered trademark of Motorola, Inc.
