Preliminary W24L11
128K × 8 CMOS STATIC RAM
Publication Release Date: October 1999
- 1 - Revision A1
GENERAL DESCRIPTION
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bits that
operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
• Low power consumption:
− Active: 144 mW (max.)
• Access time: 70 nS
• Single 3.3V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 2V (min.)
• Packaged in 600 mil DIP, 450 mil SOP,
standard type one, TSOP (8 mm × 20 mm) ,
small type one and TSOP (8 mm × 13.4 mm)
PIN CONFIGURATIONS BLOCK DIAGRAM
V
A8
A9
WE
1
2
3
4
5
24
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16 17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
A13
V
A14
A16
32
31
30
29
A15
CS2
DD
SS
1
32-pin
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O8
A15
A12
A7
A6
A5
A4
V
CS2
WE
A13
A8
DD
A11
A9
NC
A14
A16 VSS
WE
OE
PRECHARGE CKT.
A13 A1A0 A10
CS1
A16
A14
A4
A3
A7
A6
A9
I/O1
:
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A16 Address Inputs
I/O1−I/O8 Data Inputs/Outputs
CS1
, CS2 Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
VDD Power Supply
VSS Ground
NC No Connection
Preliminary W24L11
- 2 -
TRUTH TABLE
CS1
CS2
OE
WE
MODE I/O1
−
I/O8 VDD CURRENT
H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature 0 to 70 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 3.0V to 3.6V; VSS = 0V; TA (°C) = 0 to 70)
PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT
Input Low Voltage VIL - -0.5 +0.6 V
Input High Voltage VIH - +2.0 VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -1 +1 µA
Output Leakage Current ILO VI/O = VSS to VDD,
CS1 = VIH (min.) or
CS2 = VIL (max.) or
OE = VIH (min.) or
WE
= VIL (max.)
-1
+1
µA
Output Low Voltage VOL IOL = +2.1 mA - 0.4 V
Output High Voltage VOH IOH = -1.0 mA 2.2 - V
Operating Power Supply
Current IDD CS1 = VIL (max.) and
CS2 = VIH (min.), I/O = 0 mA,
Cycle = min. Duty = 100%
-
40
mA
Preliminary W24L11
Publication Release Date: October 1999
- 3 - Revision A1
Operating Characteristics, continued
PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT
Standby Power Supply
Current ISB CS1 = VIH (min.) or
CS2 = VIL (max.)
Cycle = min. Duty = 100%
-
1 mA
ISB1 CS1 ≥ VDD -0.2V or LL - 50 µA
CS2 ≤ 0.2V L - 100
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V
CAPACITANCE
(VDD = 3.3 V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
AC characteristics
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC Test Loads and Waveform
90% 90%
5 nS
10%
5 nS 10%
OUTPUT OUTPUT
3.0 V
0 V
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL 1 TTL
CLZ, OLZ, CHZ, OHZ, WHZ, OW
(For T T T T T T )
Preliminary W24L11
- 4 -
AC Characteristics, continued
(VDD = 3.0V to 3.6 V; VSS = 0V; TA (°C) = 0 to 70)
Read Cycle
PARAMETER SYMBOL W24L11-70L/LL UNIT
MIN. MAX.
Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time TACS - 70 nS
Output Enable to Output Valid TAOE - 35 nS
Chip Selection to Output in Low Z TCLZ* 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - nS
Chip Deselection to Output in High Z TCHZ* - 30 nS
Output Disable to Output in High Z TOHZ* - 30 nS
Output Hold from Address Change TOH 10 - nS
∗ These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYMBOL W24L11-70L/LL UNIT
MIN. MAX.
Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 55 - nS
Address Valid to End of Write TAW 55 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 50 - nS
Write Recovery Time
CS1
, CS2,
WE
TWR 0 - nS
Data Valid to End of Write TDW 45 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z TWHZ* - 25 nS
Output Disable to Output in High Z TOHZ* - 25 nS
Output Active from End of Write TOW 5 - nS
∗ These parameters are sampled but not 100% tested
Preliminary W24L11
Publication Release Date: October 1999
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
TRC
TAA
TOH TOH
DOUT
Read Cycle 2
(Chip Select Controlled)
DOUT
CS1
TCLZ
TACS CHZ
T
CS2
Read Cycle 3
(Output Enable Controlled)
Address
TRC
CS1
TAA
OE
TAOE
TOLZ
TOH
TACS
DOUT CLZ
TCHZ
TTOHZ
CS2
Preliminary W24L11
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
TWC
TWR
WE
DOUT
DIN
TWP
TAS
TOHZ (1, 4)
TDW TDH
TAW
CS1 TCW
CS2
Write Cycle 2
(
OE
= VIL Fixed)
WE
DOUT
DIN
TAS
TDH
TWP
TWHZ
DW
T
(2) (3)
TOW
TOH
AW
T
(1, 4)
TCW TWR
Address
TWC
CS1
CS2
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Preliminary W24L11
Publication Release Date: October 1999
- 7 - Revision A1
DATA RETENTION CHARACTERISTICS
(TA (°C) = 0 to 70)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX.
UNIT
VDD for Data Retention VDR CS1 ≥ VDD -0.2V or
CS2 ≤ 0.2V
2.0 - - V
Data Retention Current IDDDR CS1 ≥ VDD -0.2V or
CS2 ≤ 0.2V, VDD = 3V
- - 50 µA
Chip Deselect to Data
Retention Time TCDR See data retention waveform
0 - - nS
Operation Recovery Time TR TRC* - - nS
* Read Cycle Time
DATA RETENTION WAVEFORM
TCDR
-0.2VDD
V
VDD
CS1
TR
CS1
VDR 2V
=
>
=
>
0.9 DD
V0.9 DD
V
CS2 0V CS2 0.2V
<
=<
=
Preliminary W24L11
- 8 -
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
OPERATING
VOLTAGE
(V)
OPERATING
TEMPERATURE
(
°
C)
STANDBY
CURRENT
MAX.(
µ
A)
PACKAGE
W24L11-70LL 70 3.0V to 3.6V 0 to 70 50 600 mil DIP
W24L11S-70LL 70 3.0V to 3.6V 0 to 70 50 450 mil SOP
W24L11T-70LL 70 3.0V to 3.6V 0 to 70 50 Standard type one
TSOP
W24L11Q-70LL 70 3.0V to 3.6V 0 to 70 50 Small type one TSOP
W24L11-70L 70 3.0V to 3.6V 0 to 70 100 600 mil DIP
W24L11S-70L 70 3.0V to 3.6V 0 to 70 100 450 mil SOP
W24L11T-70L 70 3.0V to 3.6V 0 to 70 100 Standard type one
TSOP
W24L11Q-70L 70 3.0V to 3.6V 0 to 70 100 Small type one TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Preliminary W24L11
Publication Release Date: October 1999
- 9 - Revision A1
PACKAGE DIMENSIONS
32-pin P-DIP
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.371.22
0.0540.048
Notes:
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in inches Dimension in mm
A
B
c
D
e
A
L
S
A
A1
2
E
0.050 1.27
0.210 5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.555
0.550
0.545 14.10
13.9713.84
17.02
15.24
14.99 15.49
0.6000.590 0.610
2.29 2.54 2.790.090 0.100 0.110
B1
1
e
E1
a
1.650 1.660 41.91 42.16
0 15
0.085 2.16
0.650
0.630 16.00 16.51
protrusion/intrusion.
4. Dimension B1 does not include dambar
5. Controlling dimension: Inches
150
Seating Plane
eA
2
A
a
c
E
Base Plane
1
A
1e
L
A
S
1
E
D
1
B
B
32
116
17
32-pin SOP Wide Body
1
17
32
16
ye
D
S
Seating Plane
b
A
A
EH
L
L
E
E
1
c
e1
1
e
A2
See Detail F
Detail F
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
.
Notes:
4. Controlling dimension: Inches
5. General appearance spec should be based
on final visual inspection spec.
0.200.15
0.0080.006
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in Inches Dimension in mm
A
b
c
D
e
HE
L
y
A
A
LE
1
2
E
0.012 0.31
0.118 3.00
0.004
0.101
0.014
0.106
0.016
0.111
0.020
2.57
0.36
0.10
2.69
0.41
2.82
0.51
0.047
0.004
010
0.805
0.055
0.817
0.063 1.19
20.45
1.40
20.75
1.60
0.5560.5560.546 14.3814.1213.87
10
0
0.10
11.43
11.30
11.18
0.4500.4450.440
0.58 0.79 0.99
0.023 0.031 0.039
1.12 1.27 1.420.044 0.050 0.056
S0.91
0.036
θ
θ
Preliminary W24L11
- 10 -
Package Dimensions, continued
32-pin Standard Type One TSOP
A
A
A
2
1
L
L1Y
c
E
H
D
D
b
e
M
0.10(0.004)
θ
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
Controlling dimension: Millimeters
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.005 0.006 0.007
0.720 0.724 0.728
0.311 0.315 0.319
0.780 0.787 0.795
0.020
0.016 0.020 0.024
0.031
0.000 0.004
13 5
0.002
1.20
0.05 0.15
1.051.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20 0.23
0.15 0.17
18.40 18.50
8.00 8.10
20.00 20.20
0.50
0.50 0.60
0.80
0.10
3 5
Dimension in mm
θ
__ __ __ __
__ __
__ __
__ __
__
__
__
__
____
1
32-pin Small Type One TSOP
A
AA
2
1
L
L1Y
c
E
H
D
D
b
e
1
Controlling dimension: Millimeters
Min.
Dimension in mm
Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
11.70
13.20
0.675
1.25
0.05 0.15
1.051.00
0.95
0.17
0.14
0.30
0.00
0.20 0.27
0.15 0.16
11.80 11.90
13.40 13.60
0.50
0.50 0.70
0.10
0.049
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.00560.00590.0062
0.461 0.465 0.469
7.90 8.00 8.100.311 0.315 0.319
0.520 0.528 0.536
0.020
0.012 0.020 0.028
0.027
0.000 0.004
0.002
0 3 50 3 5
θ
Dimension in Inches
θ
Preliminary W24L11
Publication Release Date: October 1999
- 11 - Revision A1
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Oct. 1999 - Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
