DRPIC1655X - Lattice Semiconductor

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High Performanc e Configura ble

8-bit RISC Microcontroller

ver 2.03

OVERVIEW

The DRPIC1655X is a low-cost, high per-

formance, 8-bit, fully static soft IP Core, dedi-

cated for operation with fast (typically on-chip)

dual ported memory. The core has been de-

signed with a special concern about low

power consumption.

DRPIC1655X soft core is software-

compatible with the industry standard

PIC16C554 and PIC16C558. It implements an

enhanced Harvard architecture (i.e. sepa-

rate instruction and data memories) with inde-

pendent address and data buses. The 14 bit

program memory and 8-bit dual port data

memory allow instruction fetch and data op-

erations to occur simultaneously. The advan-

tage of this architecture is that instruction

fetch and memory transfers can be over-

lapped by multi stage pipeline, so that the next

instruction can be fetched from program

memory while the current instruction is exe-

cuted with data from the data memory. The

DRPIC1655X architecture is 4 times faster

compared to standard architecture. So most

instructions are executed within 1 system

clock period, except the instructions which

directly operates on program counter PC

(GOTO, CALL, RETURN), this situation

require the pipeline to be cleared and

subsequently refilled. This operation takes

additional one clock cycle.

The DRPIC1655X Microcontroller fits

perfectly in applications ranging from high-

speed automotive and appliance motor control

to low-power remote transmitters/receivers,

pointing devices and telecom processors.

Built-in power save mode make this IP perfect

for applications where power consumption is

critical.

DRPIC1655X is delivered with fully auto-

mated testbench and complete set of tests

allowing easy package validation at each

stage of SoC design flow

CPU FEATURES

● Software compatible with industry standard

PIC16C55X

● Pipelined Harvard architecture 4 times

faster compared to original implementation

● 35 instructions

● 14 bit wide instruction word

● Up to 512 bytes of internal Data Memory

● Up to 64K bytes of Program Memory

● Configurable hardware stack

● Power saving SLEEP mode

● Fully synthesizable, static synchronous

design with no internal tri-states

● Scan test ready

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● Technology independent HDL Source

Code

● 800 MHz virtual clock frequency in a 0.35u

technological process

PERIPHERALS

● Four 8 bit I/O ports

○ Four 8-bit corresponding TRIS registers

○ Interrupt feature on PORTB(7:4) change

● Timer 0

○ 8-bit timer/counter

○ Readable and Writable

○ 8-bit software programmable prescaler

○ Internal or external clock se lect

○ Interrupt generation on timer overflow

○ Edge select for external clock

● Watchdog Timer

○ Configurable Time out period

○ 7-bit software programmable prescaler

○ Dedicated in dep end ent W atchdog Cloc k inpu t

● Interrupt Controller

○ Three individually maskable Interrupt sources

○ External interrupt INT

○ Timer Overflow interrupt

○ Port B[7:4] change interrupt

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

♦ VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

CONFIGURATION

The following parameters of the DRPIC1655X

core can be easy adjusted to requirements of

dedicated application and technology. Con-

figuration of the core can be prepared by ef-

fortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- 1-16

Number of hardware stack

levels - default 8

- up to 512

RAM size - default 256

- up 64 kWords

Program Memory size - default 8k

- used

SLEEP mode - unused

- used / width

WATCHDOG Timer - unused

- used

Timer system - unused

- used

Interrupt system - unused

- used

PORTS A,B,C,D - unused

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

● Single Design license for

○ VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

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are trademarks of their respective owners. http://www.dcd.pl

● One Year license for

○ Encrypted N et lis t only

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ HDL Source to Netlist

○ Single Design to Unlimited Designs

PINS DESCRIPTION

PIN TYPE DESCRIPTION

clk input Global clock

clkwdt input Watchdog clock

por input Global reset Power On Reset

mclr input User reset

prgdata[13:0] input Data bus from program memory

ramdati[7:0] input Data bus from int. data memory

int input External interrupt

t0cki input Timer 0 input

portai[7:0] input Port A input

portbi[7:0] input Port B input

portci[7:0] input Port C input

portdi[7:0] input Port D input

prgaddr[15:0] output Program memory address bus

ramdatao[7:0] output Data bus for internal data memory

ramaddr[8:0] output RAM address bus

ramwe output Data memory write

ramoe output Data memory output enable

sleep output Sleep signal

portao[7:0] output Port A output

portbo[7:0] output Port B output

portco[7:0] output Port C output

portdo[7:0] output Port D output

trisa[7:0] output Data direction pins for Port A

trisb[7:0] output Data direction pins for Port B

trisc[7:0] output Data direction pins for Port C

trisd[7:0] output Data direction pins for Port D

SYMBOL

ramwe

ramoe

portao(7:0)

portbo(7:0)

portai(7:0)

portbi(7:0)

ramdatai(7:0)

t0cki

clk

clkwdt

ramdatao(7:0)

rdaddr(8:0)

wraddr(8:0)

int

trisa(7:0)

trisb(7:0)

sleep

por

mclr

prgdata(13:0) prgaddr(15:0)

portci(7:0)

portdi(7:0)

portco(7:0)

portdo(7:0)

trisc(7:0)

trisd(7:0)

BLOCK DIAGRAM

ALU – Arithmetic Logic Unit performs arithme-

tic and logic operations during execution of an

instruction. This module contains work register

(W) and Status register.

Control Unit – It performs the core synchroni-

zation and data flow control. This module

manages execution of all instructions. Per-

forms decode and control functions for all

other blocks. It contains program counter (PC)

and hardware stack.

Hardware Stack – it’s a configurable hard-

ware stack. The stack space is not a part of

either program or data space and the stack

pointer is not readable or writable. The PC is

pushed onto the stack when CALL instruction

is executed or an interrupt causes a branch.

The stack is popped while RETURN, RETFIE

and RETLW instruction execution. The stack

operates as a circular buffer. This means that

after the stack has been pushed eight times,

the ninth push overwrites the value that was

stored from the first push.

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RAM Controller – It performs interface func-

tions between Data memory and

DRPIC1655X internal logic. It assures correct

Data Memory addressing and data transfers.

The DRPIC1655X supports two addressing

modes: direct or indirect. In Direct Addressing

the 9-bit direct address is computed from

RP(1:0) bits (STATUS) and 7 least significant

bits of instruction word.

Indirect addressing is possible by using the

INDF register. Any instruction using INDF reg-

ister actually accesses data pointed to by the

file select register FSR. Reading INDF register

indirectly will produce 00h. Writing to the INDF

effective 9-bit address is obtained by concate-

nating the IRP bit (STATUS) and the 8-bit

FSR register.

portao

portdo

portco

portbo

ramdatai

clk

ramdatao

RAM

Controller

I/O

Ports

Hardware

Stack

Control

Unit

Interrupt

Controller

int

por

sleep

ramwe

rdaddr

mclr

portai

portbi

Timer 0

t0cki

prgdata

prgaddr

wraddr

Watchdog

Timer

clkwdt

portci

portdi

trisa

trisd

trisc

trisb

ramoe

Interrupt Controller – Interrupt Controller

module is responsible for interrupt manage

system for the external and internal interrupt

sources. It contains interrupt related register

called INTCON. There are three interrupt

sources:

¨ External interrupt INT

¨ TMR0 overflow interrupt

¨ PORTB change interrupt (pins B7:B4)

The interrupt control register INTCON records

individual interrupt requests in flag bits.

A global interrupt enable bit, GIE enables all

unmasked interrupts. Each interrupt source

has an individual enable bit, which can enable

or disable corresponding interrupt.

When an interrupt is responded to, the GIE is

cleared to disable any further interrupt, the

return address is pushed into the stack and

the PC is loaded with 0004h. The interrupt flag

bits must be cleared in software before re-

enabling interrupts.

Timer 0 – Main system’s timer and prescaler.

This timer operates in two modes: 8-bit timer

or 8-bit counter. In the “timer mode”, timer

registers are incremented every 4 CLK peri-

ods. When the prescaler is assigned into the

TIMER prescale ration can be divided by 2, 4

.. 256. In the “counter mode” the timer register

is incremented every falling or rising edge of

T0CKI pin, dependent on T0SE bit in OPTION

Watchdog Timer– it’s a free running timer.

WDT has own clock input separate from sys-

tem clock. It means that the WDT will run

even if the system clock is stopped by execu-

tion of SLEEP instruction. During normal op-

eration, a WDT time-out generates a Watch-

dog reset. If the device is in SLEEP mode the

WDT time-out causes the device to wake-up

and continue with normal operation.

I/O Ports – Block contains DRPIC1655X’s

general purpose I/O ports and data direction

registers (TRIS). The DRPIC1655X has four

8-bit full bi-directional ports PORT A, PORT B,

PORT C, PORT D. Each port’s bit can be indi-

vidually accessed by bit addressable instruc-

tions. Read and write accesses to the I/O port

are performed via their corresponding SFR’s

PORTA, PORTB, PORTC, PORTD. The read-

ing instruction always reads the status of Port

pins. Writing instructions always write into the

Port latches. Each port’s pin has an corre-

sponding bit in TRISA, B, C and D registers.

When the bit of TRIS register is set this

means that the corresponding bit of port is

configured as an input (output drivers are set

into the High Impedance).

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are trademarks of their respective owners. http://www.dcd.pl

OPTIONAL

PERIPHERALS

There are also available an optional pe-

ripherals, not included in presented

DRPIC1655X Microcontroller Core. The op-

tional peripherals, can be implemented in mi-

crocontroller core upon customer request.

● Full duplex UART

● SPI – Master and Slave Serial Peripheral

Interface

○ Supports speeds up ¼ of system clock

○ Mode fault error

○ Write collis ion error

○ Software selectable polarity and phase of se-

rial clock SCK

○ System errors detection

○ Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

○ Interrupt generation

● PWM – Pulse Width Modulation Timer

○ 2 independent 8-bit PWM channels, concate-

nated on one 16-bit PWM channel

○ Software- s elec tab le duty fr om 0% to 10 0% an d

pulse period

○ Software-selectable polarity of output wave-

form

● I2C bus controller - Master

○ 7-bit and 10-b it addres sin g modes

○ NORMAL, FAST, HIGH speeds

○ Multi-master systems supported

○ Clock arbitration and synchronization

○ User defined timings on I2C lines

○ Wide range of system clock frequencies

○ Interrupt generation

● I2C bus controller - Slave

○ NORMAL speed 100 kbs

○ FAST speed 400 kbs

○ HIGH speed 3400 kbs

○ Wide range of system clock frequencies

○ User defined data setup time on I2C lines

○ Interrupt generation

PERFORMANCE

The following tables give a survey about the

Core area and performance in the Program-

mable Logic Devices after Place & Route (all

CPU features and peripherals have been in-

cluded):

Device Speed grade Fmax

ORCA 3T -7 23 MHz

ORCA 4E -3 45 MHz

ispXPGA -5 43 MHz

Core performance in LATTI CE® devic es

Area utilized by the each unit of DRPIC1655X

core in vendor specific technologies is sum-

marized in table below.

Area

Component [LC / PFU] [FFs]

CPU* 514 / 91 267

Timer 0 43 / 9 22

Watchdog Timer 41 / 9 26

I/O Ports 63 / 13 73

Total area 661 / 122 390

*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,

External INT pin Interrupt Controller

Core components area utilization

IMPROVEMENT

Most instruction of DRPIC1655X is exe-

cuted within 1 CLK period, except program

branches that require 2 CLK periods. The ta-

ble below shows sample instructions execu-

tion times:

Mnemonic

operands DRPIC1655X

(CLK cycles) PIC16C554

(CLK cycles) Impr.

ADDWF 1 4 4

ANDWF 1 4 4

RLF 1 4 4

BCF 1 4 4

DECFSZ 1(2)1 4(8)1 4

INCFSZ 1(2)1 4(8)1 4

BTFSC 1(2)1 4(8)1 4

BTFSS 1(2)1 4(8)1 4

CALL 2 8 4

GOTO 2 8 4

RETFIE 2 8 4

RETLW 2 8 4

RETURN 2 8 4

1- number of clock in case that result of opera-

tion is 0.

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are trademarks of their respective owners. http://www.dcd.pl

DFPIC FAMILY OVERVIEW

The family of DCD DFPICXX IP Cores combine a high–performance, low cost, and small compact

size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are dedicated for

use in cost-sensitive consumer products, computer peripherals, office automation, automotive control

systems, security and telecommunication applications.

DCD DFPICXX IP Cores family contains three 8-bit microcontroller Cores to best meet your needs:

DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, and DRPIC1655X single cycle

microcontroller with 14-bit program word. All three microcontroller cores are binary compatible with

widely accepted PIC16C5X and PIC16CXXX. It employ a modified RISC architecture two or four

times faster than the original ones.

The DFPICXXX IP Cores are written in pure VHDL/VERILOG HDL languages which makes them

technologically independent. All of the DFPICXX family members supports a power saving SLEEP

mode and allows the user to configure the watchdog time-out period and a number of hardware stack

levels. DFPICXX can be fully customized according to customer needs.

Design

Program Memory

space

Data Memory

space

Program word

length

Number of

instructions

I/O Ports

Timer 0

Watchdog Timer

Sleep Mode

External

interrupts

Internal

Interrupts

Levels of

hardware stack

Wa ke up on port

pin change

Speed rate

DFPIC165X 2k 128 12 33 24 - - 2 - 2

DFPIC1655X 64k 512 14 35 16 5 1 8 2

DRPIC1655X 64k 512 14 35 32 5 1 8 4

DFPIC family of High Performance Microcontroller Cores

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are trademarks of their respective owners. http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

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