1 A, Low VIN, Low Noise,
CMOS Linear Regulator
Data Sheet ADP1761
Rev. C Document Feedback
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FEATURES
1 A maximum output current
Low input voltage supply range
VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
Noise spectral density
4 nV/√Hz at 10 kHz
3 nV/√Hz at 100 kHz
Low dropout voltage: 30 mV typical at 1 A load
Operating supply current: 4.5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
67 dB typical at 10 kHz at 1 A load
51 dB typical at 100 kHz at 1 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 10 μF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
TYPICAL APPLICATION CIRCUITS
VIN
EN
SS
VREG
VOUT
SENSE
C
OUT
10µF
PG
R
PULL-UP
100kΩ PG
VADJ
GND
REFCAP
C
IN
10µF
ON
OFF
V
OUT
= 1.5V
ADP1761
V
IN
= 1.7V
C
REG
1µF
C
REF
1µF
C
SS
10nF
12919-001
Figure 1. Fixed Output Operation
VIN
EN
SS
VREG
VOUT
SENSE
PG
R
PULL-UP
100kΩ PG
VADJ
GND
REFCAP
C
REG
1µF
C
REF
1µF
R
ADJ
10kΩ
C
SS
10nF
ON
OFF
V
OUT
= 1.5V
ADP1761
V
IN
= 1.7V
C
OUT
10µF
C
IN
10µF
12919-002
Figure 2. Adjustable Output Operation
Table 1. Related Devices
Device
Input
Voltage
Maximum
Current
Fixed/
Adjustable Package
ADP1762 1.10 V to
1.98 V
2 A Fixed/adjustable 16-lead
LFCSP
ADP1763 1.10 V to
1.98 V
3 A Fixed/adjustable 16-lead
LFCSP
ADP1740/
ADP1741
1.6 V to
3.6 V
2 A Fixed/adjustable 16-lead
LFCSP
ADP1752/
ADP1753
1.6 V to
3.6 V
0.8 A Fixed/adjustable 16-lead
LFCSP
ADP1754/
ADP1755
1.6 V to
3.6 V
1.2 A Fixed/adjustable 16-lead
LFCSP
GENERAL DESCRIPTION
The ADP1761 is a low noise, low dropout (LDO) linear regulator.
It is designed to operate from a single input supply with an input
voltage as low as 1.10 V, without the requirement of an external
bias supply to increase efficiency and provide up to 1 A of
output current.
The low 30 mV typical dropout voltage at a 1 A load allows the
ADP1761 to operate with a small headroom while maintaining
regulation and providing better efficiency. The ADP1761 is
optimized for stable operation with small 10 μF ceramic output
capacitors.
The ADP1761 delivers optimal transient performance with
minimal board area.
The ADP1761 is available in fixed output voltages ranging from
0.9 V to 1.5 V. The output of the adjustable output model can
be set from 0.5 V to 1.5 V through an external resistor connected
between VADJ and ground.
The ADP1761 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1761 is available in a small 16-lead LFCSP package for
the smallest footprint solution to meet a variety of applications.
ADP1761 Data Sheet
Rev. C | Page 2 of 18
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Typical Application Circuits ........................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Input and Output Capacitor: Recommended Specifications . 4
Absolute Maximum Ratings ........................................................... 5
Thermal Data ................................................................................ 5
Thermal Resistance/Parameter .................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Soft Start Function ..................................................................... 11
Adjustable Output Voltage ....................................................... 12
Enable Feature ............................................................................ 12
Power-Good (PG) Feature ........................................................ 12
Applications Information ............................................................. 13
Capacitor Selection .................................................................... 13
Undervoltage Lockout ............................................................... 14
Current-Limit and Thermal Overload Protection ................ 14
Thermal Considerations ........................................................... 14
PCB Layout Considerations ..................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/2020—Rev. B to Rev. C
Changes to Thermal Data Section, Thermal
Resistance/Parameter Section, and Table 5 .................................. 5
8/2019—Rev. A to Rev. B
Change to Undervoltage Lockout, Hysteresis Parameter ........... 4
Updated Outline Dimensions ....................................................... 18
9/2016—Rev. 0 to Rev. A
Changes to Figure 23 and Figure 24 ............................................ 11
4/2016—Revision 0: Initial Version
Data Sheet ADP1761
Rev. C | Page 3 of 18
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, ILOAD = 10 mA, CIN = 10 μF, COUT = 10 μF, CREF = 1 μF, CREG = 1 μF, TA = 25°C,
minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE SUPPLY RANGE VIN T
J = −40°C to +125°C 1.10 1.98 V
CURRENT
Operating Supply Current IGND I
LOAD = 0 μA 4.5 8 mA
I
LOAD = 10 mA 4.9 8 mA
I
LOAD = 100 mA 5.5 8.5 mA
I
LOAD = 1 A 7.3 11 mA
Shutdown Current IGND-SD EN = GND 2 μA
TJ = −40°C to +85°C,
VIN = (VOUT + 0.2 V) to 1.98 V
180 μA
TJ = 85°C to 125°C,
VIN = (VOUT + 0.2 V) to 1.98 V
800 μA
OUTPUT NOISE1 OUTNOISE 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 12 μV rms
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V 2 μV rms
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 15 μV rms
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V 2 μV rms
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 21 μV rms
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V 2 μV rms
Noise Spectral Density OUTNSD V
OUT = 0.9 V to 1.5 V, ILOAD = 100 mA
At 10 kHz 4 nV/√Hz
At 100 kHz 3 nV/√Hz
POWER SUPPLY REJECTION RATIO1 PSRR ILOAD = 1 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.5 V 67 dB
100 kHz, VOUT = 1.3 V, VIN = 1.5 V 51 dB
1 MHz, VOUT = 1.3 V, VIN = 1.5 V 41 dB
10 kHz, VOUT = 0.9 V, VIN = 1.1 V 66 dB
100 kHz, VOUT = 0.9 V, VIN = 1.1 V 50 dB
1 MHz, VOUT = 0.9 V, VIN = 1.1 V 35 dB
OUTPUT VOLTAGE
Output Voltage Range TA = 25°C
V
OUT_FIXED 0.9 1.5 V
V
OUT_ADJ 0.5 1.5 V
Fixed Output Voltage Accuracy VOUT I
LOAD = 100 mA, TA = 25°C −0.5 +0.5 %
10 mA < ILOAD < 1 A, VIN = (VOUT + 0.2 V) to
1.98 V, TJ = 0°C to 85°C
−1 +1.5 %
10 mA < ILOAD < 1 A, VIN = (VOUT + 0.2 V) to
1.98 V
−1.5 +1.5 %
ADJUSTABLE PIN CURRENT IADJ T
A = 25°C 49.5 50.0 50.5 μA
V
IN = (VOUT + 0.2 V) to 1.98 V 48.8 50.0 51.0 μA
ADJUSTABLE OUTPUT VOLTAGE GAIN
FACTOR
AD TA = 25°C 3.0
V
IN = (VOUT + 0.2 V) to 1.98 V 2.95 3.055
REGULATION
Line Regulation ∆VOUT/∆VIN V
IN = (VOUT + 0.2 V) to 1.98 V −0.15 +0.15 %/V
Load Regulation2 ∆VOUT/∆IOUT I
LOAD = 10 mA to 1 A 0.25 0.44 %/A
DROPOUT VOLTAGE3 V
DROPOUT I
LOAD = 100 mA, VOUT = 1.2 V 12 23 mV
I
LOAD = 1 A, VOUT = 1.2 V 30 53 mV
START-UP TIME1, 4 TSTART-UP C
SS = 10 nF, VOUT = 1.3 V 0.6 ms
SOFT START CURRENT ISS 1.1 V ≤ VIN ≤ 1.98 V 8 10 12 μA
ADP1761 Data Sheet
Rev. C | Page 4 of 18
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CURRENT-LIMIT THRESHOLD5 I
LIMIT 1.5 2 2.4 A
THERMAL SHUTDOWN
Threshold TSSD T
J rising 150 °C
Hysteresis TSSD-HYS 15 °C
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling PGFALL 1.1 V ≤ VIN ≤ 1.98 V −7.5 %
Rising PGRISE 1.1 V ≤ VIN ≤ 1.98 V −5 %
PG OUTPUT
Output Voltage Low PGLOW 1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA 0.35 V
Leakage Current IPG-LKG 1.1 V ≤ VIN ≤ 1.98 V 0.01 1 μA
Delay1 PGDELAY ENRISING to PGRISING 0.75 ms
PRECISION EN INPUT 1.1 V ≤ VIN ≤ 1.98 V
Logic Input
High ENHIGH 595 625 690 mV
Low ENLOW 550 580 630 mV
Input Logic Hysteresis ENHYS 45 mV
Input Leakage Current IEN-LKG EN = VIN or GND 0.01 1 μA
Input Delay Time tIEN-DLY From EN rising from 0 V to VIN to 0.1 × VOUT 100 μs
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage
Rising UVLORISE T
J = −40°C to +125°C 1.01 1.06 V
Falling UVLOFALL T
J = −40°C to +125°C 0.87 0.93 V
Hysteresis UVLOHYS 80 mV
1 Guaranteed by design and characterization; not production tested.
2 Based on an endpoint calculation using 10 mA and 1 A loads.
3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of the nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CAPACITANCE1 T
A = −40°C to +125°C
Input CIN 7.0 10 μF
Output COUT 7.0 10 μF
Regulator CREG 0.7 1 μF
Reference CREF 0.7 1 μF
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) RESR T
A = −40°C to +125°C
CIN, COUT 0.001 0.5 Ω
CREG, CREF 0.001 0.2 Ω
1 The minimum input and output capacitance must be >7.0 μF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Data Sheet ADP1761
Rev. C | Page 5 of 18
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN to GND −0.3 V to +2.16 V
EN to GND −0.3 V to +3.96 V
VOUT to GND −0.3 V to VIN
SENSE to GND −0.3 V to VIN
VREG to GND −0.3 V to VIN
REFCAP to GND −0.3 V to VIN
VADJ to GND −0.3 V to VIN
SS to GND −0.3 V to VIN
PG to GND −0.3 V to +3.96 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Operating Junction Temperature 125°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1761 can be damaged when the junction
temperature limits are exceeded. The use of appropriate thermal
management techniques is recommended to ensure that the
maximum junction temperature does not exceed the limits shown
in Table 4.
Use the following equation to calculate the junction temperature
(TJ) from the board temperature (TBOARD) or package top
temperature (TTOP)
TJ = TBOARD + (PD × ΨJB)
TJ = TTOP + (PD × ΨJT)
ΨJB is the junction to board thermal characterization parameter
and ΨJT is the junction to top thermal characterization
parameter with units of °C/W.
ΨJB of the package is based on modeling and calculation using a
4-layer board. JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information, states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-
world applications.
THERMAL RESISTANCE/PARAMETER
Values shown in Table 5 are calculated in compliance with
JEDEC standards for thermal reporting. θJA is the natural
convection junction to ambient thermal resistance measured in a
one cubic foot sealed enclosure. θJC is the junction to case thermal
resistance. θJB is the junction to board thermal resistance. ΨJB is
the junction to board thermal characterization parameter. ΨJT is
the junction to top thermal characterization parameter.
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. Thermal
resistance/parameter values may vary, depending on the PCB
material, layout, and environmental conditions.
Table 5. Thermal Resistance/Parameter
Package
Type θJA θ
JB θ
JC-T θ
JC-B Ψ
JB ΨJT Unit
CP-16-221 50.95 29.31 49.53 8.53 29.31 0.3 °C/W
1 Thermal resistance/parameter simulated values are based on a JEDEC 2S2P
thermal test board for ΨJT, ΨJB, θJA and θJB and a JEDEC 1S0P thermal test
board for θJC with four thermal vias. See JEDEC JESD51-12.
ESD CAUTION
ADP1761 Data Sheet
Rev. C | Page 6 of 18
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VIN
VIN
VIN
VIN
VOUT
NOTES
1. THE EXPOSED PAD IS ELECTRICALLY
CONNECTED TO GND. IT IS RECOMMENDED
THAT THIS PAD BE CONNECTED TO A GROUND
PLANE ON THE PCB. THE EXPOSED PAD IS
ON THE BOTTOM OF THE PACKAGE.
SENSE
SS
PG
EN
VOUT
VOUT
VOUT
REFCAP
VREG
GND
VADJ
ADP1761
TOP VIEW
(Not to Scale)
12919-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be
connected to the source supply.
5 REFCAP Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to ground.
6 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect
a load to ground.
7 GND Ground.
8 VADJ Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ
pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating.
9 to 12 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins
must be connected to the load.
13 SENSE Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier.
Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the
load.
14 SS Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms.
15 PG Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown
mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output
voltage, the PG pin immediately transitions low.
16 EN Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For
automatic startup, connect the EN pin to the VIN pin.
EP Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected
to a ground plane on the PCB. The exposed pad is on the bottom of the package.
Data Sheet ADP1761
Rev. C | Page 7 of 18
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.5 V, VOUT = 1.3 V, TA = 25°C, unless otherwise noted.
12919-004
OUTPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1.295
1.297
1.299
1.301
1.303
1.305
–50 –25 0 25 50 75 100 125 150
NO LOAD
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 1A
Figure 4. Output Voltage (VOUT) vs. Junction Temperature
12919-005
1.3015
1.3020
1.3025
1.3030
1.3035
0.01 0.1 1
OUTPUT VOL
T
AGE (V)
LOAD CURRENT (A)
Figure 5. Output Voltage (VOUT) vs. Load Current
12919-006
1.298
1.300
1.302
1.304
1.306
1.308
1.310
1.51.61.71.81.92.0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1A
Figure 6. Output Voltage vs. Input Voltage
0
1
2
3
4
5
6
7
8
9
10
–50 –25 0 25 50 75 100 125 150
GROUND CURRENT (mA)
JUNCTION TEMPERATURE (°C)
NO LOAD
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
12919-007
Figure 7. Ground Current vs. Junction Temperature
0
1
2
3
4
5
6
7
8
0.01 0.1 1
GROUND CURRENT (mA)
LOAD CURRENT (A)
12919-008
Figure 8. Ground Current vs. Load Current
0
1
2
3
4
5
6
7
8
9
1.5 1.6 1.7 1.8 1.9 2.0
GROUND CURRENT (mA)
INPUT VOLTAGE (V)
NO LOAD
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
12919-009
Figure 9. Ground Current vs. Input Voltage
ADP1761 Data Sheet
Rev. C | Page 8 of 18
–20
0
20
40
60
80
100
120
140
160
180
200
–50 –25 0 25 50 75 100 125 150
SHUTDOWN CURRENT (µA)
JUNCTION TEMPERATURE (°C)
V
IN
= 1.5V
V
IN
= 1.7V
V
IN
= 1.9V
V
IN
= 1.6V
V
IN
= 1.8V
V
IN
= 1.98V
12919-010
Figure 10. Shutdown Current vs. Junction Temperature at
Various Input Voltages (VIN)
12919-011
0
5
10
15
20
25
30
35
0.1 1
DROPOUT VOLTAGE (mV)
LOAD (A)
Figure 11. Dropout Voltage vs. Load Current, VOUT = 1.3 V
12919-012
1.10
1.15
1.20
1.25
1.30
1.35
1.2 1.3 1.4 1.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1A
Figure 12. Output Voltage vs. Input Voltage (in Dropout), VOUT = 1.3 V
0
1
2
3
4
5
6
7
8
9
1.11.21.31.41.51.6
GROUND CURRENT (mA)
INPUT VOLTAGE (V)
NO LOAD
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
12919-013
Figure 13. Ground Current vs. Input Voltage (in Dropout), VOUT = 1.3 V
CH1 20.0mV CH2 500mA M4.00µs A CH2 640mA
1
2
T 18.70%
V
OUT
I
LOAD
3A/µs SLEW RATE
12919-014
Figure 14. Load Transient Response, COUT = 10 μF, VIN = 1.7 V, VOUT = 1.3 V
CH1 20.0mV CH2 500mA M4.00µs A CH2 640mA
2
1
T 19.00%
VIN
ILOAD
3A/µs SLEW RATE
12919-015
Figure 15. Load Transient Response, COUT = 47 μF, VIN = 1.7 V, VOUT = 1.3 V
Data Sheet ADP1761
Rev. C | Page 9 of 18
CH1 5.00mV CH2 500mV M2.00µs A CH2 1.68V
2
1
T 17.50%
V
OUT
V
IN
1V/µs SLEW RATE
12919-016
Figure 16. Line Transient Response, Load Current = 1 A,
VIN = 1.5 V to 1.98 V Step, VOUT = 1.3 V
0
2
4
6
8
10
12
14
16
0.1 1
NOISE (µV rms)
LOAD CURRENT (A)
V
OUT
= 1.3V (100Hz TO 100kHz)
V
OUT
= 1.3V (10Hz TO 100kHz)
12919-017
Figure 17. Noise vs. Load Current for Various Output Voltages
0.1
1
10
100
1k
10k
10 100 1k 10k 100k
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
OUT
= 0.9V
V
OUT
= 1.3V
V
OUT
= 1.5V
12919-018
Figure 18. Noise Spectral Density vs. Frequency for Various Output Voltages,
Load Current = 100 mA
12919-019
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
1 10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
IN
= 1.1V
V
IN
= 1.2V
V
IN
= 1.3V
V
IN
= 1.4V
V
IN
= 1.5V
V
IN
= 1.6V
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various VIN,
VOUT = 0.9 V, Load Current = 1 A
12919-020
1 10 100 1k 10k 100k 1M 10M
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
PSRR (dB)
FREQUENCY (Hz)
V
IN
= 1.5V
V
IN
= 1.6V
V
IN
= 1.7V
V
IN
= 1.8V
V
IN
= 1.9V
V
IN
= 1.98V
Figure 20. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various VIN,
VOUT = 1.3 V, Load Current = 1 A
12919-021
1 10 100 1k 10k 100k 1M 10M
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
PSRR (dB)
FREQUENCY (Hz)
V
IN
= 1.7V
V
IN
= 1.8V
V
IN
= 1.9V
V
IN
= 1.98V
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various VIN,
VOUT = 1.5 V, Load Current = 1 A
Data Sheet ADP1761
Rev. C | Page 11 of 18
THEORY OF OPERATION
The ADP1761 is an LDO, low noise linear regulator that uses an
advanced proprietary architecture to achieve high efficiency
regulation. It also provides high PSRR and excellent line and load
transient response using a small 10 F ceramic output capacitor.
The device operates from a 1.10 V to 1.98 V input rail to provide
up to 1 A of output current. Supply current in shutdown mode is
2 μA.
SS BLOCK
REFCAP
SS
PG
SHORT-CIRCUIT,
THERMAL
PROTECTION
INTERNAL
BIAS SUPPLY
ADP1761
VIN
VREG
EN
GND
REFERENCE,
BIAS
VOUT
SENSE
12919-023
Figure 23. Functional Block Diagram, Fixed Output
SS BLOCK
SHORT-CIRCUIT,
THERMAL
PROTECTION
INTERNAL
BIAS SUPPLY
3×
REFCAP
SS
PG
VIN
V
RE
G
VADJ
I
ADJ
EN
GND
VOUT
SENSE
ADP1761
12919-024
Figure 24. Functional Block Diagram, Adjustable Output
Internally, the ADP1761 consists of a reference, an error amplifier,
and a pass device. The output current is delivered via the pass
device, which is controlled by the error amplifier, forming a
negative feedback system that ideally drives the feedback voltage to
equal the reference voltage. If the feedback voltage is lower than
the reference voltage, the negative feedback drives more current,
increasing the output voltage. If the feedback voltage is higher than
the reference voltage, the negative feedback drives less current,
decreasing the output voltage.
The ADP1761 is available in output voltages ranging from 0.9 V to
1.5 V for a fixed output. Contact a local Analog Devices, Inc., sales
representative for other fixed voltage options. The adjustable
output option can be set from 0.5 V to 1.5 V.
The ADP1761 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is high, VOUT
turns on. When EN is low, VOUT turns off. For automatic
startup, tie EN to VIN.
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1761
provides a programmable soft start function. The programmable
soft start is useful for reducing inrush current upon startup and for
providing voltage sequencing. To implement soft start, connect a
small ceramic capacitor from SS to ground. At startup, a 10 μA
current source charges this capacitor. The voltage at SS limits the
ADP1761 start-up output voltage, providing a smooth ramp-up to
the nominal output voltage. To calculate the start-up time for the
fixed output and adjustable output, use the following equations:
tSTART-UP_FIXED = tDELAY + VREF × (CSS/ISS) (1)
tSTART-UP_ADJ = tDELAY + VADJ × (CSS/ISS) (2)
where:
tDELAY is a fixed delay of 100 μs.
VREF is a 0.5 V internal reference for the fixed output model option.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (10 μA).
VADJ is the voltage at the VADJ pin equal to RADJ × IADJ.
TIME (ms)
V
OUT, EN
(V)
–0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
–0.2 0.3 0.8 1.3 1.8
EN
C
SS
= 0nF
C
SS
= 10nF
C
SS
= 22nF
12919-025
Figure 25. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time
–0.5
0
0.5
1.0
1.5
2.0
–0.2 0.3 0.8 1.3 1.8
V
OUT, EN
(V)
TIME (ms)
EN
V
OUT
= 0.5V; C
SS
= 10nF
V
OUT
= 0.5V; C
SS
= 22nF
V
OUT
= 1.5V; C
SS
= 10nF
V
OUT
= 1.5V; C
SS
= 22nF
12919-226
Figure 26. Adjustable VOUT Ramp-Up with External Soft Start Capacitor
(VOUT, EN) vs. Time
ADP1761 Data Sheet
Rev. C | Page 12 of 18
ADJUSTABLE OUTPUT VOLTAGE
The output voltage of the ADP1761 can be set over a 0.5 V to
1.5 V range. Connect a resistor (RADJ) from the VADJ pin to
ground to set the output voltage. To calculate the output
voltage, use the following equation:
VOUT = AD × (RADJ × IADJ) (3)
where:
AD is the gain factor with a typical value of 3.0 between the
VADJ pin and the VOUT pin.
IADJ is the 50.0 μA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1761 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in
Figure 27, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
CH1 200mV CH2 200mV M4.0ms A CH1 768mV
1
T 8.26ms
EN
V
OUT
12919-026
BWBW
Figure 27. Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
EN VOLTAGE (V)
0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65
OUTPUT VOLTAGE (V)
12919-127
Figure 28. Output Voltage vs. Typical EN Pin Voltage, VOUT = 1.3 V
POWER-GOOD (PG) FEATURE
The ADP1761 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the device
is in shutdown mode, current-limit mode, or thermal shutdown,
or if it falls below 90% of the nominal output voltage, PG
immediately transitions low. During soft start, the rising
threshold of the power-good signal is 95% of the nominal
output voltage.
The open-drain output is held low when the ADP1761 has a
sufficient input voltage to turn on the internal PG transistor. An
optional soft start delay can be detected. The PG transistor is
terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 92.5% of the nominal regulator output
voltage when this voltage is rising, with a 95% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no good if VOUT falls below 92.5%.
A normal power-down triggers a power good when VOUT is at 95%.
CH1 1.00V CH2 1.00V M100µs A CH4 420mV
1
2
4
T228.0000µs
CH4 1.00V
VIN
VOUT
PG
12919-027
Figure 29. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V)
1
2
4
CH1 1.00V CH2 1.00V M200µs A CH1 3.00V
T 0.000000s
CH4 1.00V
VIN
VOUT
PG
12919-128
Figure 30. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V)
Data Sheet ADP1761
Rev. C | Page 13 of 18
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1761 is designed for operation with small, space-
saving ceramic capacitors, but it can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A
minimum of 10 μF capacitance with an ESR of 500 mΩ or less is
recommended to ensure the stability of the ADP1761. Transient
response to changes in load current is also affected by output
capacitance. Using a larger value of output capacitance improves
the transient response of the ADP1761 to large changes in load
current. Figure 31 and Figure 32 show the transient responses
for output capacitance values of 10 μF and 47 μF, respectively.
CH1 20.0mV CH2 500mA M1.00µs A CH2 640mA
1
2
T 18.70%
12919-030
V
OUT
I
LOAD
BW
Figure 31. Output Transient Response, COUT = 10 μF
CH1 20.0mV CH2 500mA M1.00µs A CH2 640mA
1
2
T19.00%
12919-031
V
IN
I
LOAD
Figure 32. Output Transient Response, COUT = 47 μF
Input Bypass Capacitor
Connecting a 10 μF capacitor from the VIN pin to the GND pin to
ground reduces the circuit sensitivity to the PCB layout, especially
when long input traces or a high source impedance is encountered.
If output capacitance greater than 10 μF is required, it is
recommended that the input capacitor be increased to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP1761, as
long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over
temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recommended.
Y5V and Z5U dielectrics are not recommended, due to poor
temperature and dc bias characteristics.
Figure 33 shows the capacitance vs. bias voltage characteristics
of an 0805 case, 10 μF, 10 V, X5R capacitor. The voltage
stability of a capacitor is strongly influenced by the capacitor
size and voltage rating. In general, a capacitor in a larger
package or with a higher voltage rating exhibits better stability.
The temperature variation of the X5R dielectric is about ±15%
over the −40°C to +85°C temperature range and is not a
function of package size or voltage rating.
0
2
4
6
8
10
12
0123456
DC BIAS VOLTAGE (V)
C
A
PACITANCE (µF)
12919-032
Figure 33. Capacitance vs. DC Bias Voltage
Use Equation 4 to determine the worst case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = COUT × (1 − tempco) × (1 − TOL) (4)
where:
CEFF is the effective capacitance at the operating voltage.
COUT is the output capacitor.
Tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient
(tempco) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 10 μF at 1.0 V, as shown in Figure 33.
Substituting these values in Equation 4 yields
CEFF = 10 μF × (1 − 0.15) × (1 − 0.1) = 7.65 μF
ADP1761 Data Sheet
Rev. C | Page 14 of 18
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1761, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP1761 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 1.06 V. The UVLO ensures that the ADP1761
inputs and the output behave in a predictable manner during
power-up.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1761 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP1761 is designed to reach the current limit
when the output load reaches 2 A (typical). When the output
load exceeds 2 A, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and power
dissipation) when the junction temperature begins to rise above
150°C, the output is turned off, reducing the output current to
zero. When the junction temperature drops below 135°C (typical),
the output is turned on again, and the output current is restored
to the nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1761 reaches the current limit so that
only 2 A is conducted into the short circuit. If self-heating of
the junction becomes great enough to cause the temperature to
rise above 150°C, thermal shutdown activates, turning off the
output and reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 2 A into the short circuit, again causing the junction
temperature to rise above 150°C. This thermal oscillation between
135°C and 150°C causes a current oscillation between 2 A and
0 A that continues as long as the short circuit remains at the
output.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, limit the device power dissipation externally so
that junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of
the ADP1761 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient
temperature, power dissipation in the power device, and
thermal resistance between the junction and ambient air (θJA).
The θJA value is dependent on the package assembly compounds
used and the amount of copper to which the GND pin and the
exposed pad (EPAD) of the package are soldered on the PCB.
Table 7 shows typical θJA values for the 16-lead LFCSP for
various PCB copper sizes. Table 8 shows typical ΨJB values for
the 16-lead LFCSP.
Table 7. Typical θJA Values
Copper Size (mm2) θJA (°C/W), LFCSP
25 138.1
100 102.9
500 76.9
1000 67.3
6400 56
Table 8. Typical ΨJB Values
Copper Size (mm2) ΨJB (°C/W) at 1 W
100 33.3
500 28.9
1000 28.5
To calculate the junction temperature of the ADP1761, use the
following equation:
TJ = TA + (PD × θJA) (5)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (6)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
As shown in Equation 6, for a given ambient temperature and
computed power dissipation, a minimum copper size requirement
exists for the PCB to ensure that the junction temperature does
not rise above 125°C.
Data Sheet ADP1761
Rev. C | Page 15 of 18
Figure 34 through Figure 39 show the junction temperature
calculations for the different ambient temperatures, load
currents, VIN to VOUT differentials, and areas of PCB copper.
0
20
40
60
80
100
120
140
0.20.40.60.81.01.21.41.6
JUNCTION TEMPER
A
TURE (°C)
V
IN
– V
OUT
(V)
T
J
MAX
10mA
100mA
500mA
1A
12919-034
Figure 34. 6400 mm2 of PCB Copper, TA = 25°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-035
Figure 35. 500 mm2 of PCB Copper, TA = 25°C
VIN – VOUT (V)
0
20
40
60
80
100
120
140
0.20.40.60.81.01.21.41.6
JUNCTION TEMPE
R
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-036
Figure 36. 25 mm2 of PCB Copper, TA = 25°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-037
Figure 37. 6400 mm2 of PCB Copper, TA = 50°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-038
Figure 38. 500 mm2 of PCB Copper, TA = 50°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-039
Figure 39. 25 mm2 of PCB Copper, TA = 50°C
ADP1761 Data Sheet
Rev. C | Page 16 of 18
In cases where the board temperature is known, the thermal
characterization parameter (ΨJB) can estimate the junction
temperature rise. The maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB) (7)
Figure 40 through Figure 43 show the junction temperature
calculations for the different board temperatures, load currents,
VIN to VOUT differentials, and areas of PCB copper.
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.20.40.60.81.01.21.41.6
JUNCTION TEMPE
R
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-040
Figure 40. 500 mm2 of PCB Copper, TB = 25°C
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPE
R
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-041
V
IN
– V
OUT
(V)
Figure 41. 500 mm2 of PCB Copper, TB = 50°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.20.40.60.81.01.21.41.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-042
Figure 42. 1000 mm2 of PCB Copper, TB = 25°C
V
IN
– V
OUT
(V)
0
20
40
60
80
100
120
140
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
JUNCTION TEMPER
A
TURE (°C)
10mA
100mA
500mA
1A
T
J
MAX
12919-043
Figure 43. 1000 mm2 of PCB Copper, TB = 50°C
Data Sheet ADP1761
Rev. C | Page 17 of 18
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP1761.
However, as shown in Table 8, a point of diminishing returns is
eventually reached, beyond which an increase in the copper size
does not yield significant heat dissipation benefits.
Use the following recommendations when designing PCBs:
Place the input capacitor as close as possible to the VIN
and GND pins.
Place the output capacitor as close as possible to the
VOUT and GND pins.
Place the soft start capacitor (CSS) as close as possible to the
SS pin.
Place the reference capacitor (CREF) and regulator capacitor
(CREG) as close as possible to the REFCAP pin and the
VREG pin, respectively.
Connect the load as close as possible to the VOUT and
SENSE pins.
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
12919-044
Figure 44. Evaluation Board
12919-045
Figure 45. Typical Board Layout, Top Side
12919-046
Figure 46. Typical Board Layout, Bottom Side
ADP1761 Data Sheet
Rev. C | Page 18 of 18
OUTLINE DIMENSIONS
1
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.20 REF
0.20 MIN
PKG-005138
SIDE VIEW
08-24-2018-E
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1.75
1.60 SQ
1.45
3.10
3.00 SQ
2.90
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.23
0.18
0.80
0.75
0.70
SEATING
PLANE
EXPOSED
PAD
PIN 1
INDICATORAREAOPTIONS
(SEEDETAILA)
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
0.50
BSC
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range
Output
Voltage (V)2 Package Description
Package
Option
Marking
Code
ADP1761ACPZ-R7 −40°C to +125°C Adjustable 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRJ
ADP1761ACPZ-0.9-R7 −40°C to +125°C 0.9 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRK
ADP1761ACPZ0.95-R7 −40°C to +125°C 0.95 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LUN
ADP1761ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRL
ADP1761ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRM
ADP1761ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRN
ADP1761ACPZ1.25-R7 −40°C to +125°C 1.25 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRP
ADP1761ACPZ-1.3-R7 −40°C to +125°C 1.3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRQ
ADP1761ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LRR
ADP1761-1.3-EVALZ 1.3 Evaluation Board
ADP1761-ADJ-EVALZ 1.1 Evaluation Board
1 Z = RoHS Compliant Part.
2 For additional options, contact a local Analog Devices sales or distribution representative. Additional voltage output options available include the following: 0.5 V,
0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 0.85 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, or 1.45 V.
©2016–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12919-3/20(C)
