Section 20 Electrical Specifications 20.1 Absolute Maximum Ratings Table 20-1 lists the absolute maximum ratings. Table 20-1 Absolute Maximum Ratings ftem Symbol Rating Unit Supply voltage Vcc 0.3 to +7.0 Vv Programming voltage Vpp 0.3 to +13.5 Vv Input voltage (except port 8) Vin -0.3 to Vcc + 0.3 Vv (port 8) Vin -0.3 to AVcc + 0.3 V Analog supply voltage AVcc ~0.3 to +7.0 Vv Analog input voltage VAN -0.3 to AVcc + 0.3 Vv Operating temperature Topr Regular specifications: 20 to +75 C Wide-range specifications: 40 to+85 C Storage temperature Tstg 55 to +125 C Note: Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. 20.2 Electrical Characteristics 20.2.1 DC Characteristics Table 20-2 lists the DC characteristics. 319 HITACHITable 20-2 DC Characteristics Conditions: Vcc = 5.0V 10%*1, AVCC = 5.0V +10%,"! Vss = AVss = OV, Ta = -20 to +75C (Regular Specifications) Ta = 40 to +85C (Wide-Range Specifications) Sym- Measurement Item - bol Min . Typ Max Unit Conditions Input High voltage RES, STBY, VIH Vcc -0.7. - Vec+0.3 V MD2, MD:1, MDo EXTAL Voc x0.7 Vec+0.3 V Port 8 2.2 - AVcc+0.3 V Other input pins 2.2 _ Vec+0.3 V (except port 7) Input Low voltage RES, STBY, Vit -0.3 - 0.5 V MDa, MD1, MDo Other input pins -0.3 - 0.8 Vv (except port 7) Schmitt trigger Port 7 Vr 1.0 - 2.5 Vv input voltage VIt 2.0 - 3.5 V VI+-VT 0.4 = - V Input leakage RES | lin | - - 10.0 uA Vin = 0.5 to current STBY, NMI, - = 1.0 pA Vcc-0.5V MD2, MD1, MDo port 8 ~ - 1.0 uA Vin =.0.5 to AVcc-0.5V Leakage current Port9, [ITs] - 1.0 pA Vin =0.5 to in 3-state ports 7 to 1 Vcec-0.5V (off state) Input pull-up Ports 6and5 -IP 50 - 200 pA Vin =O0V MOS current Output High All output pins = VOH Vec-0.5 -- - Vv 1OH = 200nA Voltage 3.5 - - Vv IOH = -1mMA Output Low Alloutput pins = VoL - - 0.4 Vv lo. = 1.6mA Voltage Port 4 - - 1.0 Vv lo = 8mA - - 1.2 Vv lo. = 10mA Input capacitance RES Cin - - 60 pF Vin= OV NM! - - 30 pF f = 1MHz All input pins - - 15 pF Ta= 25C except RES, NMI Note: *1 AVcc must be connected to a power supply line, even when the A/D converter is not used. HITACHI 320Table 20-2. DC Characteristics (cont) Sym- Measurement Item bol Min Typ Max Unit Conditions Current dissipation*2 Normal operation Icc - 20 30 mA f= 6MHz - 25 40 mA f= 8MHz - 30 50 mA f= 10MHz Sleep mode - 12 20 mA f= 6MHz - 16 25 mA f=8MHz - 20 30 mA f=10MHz Standby - 0.01 50 WBA Ta < 50C - - 20 wA Ta>50C Analog supply During A/D Alec - 1.2 2.0 mA current conversion While waiting - 0.01 50 4wpA RAM standby voltage VRAM 2.0 - - Vv *2 Current dissipation values assume that VIH min = Vcc 0.5V, VIL max = 0.5V, all output pins are in the no-load state, and all MOS input pull-ups are off. Table 20-3 Allowable Output Current Sink Values Conditions: Vcc = 5.0V +10%, AVcc = 5.0V +10%, VSS = AVSS = OV, Ta = 20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications) Item Symbol Min Typ Max Unit Allowable output Low Port 4 Io - - 10 mA current sink (per pin) Other output pins - - 2.0 mA Allowable output Low _ Port 4, total of 8 pins = lot - - 40 mA current sink (total) Total of all other - - 80 mA output pins Allowable output High = All output pins loH - - 2.0 mA current sink (per pin) Allowable output High _Total of all output = -IOH ~ - 25 mA current sink (total) pins Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 20-3. In particular, when driving a Darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 20-1 and 20-2. 321 HITACHIH8/532 H8/532 Vcc we eee Hoe bes Port 6002 Darlington pair Port 4 LED Figure 20-1 Example of Circuit for Driving a Figure 20-2 Example of Circuit for Driving Darlington Transistor Pair an LED 20.2.2 AC Characteristics The AC characteristics of the H8/532 chip are listed in three tables. Bus timing parameters are given in table 20-4, control signal timing parameters in table 20-5, and timing parameters of the on-chip supporting modules in table 20-6. Table 20-4 Bus Timing Conditions: Vcc = 5.0V +10%, AVcc = 5.0V +10%, @ = 0.5 to 1OMHz, Vss = OV Ta = 20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications) 6MHz 8MHz 10MHz Measurement item Symbol Min Max Min Max Min Max Unit Conditions Clock cycle time teyc 166.7 2000 125 2000 100 2000 ns_ See figure 20-4 Clock pulse width Low tCL 65 - 45 - 35 - ns Clock pulse width High tCH 65 - 45 - 35 = ns Clock rise time tCr - 15 - 15 - 15 ns Clock fall time tt - 15 - 15 - 15 ns Address delay time taD - 70 - 65 - 65 ns Address hold time tAH 30 - 2 - 20 - ns Data strobe delay time 1 tOSDi - 70 - 60 - 40 ns Data strobe delay time 2 tbsb2. 70 - 60 - 50 ns Data strobe delay time 3 tDso3. 70 - 60 - 50 ons Write data strobe pulse width tpsww 200) 150 - 120 - ns Address setup time 1 tAS1 25 - 20. - 15 - ns 322 HITACHITable 20-4 Bus Timing (cont) 6MHz 8MHz 10MHz Measurement Item Symbol! Min) Max Min Max Min Max Unit Conditions Address setup time 2 tas2 105 - 80 - 65 - ns See figure 20-4 Read data setup time tRDS 60 - 50 + 40 - ns Read data hold time tRDH 0 - 0 - Oo - ns Read data access time tacc - 280 - 190 - 160 ns Write data delay time twDD - 70 - 6 - 65 as Write data setup time twDs 30 - 15 - 10 - ns Write data hold time tWDH 30 - 2 = 20. - ns Wait setup time twis 40 ~ 40 - 40 - ns__ See figure 20-5 Wait hold time tWTH 10 - 10 - 10 - ns Bus request setup time tsras 40 - 40 - 40 - ns See figure 20-10 Bus acknowledge delay time 1 t8ACD1 70 - 60 - 55 os Bus acknowledge delay time 2 taacb2 70 - 60 - 55 os Bus floating delay time tBzD - tBACD1 tBACD1 - tBACDI NS E clock delay time tED ~ 20 - 1 - 15 ns _ See figure 20-11 E clock rise time tEr - 15 - 1 - 15 ons E clock fall time te - 15 - 15 - 15 ons Read data hold time tRDHE 0 ~ 0 - Oo - ns See figure 20-6 (E clock sync) Write data hold time tWOHE = 50 - 40 - 30 - ns (E clock sync) 323 HITACHITable 20-5 Control Signal Timing Conditions: Vcc = 5.0V +10%, AVCC = 5.0V +10%, g = 0.5 to IOMHz, Vss = OV Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications) 6MHz 8MHz 10MHz Measurement Item Symbol Min Max Min Max Min Max Unit Conditions RES setup time tress 200 - 200 - 200 - ns See figure 20-7 RES pulse width tREsw 6.0 - 6.0 - 6.0 - teyc Mode programming tMDS 40 - 40 - 40 - teyc setup time NMI setup time tNMIS 150 - 150 150 ns See figure 20-8 NMI hoid time tNMIH 10 = 10 - 10 - ns TRQo setup time tiRaas =O 50 - 50 - ns IRQ: setup time tras 50 - 50 - 50 - ns IRQi hold time tiaoiH 6100 10 = 10 - ns NMI pulse width tnmiw 2000 200 - 200 - ns See figure 20-9 (for recovery from software standby mode) Crystal oscillator settling tOsci 20 - 20. - 20 - ms See figure 20-12 time (reset) Crystal oscillator settling time tosc2 10 - 1 - 10 - ms See figure 18-1 (software standby) HITACHI 324Table 20-6 Timing Conditions of On-Chip Supporting Modules Conditions: Vcc = 5.0V 10%, AVCC = 5.0V 10%, 6 = 0.5 to 1OMHz, Vss = 0V Ta = ~20 to +75C (Regular Specifications) Ta = 40 to +85C (Wide-Range Specifications) 6MHz 8MHz 10MHz Measurement Item Symbol Min Max Min Max Min Max Unit Conditions FRT Timer output delay time tFTOD - 100. 100. - 100 ns _ See figure 20-14 Timer input setup time Tis 60 - 50. - 50 - ns Timer clock input setup time FICS 50 - 50 - 50 - ns See figure 20-15 Timer clock pulse width ICM, tficwH 8615 = - 15 = 15 - tye TMR Timer output delay time tTMoD - 100 100 - 100 ns See figure 20-16 Timer clock input setup time tTMcs 50 - 50 - 50 - ns See figure 20-17 Timer clock pulse width tTMCcWL, tTMCWH 615 15 - 15 - teyc Timer reset input setup time {TMRS 50 - 50 - 50 - ns See figure 20-18 PWM _ Timer output delay ime ipwoD 100 100. - 100 ns _ See figure 20-19 Sci Input clock cycle (Async) tSeyc 2 - 2 - 2 - tye See figure 20-20 (Sync) 4 - 4 - 4 - teyc input clock pulse width tschw 04 06) O04 06) 04 (06 Beye Transmit data delay ime (Sync) tTxo ~ 100, - 100 100 ns See figure 20-21 Receive data setup time (Sync) (Axs 100 - {00 - 100 - ns Receive data hold time (Sync) tAXH 100 - 100 - 100 - ns Port Output data delay time tPwo - 100. - 100 - 100 ns See figure 20-13 Input data setup time {PRS 50 - 50. - 50 - ns Input data hold tme tPRH 50 - 50. - 50 - ns * Measurement Conditions for AC Characteristics 5V Re H8/532 output pin C =90pF: P1, P2, P3, P4, PS, P = 30pF: P7, PS Rie = 2.4kQ Ri = 12kQ RH nput/output timing reference levels c Low: 0.8V High: 2.0V Figure 20-3 Output Load Circuit 325 HITACHI20.2.3 A/D Converter Characteristics Table 20-7 lists the characteristics of the on-chip A/D converter. Table 20-7 A/D Converter Characteristics Conditions: Vcc = 5.0V +10%, AVcc = 5.0V +10%, Vss = AVSS = OV, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications) 6MHz 8MHz 10MHz Item Min Typ Max Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 10 10 10 Bits Conversion time 230 17.25 13.8 ps Analog input capacitance - - 20 20 20 pF Allowable signal-source impedance 10 10 10 kQ Nonlinearity error #20 420 +20 LSB Offset error +20 420 +20 LSB Full-scale error 20 #20 +20 LSB Quantizing error 4105 405 +05 LSB Absolute accuracy #25 425 +25 LSB 20.3 MCU Operational Timing This section provides the following timing charts: 20.3.1 Bus timing 20.3.2 Control Signal Timing 20.3.3 Clock Timing 20.3.4 YO Port Timing 20.3.5 16-Bit Free-Running Timer Timing 20.3.6 8-Bit Timer Timing 20.3.7 Pulse Width Modulation Timer Timing 20.3.8 Serial Communication InterfaceTiming HITACHI Figures 20-4 to 20-6 Figures 20-7 to 20-10 Figures 20-11 and 20-12 Figure 20-13 Figures 20-14 and 20-15 Figures 20-16 to 20-18 Figure 20-19 Figure 20-20 and 20-21 32620.3.1 Bus Timing 1. Basic Bus Cycle (without Wait States) in Expanded Modes Ats to Ao RW AS, DS (Read), RD D7 to Do (Read) DS (Write), WR D7 to Do (Write) Figure 20-4 Basic Bus Cycle (without Wait States) in Expanded Modes 327 HITACHI2. Basic Bus Cycle (with 1 Wait State) in Expanded Modes T1 T2 Tw T3 N Ny @ A A ai X _X DS (Read) (Read) RD : iN fo 07000 : <> DS (Write), oS WR / twTs | | tWTH twTs 1] tWTH = Figure 20-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes 328 HITACHI3. Bus Cycle Synchronized with E Clock A1g ta Ao RW AS, DS (Read), RD D7? to Do (Read) DS (Write), WR D7 to Do (Write) Figure 20-6 Bus Cycle Synchronized with E Clock 329 HITACHI20.3.2 Control Signal Timing 1. Reset Input Timing RES MDe to MDo xX! T Figure 20-7 Reset Input Timing 2. Interrupt Input Timing \LY * NY \_) {NMS tNMIK. NMI tRO1S] | tiROTH Vs kK trROOS Figure 20-8 Interrupt Input Timing 3. NMI Pulse Width NMI Figure 20-9 NMI Pulse Width (for Recovery from Software Standby Mode) 330 HITACHI4. Bus Release State Timing tanas PONG ts BREQ (Input) , , teacns taacoz BACK i (Output) . { tazo tao Aig to Ao, RW, Ds, RD, WR, AS Figure 20-10 Bus Release State Timing 20.3.3. Clock Timing 1. E Clock Timing teo ter ter Figure 20-11 E Clock Timing 331 HITACHI2. Clock Oscillator Stabilization Timing tose: Lt oF {6 TTT. DIV I PND EIN wa a 8 2 ~ ~y > g E ie s > a jo Figure 20-12 Clock Oscillator Stabilization Timing 332 HITACHI20.3.4 I/O Port Timing Port read/write cycle T1 T2 - teas tern Port 1 to (Input) port 9 tewo Port 1* to (Output) port9 * Except P14 Pta and P87 to P80 Figure 20-13 I/O Port Input/Output Timing 333 HITACHI20.3.5 16-Bit Free-Running Timer Timing 1. Free-Running Timer Input/Output Timing Free-running timer counter FTOA1, FTOB1, FTOA2, FTOB2, FTOA3, FTOB3 FTi1, FTl2, FTI3 Ne, ee Nee ae Compare-match tetoo XX Figure 20-14 Free-Running Timer Input/Output Timing 2. External Clock Input Timing for Free-Running Timers FITCH, FTCle, om FTCI3 tt i {FICS \ TFTCWL TF TCWH ? N Figure 20-15 External Clock Input Timing for Free-Running Timers HITACHI 33420.3.6 8-Bit Timer Timing 1. 8-Bit Timer Output Timing Sf NAN YZ NN Timer counter. COMpare-match x trwoo TMO vi Figure 20-16 8-Bit Timer Output Timing 2. 8-Bit Timer Clock Input Timing \ trucs, trucs mc1 \ tc. a tracws Figure 20-17 8-Bit Timer Clock Input Timing 3. 8-Bit Timer Reset Input Timing trwas TMRI Timer n xX H'00 counter Figure 20-18 8-Bit Timer Reset Input Timing 335 HITACHI20.3.7 Pulse Width Modulation Timer Timing Sf \_ FNS NY NN Timer Compare-match X counter tPwoDd PW , PW2 , PWws3 Figure 20-19 PWM Timer Output Timing 20.3.8 Serial Communication Interface Timing tsckw [_] tr > Figure 20-20 SCI Input Clock Timing tScyc Serial clock 4 Ne ee trxD sar x << taxs | | [RxXH daa _X. Da IY xX Figure 20-21 SCI Input/Output Timing (Synchronous Mode) 336 HITACHI