TDA7449 Digital tone control audio processor Datasheet - production data Description The TDA7449 is a volume tone (bass and treble) balance (left/right) processor for quality audio applications in TV systems. Selectable input gain is provided. A serial bus controls all functions. ) s t( SO20 Features Input multiplexer - Two stereo inputs - Selectable input gain for optimal adaptation to different sources One stereo output Treble and bass control in 2.0 db steps Volume control in 1.0 db steps ) s t( Two speaker attenuators: - Two independent speaker controls in 1.0 db steps to facilitate balance - Independent mute function c u d The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. o r P Bipolar/CMOS technology used allows obtaining low distortion, low noise and DC stepping. e t le so Table 1. Device summary Order code Package Packing TDA7449D13TR SO20 Tape and reel b O - c u d o r P All functions are programmable via serial bus e t le so Ob L-IN1 Figure 1. Block diagram MUXOUTL 10 TREBLE(L) 16 BIN(L) BOUT(L) 15 8 14 RB 100K L-IN2 9 G 100K R-IN1 VOLUME SPKR ATT LEFT BASS I2CBUS DECODER + LATCHES 20 18 100K R-IN2 5 19 0/30dB 2dB STEP 7 TREBLE 6 G 100K VOLUME TREBLE SPKR ATT RIGHT BASS 4 LOUT SCL SDA DIG_GND ROUT VREF 2 SUPPLY INPUT MULTIPLEXER + GAIN RB 11 MUXOUTR September 2014 This is information on a product in full production. 17 TREBLE(R) DocID006317 Rev 5 12 13 BIN(R) BOUT(R) 3 VS AGND 1 CREF D98AU847A 1/21 www.st.com Contents TDA7449 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics and test circuit . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Application recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Bass, stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 c u d I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 o r P 4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 e t le o s b O ) s ( t c Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 6 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 u d o r P e Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 No incremental bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Incremental bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 t e l o s b O 7 ) s t( Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 DocID006317 Rev 5 TDA7449 1 Overview Overview Table 2. Absolute maximum ratings Symbol Parameter VS Operating supply voltage Tamb Operating ambient temperature Tstg Storage temperature range Value Unit 10.5 V 0 to 70 C -55 to 150 C ) s t( Figure 2. Pin connections CREF 1 20 SDA 2 19 SCL 3 18 DIG_GND ROUT 4 17 TREBLE(R) LOUT 5 16 TREBLE(L) R_IN2 6 15 BIN(L) R_IN1 7 14 BOUT(L) L_IN1 8 13 BOUT(R) L_IN2 9 12 BIN(R) 11 MUXOUT(R) MUXOUT(L) Rth j-pin du O bs e t le o s b -O 10 o r P D98AU848 Table 3. Thermal data Parameter ro Thermal resistance junction pins P e et ol ) s ( ct Symbol c u d VS PGND Value Unit 85 C/W Table 4. Quick reference data Symbol Parameter Min. Typ. Max. Unit 9 10.2 V VS Supply voltage 6 VCL Max input signal handling 2 THD Total harmonic distortion V = 0.1 Vrms f = 1 kHz 0.01 S/N Signal-to-noise ratio Vout = 1 Vrms (mode = OFF) 106 dB SC Channel separation f = 1 KHz 90 dB Input gain (2 dB step) VRMS 0.1 % 0 30 dB Volume control (1 dB step) -47 0 dB Treble control (2 dB step) -14 14 dB Bass control (2 dB step) -14 14 dB Balance control 1 dB step -79 0 dB Mute attenuation 100 DocID006317 Rev 5 dB 3/21 21 Electrical characteristics and test circuit 2 TDA7449 Electrical characteristics and test circuit Table 5. Electrical characteristics (refer to the test circuit Tamb = 25 C, VS = 9 V, RL= 10 k, RG = 600 , all controls flat (G = 0 dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 6 9 10.2 V Supply VS Supply voltage IS Supply current SVR Ripple rejection 7 60 Input resistance VCL Clipping level THD = 0.3% SIN Input separation The selected input is grounded through a 2.2 capacitor Ginmin Minimum input gain Ginman Maximum input gain Control range AVMAX Max. attenuation ASTEP Step resolution l o s ) (s e t e ol s b O ET VDC Amute o r P Attenuation set error Tracking error DC step 80 -1 Ob ct du EA c u d ro 2 P e et Volume control CRANGE dB 100 Step resolution Gstep ) s t( 90 Input stage RIN mA k 2.5 Vrms 100 dB 0 1 dB 30 dB 2 dB 45 47 49 dB 45 47 49 dB 0.5 1 1.5 dB AV = 0 to -24 dB -1.0 0 1.0 dB AV = -24 to -47 dB -1.5 0 1.5 dB AV = 0 to -24 dB 0 1 dB AV = -24 to -47 dB 0 2 dB adjacent attenuation steps 0 3 mV from 0 dB to AV max Mute attenuation 0.5 mV 80 100 dB +12.0 +14.0 +16.0 dB 1 2 3 dB 18.75 25 31.25 K +13.0 +14.0 +15.0 dB 1 2 3 dB Bass control (1) Gb BSTEP RB Control range Max. boost/cut Step resolution Internal feedback resistance Treble control (1) Gt TSTEP 4/21 Control range Max. boost/cut Step resolution DocID006317 Rev 5 TDA7449 Electrical characteristics and test circuit Table 5. Electrical characteristics (refer to the test circuit Tamb = 25 C, VS = 9 V, RL= 10 k, RG = 600 , all controls flat (G = 0 dB), unless otherwise specified) (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Speaker attenuators CRANGE Control range 76 Step resolution SSTEP EA Attenuation set error VDC DC Step AV = 0 to -20 dB AV = -20 to -56 dB 0.5 1 1.5 dB -1.5 0 1.5 dB -2 0 2 dB 0 3 mV adjacent attenuation steps Mute attenuation Amute 80 100 2.1 2.6 Clipping level d = 0.3% RL Output load resistance RO Output impedance VDC DC voltage level e t e Et S/N Signal-to-Noise ratio SC Channel separation left/right VIL e t le so Ob Note: VIH Pr Distortion Bus input u d o 40 70 b O - VRMS k W V 5 15 V AV = 0 to -24dB 0 1 dB AV = -24 to -47dB 0 2 dB ) s ( ct dB 3.8 All gains = 0dB; BW = 20Hz to 20KHz flat Output noise Total tracking error d 10 l o s General ENO o r P 2 ) s t( c u d Audio outputs VCLIP dB All gains 0dB; VO = 1VRMS ; 80 AV = 0; VI = 1VRMS ; 106 dB 100 dB 0.01 Input low voltage Input high voltage 0.08 % 1 V 3 IIN Input current VIN = 0.4 V VO Output voltage SDA acknowledge IO = 1.6 mA V -5 0.4 5 A 0.8 V 1. The device is functionally good at Vs = 5 V. A step down on Vs to 4 V doesn't reset the device. 2. Bass and treble response: the center frequency and the response quality can be chosen by the external circuitry. DocID006317 Rev 5 5/21 21 Electrical characteristics and test circuit TDA7449 Figure 3. Test circuit R2 2K C9 5.6nF 150nF J5 C7 TREBLE(L) MUXOUTL IN1L J3 10 RCA 1 2 J4 3 4 5 330nF 16 C8 BIN(L) BOUT(L) 15 14 GND IN2L GND L-IN1 RB 8 L-IN2 9 G 100K VOLUME TREBLE SPKR ATT LEFT BASS 0/30dB 2dB STEP J1 3 4 IN2R GND IN1R GND R-IN2 18 DIG_GND 19 SCL 20 SDA G VOLUME TREBLE SPKR ATT RIGHT BASS 3 4 ) s t( c u d VREF SUPPLY MOUTL RB 11 GND R3 30 MUXOUTR TREBLE(R) BOUT(R) C6 GND C10 5.6nF ) (s 150nF R1 t c u d o r P e et l o s Ob DocID006317 Rev 5 330nF 2K ol s b O ro AGND P e et 13 C5 2 VS 12 17 MOUTR CON4 6/21 J6 4 100K BIN(R) 2 3 ROUT 7 INPUT MULTIPLEXER + GAIN 1 2 4 3 J5 1 CON4 100K C2 0.47F CON JP1 JUMPER 6 C1 0.47F R-IN1 I2CBUS DECODER + LATCHES J10 4 CON4 J2 RCA 3 OUT_ R LOUT +9 V 2 2 5 IN1R 1 1 OUT_L 100K C3 0.47F C4 0.47F CON3 J9 OUT_L GND IN1L J8 OUT_R 1 CREF C11 10F D98AU849A C13 100nF C12 22F +V8 +9V GND 1 2 CON2 J7 TDA7449 3 Application recommendations Application recommendations The first and the last stages are volume control blocks. The control range is 0 to -47 dB (mute) for the first one and 0 to -79 dB (mute) for the last one. Both of them have 1 dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7449 audio processor provides dual-band tone control. Typical responses are shown in Figure 5 through 9. 3.1 Bass stage ) s t( The bass cell has an internal resistor Ri = 25 k typical. Several filter types can be implemented, connecting external components to the bass IN and OUT pins. Figure 4 refers to a basic T-type bandpass filter. The filter component values R1 internal FC, the gain AV at max. boost and the filter Q factor are calculated as given below. c u d Figure 4. T bandpass filter Ri internal e t le IN OUT C1 C2 o r P o s b R2 O ) D95AU313 1 F C = ----------------------------------------------------------------2 R1 R2 C1 C2 s ( t c u d o r P e t e l o R2C2 + R2C1 + RiC1 A V = -----------------------------------------------------------R2C1 + R2C2 R1 R2 C1 C2 Q = ------------------------------------------------R2C1 + R2C2 Once the FC, AV, and Ri internal values are fixed, the external component values will be: bs O 3.2 AV - 1 C1 = ----------------------------------------2 Fc Ri Q 2 Q C1 C2 = -----------------------------2 AV - 1 - Q 2 AV - 1 - Q R2 = --------------------------------------------------------------------2 C1 Fc A V - 1 Q Treble stage The treble stage is a high-pass filter whose time constant is fixed by an internal resistor (25 k typical) and an external capacitor connected between the treble pins and ground. 3.3 CREF The recommended 10 F reference capacitor (CREF) value can be reduced to 4.7 F if the application requires faster power ON. DocID006317 Rev 5 7/21 21 Application recommendations TDA7449 Figure 5. THD vs. frequency Figure 6. Bass response ) s t( c u d Figure 7. THD vs. RLOAD e t le o s b O ) s ( t c u d o r P e Figure 9. Channel separation vs. frequency t e l o s b O 8/21 o r P Figure 8. Treble response DocID006317 Rev 5 I2C bus interface TDA7449 I2C bus interface 4 Data transmission from the microprocessor to the TDA7449 and vice versa takes place through the 2-wire I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to the positive supply voltage must be connected). 4.1 Data validity As shown in Figure 10, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 ) s t( c u d Start and stop conditions o r P As shown in Figure 11, a start condition is a HIGH-to-LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW-to-HIGH transition of the SDA line while SCL is HIGH. 4.3 e t le o s b Byte format O ) Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge s ( t c u d o The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 12). The peripheral (audio processor) that acknowledges has to pull down (LOW) the SDA line during this clock pulse. r P e t e l o s b O 4.5 The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without acknowledge Instead of detecting the acknowledge from the audio processor, the P can use a simpler transmission which is to simply wait one clock pulse without checking the slave acknowledge and send the new data. This is of course a riskier approach. DocID006317 Rev 5 9/21 21 I2C bus interface TDA7449 Figure 10. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 11. Timing diagram of I2C bus ) s t( SCL c u d I2CBUS SDA D99AU1032 START o r P STOP e t le Figure 12. Acknowledge on the I2C bus SCL 1 SDA u d o o s b O ) s ( t c MSB START 2 3 D99AU1033 r P e t e l o s b O 10/21 DocID006317 Rev 5 7 8 9 ACKNOWLEDGMENT FROM RECEIVER TDA7449 Software specifications 5 Software specifications 5.1 Interface protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7449 address A subaddress byte A sequence of data (N byte + acknowledge) A stop condition (P) Figure 13. Interface protocol SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X B DATA MSB ACK D96AU420 e t le ACK = Acknowledge S = Start c u d DATA 1 to DATA n LSB X X ) s t( o r P DATA LSB ACK P o s b P = Stop O ) A = Address B = Auto-increment s ( t c u d o r P e t e l o s b O DocID006317 Rev 5 11/21 21 Examples TDA7449 6 Examples 6.1 No incremental bus The TDA7449 receives a start condition, the correct chip address, a subaddress with B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. Figure 14. No incremental bus (B = 0) SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK LSB X X DATA X MSB DATA ACK P c u d D96AU421 6.2 ) s t( LSB 0 D3 D2 D1 D0 ACK Incremental bus o r P The TDA7449 receives a start condition, the correct chip address, a subaddress with B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. e t le o s b DATA 1 concern the subaddress sent, and DATA 2 concerns the subaddress sent plus one in the loop etc, and at the end it receives the stop condition. O ) Figure 15. Incremental bus (B=1) t(s CHIP ADDRESS uc MSB S 1 LSB 0 0 0 eP s b O 12/21 0 0 d o r D96AU422 t e l o 1 0 SUBADDRESS MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 ACK MSB LSB DATA ACK Table 6. Power-on reset condition Input selection IN2 Input gain 28 dB Volume Mute Bass 0 dB Treble 2 dB Speaker Mute DocID006317 Rev 5 P TDA7449 7 Data bytes Data bytes Address = 88 hex (Addr: OPEN) Table 7. Function selection: first byte (subaddress) MSB LSB Subaddress D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 Input select X X X B 0 0 0 1 Input gain X X X B 0 0 1 0 Volume X X X B 0 0 1 1 Not allowed X X X B 0 1 0 0 Bass X X X B 0 1 0 1 X X X B 0 1 1 X X X B 0 1 1 B = 1: incremental bus active B = 0: no incremental bus ) s t( X = don't care MSB O bs od e t e o r P 1 Treble Speaker attenuate "R" Speaker attenuate "L" b O - Table 8. Input selection LSB X Pr X X X X X 0 0 Not allowed X X X X X X 0 1 Not allowed X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 D7 e t e ol uc c u d 0 l o s ) s t( Input multiplexer D6 D5 D4 D3 D2 D1 D0 DocID006317 Rev 5 13/21 21 Data bytes TDA7449 Table 9. Input gain selection MSB D7 D6 D5 D4 D2 D1 D0 2 dB steps 0 0 0 0 0 dB 0 0 0 1 2 dB 0 0 1 0 4 dB 0 0 1 1 6 dB 0 1 0 0 8 dB 0 1 0 1 10 dB 0 1 1 0 12 dB 0 1 1 1 14 dB 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 22 dB 1 1 0 0 24 dB 1 1 0 1 26 dB 1 0 28 dB 1 1 30 dB 1 ) s t( Input gain D3 b O - 1 1 ) s t( uc d o r P e et l o s 1 Gain = 0 to 30 dB LSB 16 dB 18 dB 20 dB Table 10. Volume selection uc MSB D7 e t le od D6 Pr D5 D4 D3 so Ob Volume D2 D1 D0 1 dB steps 0 0 0 0 dB 0 0 1 -1 dB 0 1 0 -2 dB 0 1 1 -3 dB 1 0 0 -4 dB 1 0 1 -5 dB 1 1 0 -6 dB 1 1 1 -7 dB 0 0 0 0 0 dB 0 0 0 1 -8 dB 0 0 1 0 -16 dB 0 0 1 1 -24 dB 0 1 0 0 -32 dB 0 1 0 1 -40 dB X 1 1 1 X Volume = 0 to 47dB/mute 14/21 LSB DocID006317 Rev 5 X X Mute TDA7449 Data bytes Table 11. Bass selection MSB D7 D6 D5 D4 Bass D3 D2 D1 D0 2 dB steps 0 0 0 0 -14 dB 0 0 0 1 -12 dB 0 0 1 0 -10 dB 0 0 1 1 -8 dB 0 1 0 0 -6 dB 0 1 0 1 -4 dB 0 1 1 0 -2 dB 0 1 1 1 0 dB 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 b O 1 e t e c u d o r P 1 0 ) s t( 0 dB 2 dB 4 dB 6 dB 1 1 8 dB 1 0 10 dB 0 0 1 12 dB 0 0 0 14 dB LSB Treble D0 2 dB steps l o s 1 ) s t( LSB 0 Table 12. Treble selection uc MSB D7 e t le O o s b od D6 Pr D5 D4 D3 D2 D1 0 0 0 0 -14 dB 0 0 0 1 -12 dB 0 0 1 0 -10 dB 0 0 1 1 -8 dB 0 1 0 0 -6 dB 0 1 0 1 -4 dB 0 1 1 0 -2 dB 0 1 1 1 0 dB 1 1 1 1 0 dB 1 1 1 0 2 dB 1 1 0 1 4 dB 1 1 0 0 6 dB 1 0 1 1 8 dB 1 0 1 0 10 dB 1 0 0 1 12 dB 1 0 0 0 14 dB DocID006317 Rev 5 15/21 21 Data bytes TDA7449 Table 13. Speaker attenuation selection MSB D7 D6 D5 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 Ob 16/21 1 Speaker attenuation D2 D1 D0 1 dB 0 0 0 0 dB 0 0 1 -1 dB 0 1 0 -2 dB 0 1 1 -3 dB 1 0 0 -4 dB 1 0 1 -5 dB 1 1 0 1 1 1 c u d e t le so b O 0 ) s t( -6 dB o r P -7 dB 0 dB -8 dB -16 dB -24 dB -32 dB 1 -40 dB 0 -48 dB 1 1 -56 dB ) s ( t c u 1 0 0 0 -64 dB 0 0 1 -72 dB 1 1 1 od Pr 1 so D3 0 1 e t le D4 LSB X Speaker attenuation = 0 to -79dB/mute DocID006317 Rev 5 X X Mute TDA7449 Data bytes Figure 16. Pin 1 Figure 17. Pins 10, 11 VS VS VS VS 20A 20K CREF MUXOUT ) s t( 20K c u d GND D96AU491 D96AU430 Figure 18. Pins 4, 5 e t le VS VS o s b LOUT s ( t c 20A u d o Pr 25K BIN(L) BIN(R) D96AU434 Figure 20. Pins 6, 7, 8, 9 D98AU850 Figure 21. Pins 13, 14 o s b O 20A O ) 24 ROUT e t le o r P Figure 19. Pins 12, 15 VS VS 20A 20A IN 100K VREF 44K BOUT(L) D96AU425 BOUT(R) DocID006317 Rev 5 D96AU429 17/21 21 Data bytes TDA7449 Figure 22. Pins 16, 17 Figure 23. Pin 20 VS 20A 20A SDA TREBLE(L) TREBLE(R) 50K uc D96AU423 D96AU433 d o r Figure 24. Pin 19 P e et l o s 20A SCL ) s t( b O - c u d e t le o r P D96AU424 o s b O 18/21 ) s t( DocID006317 Rev 5 TDA7449 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 25. SO20 mechanical data & package dimensions mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 e 1.27 c u d e t le 0.299 o r P o s b 0.050 H 10.0 10.65 0.394 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ) s t( 0.419 O ) s ( t c 0 (min.), 8 (max.) ddd 0.10 0.004 u d o (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 r P e t e l o s b O 0016022 D DocID006317 Rev 5 19/21 21 Revision history 9 TDA7449 Revision history Table 14. Document revision history Date Revision 03-Sep-2014 Changes Removed DIP20 package option Updated Table 1: Device summary Revised document presentation along with minor textual updates and modification of title 5 ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 20/21 DocID006317 Rev 5 o r P TDA7449 ) s t( c u d e t le o r P o s b O ) s ( t c u d o IMPORTANT NOTICE - PLEASE READ CAREFULLY r P e STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. 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