A3P1000-1PQG208II - Microsemi Corp.

February 2009 I

ProASIC3 Flash Family FPGAs

with Optional Soft ARM® Support

Features and Benefits

High Capacity

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI†

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM-enabled ProASIC®3

devices) via JTAG (IEEE 1532–compliant)†

•FlashLock

® to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os‡

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory†

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†

• True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs

• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft

Processor Available with or without Debug

† A3P015 and A3P030 devices do not support this feature. ‡ Supported only by A3P015 and A3P030 devices.

Table 1 • ProASIC3 Product Family

ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

ARM7 Devices 1M7A3P1000

Cortex-M1 Devices 1M1A3P250 M1A3P400 M1A3P600 M1A3P1000

System Gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 M

Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – –

VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576

RAM kbits (1,024 bits) – – 18 36 36 54 108 144

4,608-Bit Blocks ––488122432

FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k

Secure (AES) ISP 2– – Yes Yes Yes Yes Yes Yes

Integrated PLL in CCCs ––111 1 1 1

VersaNet Globals 36 6 18 18 18 18 18 18

I/O Banks 22224 4 4 4

Maximum User I/Os 49 81 96 133 157 194 235 300

Package Pins

QFN

VQFP

TQFP

PQFP

FBGA

QN68 QN48, QN68,

QN132

VQ100

QN132

VQ100

TQ144

FG144

QN132

VQ100

TQ144

PQ208

FG144

QN132 5

VQ100

PQ208

FG144/256 5PQ208

FG144/256/

484

PQ208

FG144/256/

484

PQ208

FG144/256/

484

Notes:

1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.

5. The M1A3P250 device does not support this package.

v1.1

II v1.1

I/Os Per Package 1

ProASIC3

Devices A3P015 A3P030 A3P060 A3P125 A3P250 3A3P400 3A3P600 A3P1000

ARM7 Devices M7A3P1000

Cortex-M1

Devices M1A3P250 3,6 M1A3P400 3M1A3P600 M1A3P1000

Package

I/O Type

Single-Ended I/O

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

Single-Ended I/O2

Differential I/O Pairs

QN48 34

QN68 49 49 – – – – –– –––

QN132 – 8180848719–– –––

VQ100 – 77 71 71 68 13 – – – – –

TQ144 – – 91 100 – – ––––––

PQ208 – – – 133 151 34 151 34 154 35 154 35

FG144 – – 96 97 97 24 97 25 97 25 97 25

FG256 – – – – 157 38 178 38 177 43 177 44

FG484 – – – – – – 194 38 235 60 300 74

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs

handbook to ensure complying with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer

to the ProASIC3 Flash Family FPGAs handbook for position assignments of the 15 LVPECL pairs.

4. FG256 and FG484 are footprint-compatible packages.

5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the

"G" in the part number.

6. The M1A3P250 device does not support FG256 or QN132 packages.

Table 2 • ProASIC3 FPGAs Package Sizes Dimensions

Package QN48 QN68 QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484

Length × Width

(mm\mm)

6 × 6 8 × 8 8 × 8 14 × 14 20 × 20 28 × 28 13 × 13 17 × 17 23 × 23

Nominal Area

(mm2)

36 64 64 196 400 784 169 289 529

Pitch (mm) 0.4 0.4 0.5 0.5 0.5 0.5 1.0 1.0 1.0

Height (mm) 0.90 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23

ProASIC3 Flash Family FPGAs

v1.1 III

ProASIC3 Ordering Information

*The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in

the commercial temperature range.

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

F = 20% Slower than Standard*

A3P1000 FG

Part Number

ProASIC3 Devices

ProASIC3 Devices with ARM7

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

TQ =Thin Quad Flat Pack (0.5 mm pitch)

144 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

30,000 System Gates

A3P030 =

15,000 System Gates

A3P015 =

60,000 System Gates

A3P060 =

125,000 System Gates

A3P125 =

250,000 System Gates

A3P250 =

400,000 System Gates

A3P400 =

600,000 System Gates

A3P600 =

1,000,000 System Gates

A3P1000 =

ProASIC3 Devices with Cortex-M1

250,000 System Gates

M1A3P250 =

400,000 System Gates

M1A3P400 =

600,000 System Gates

M1A3P600 =

1,000,000 System Gates

M1A3P1000 =

1,000,000 System Gates

M7A3P1000 =

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

IV v1.1

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start

with M7 (CoreMP7) and M1 (Cortex-M1).

Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.

A3P015 and A3P030

The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.

Package A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

ARM7 Devices M7A3P1000

Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000

QN48 –C, I––––– –

QN68 C, I C, I – – – – – –

QN132 – C, I C, I C, I C, I – – –

VQ100 – C, I C, I C, I C, I – – –

TQ144 – – C, I C, I – – – –

PQ208 – – – C, I C, I C, I C, I C, I

FG144 – – C, I C, I C, I C, I C, I C, I

FG256 – – – – C, I C, I C, I C, I

FG484 – – – – – C, I C, I C, I

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature

2. I = Industrial temperature range: –40°C to 85°C ambient temperature

Temperature Grade –F 1Std. –1 –2

C2✓✓✓✓

I3–✓✓✓

Notes:

1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

2. C = Commercial temperature range: 0°C to 70°C ambient temperature

3. I = Industrial temperature range: –40°C to 85°C ambient temperature

v1.1 1-1

1 – ProASIC3 Device Family Overview

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and

A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices

have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do

not support AES decryption.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in

the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES

decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3 devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure

design verification is possible.

ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the

ARM core must be protected at all times, AES encryption is always on for the core logic, so

bitstreams are always encrypted. There is no user access to encryption for the FlashROM

programming data.

ProASIC3 Device Family Overview

1-2 v1.1

Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES

security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable

IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3 FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system

power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs,

the device will not have to be reloaded when system power is restored. This enables the reduction

or complete removal of the configuration PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total

system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)

errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current

surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3 devices also have low dynamic power consumption to further maximize power savings.

ProASIC3 Device Family Overview

v1.1 1-3

Advanced Flash Technology

The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and

Figure 1-2 on page 1-4):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory†

• Extensive CCCs and PLLs†

• Advanced I/O structure

† The A3P015 and A3P030 do not support PLL or SRAM.

*Not supported by A3P015 and A3P030 devices

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and

A3P125)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

VersaTile

CCC

I/Os

ISP AES

Decryption*

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

ProASIC3 Device Family Overview

1-4 v1.1

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input

lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3 devices via an IEEE 1532 JTAG interface.

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core

tiles. The ProASIC3 VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600 and A3P1000)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ProASIC3 Device Family Overview

v1.1 1-5

Refer to Figure 1-3 for VersaTile configurations.

User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the A3P015 and A3P030 devices),

as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3 development software solutions, Libero® Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their

north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port.

For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded

SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG

macro (except in A3P015 and A3P030 devices).

Figure 1-3 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3 Device Family Overview

1-6 v1.1

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member

of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and

A3P030 devices do not have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL

only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC) (for PLL only)

Global Clocking

ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high fanout nets.

ProASIC3 Device Family Overview

v1.1 1-7

I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended

and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications

• Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.

B-LVDS and M-LVDS can support up to 20 loads.

Wide Range I/O Support

Actel ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the

JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of

2.7 V to 3.6 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components

from the board or move to less costly components with greater tolerances. Wide range eases I/O

bank management and provides enhanced protection from system voltage spikes, while providing

the flexibility to easily run custom voltage applications.

Part Number and Revision Date

Part Number 51700097-001-2

Revised February 2009

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v1.1) Page

v1.0

(February 2008)

The "Advanced I/O" section was revised to add a bullet regarding wide range

power supply voltage support.

The Table 1 · ProASIC3 Product Family was updated to include a value for

typical equivalent macrocells or A3P250.

The QN48 package was added to the following tables:

"ProASIC3 Product Family"

"I/Os Per Package 1"

"ProASIC3 FPGAs Package Sizes Dimensions"

"Temperature Grade Offerings"

The number of singled-ended I/Os for QN68 was added to the "I/Os Per

Package 1" table.

N/A

The "Wide Range I/O Support" section is new. 1-7

51700097-001-1 This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

N/A

ProASIC3 Device Family Overview

1-8 v1.1

51700097-001-0

(January 2008)

This document was updated to include A3P015 device information. QN68 is a

new package that was added because it is offered in the A3P015. The following

sections were updated:

"Features and Benefits"

"ProASIC3 Ordering Information"

"Temperature Grade Offerings"

"ProASIC3 Product Family"

"A3P015 and A3P030" note

"Introduction and Overview"

N/A

The "ProASIC3 FPGAs Package Sizes Dimensions" table is new. II

In the "ProASIC3 Ordering Information", the QN package measurements were

updated to include both 0.4 mm and 0.5 mm.

III

In the "General Description" section, the number of I/Os was updated from 288

to 300.

1-1

v2.2

(July 2007)

This document was previously in datasheet v2.2. As a result of moving to the

handbook format, Actel has restarted the version numbers. The new version

number is 51700097-001-0.

N/A

v2.1

(May 2007)

The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3

Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering

Information", "Temperature Grade Offerings", and "Speed Grade and

Temperature Grade Matrix".

i, ii, iii,

iii, iv

The words "ambient temperature" were added to the temperature range in

the "Automotive ProASIC3 Ordering Information", "Temperature Grade

Offerings", and "Speed Grade and Temperature Grade Matrix" sections.

iii, iv

v2.0

(April 2007)

In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input

Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).

The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i

In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and

A3P600 device I/Os were updated.

Advance v0.7

(January 2007)

In the "Packaging Tables", Ambient was deleted. ii

Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv

Advance v0.6

(April 2006)

In the "I/Os Per Package" table, the I/O numbers were added for A3P060,

A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.

Advance v0.5

(January 2006)

B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Table 1 was updated to include the QN132. ii

The "I/Os Per Package" table was updated with the QN132. The footnotes were

also updated. The A3P400-FG144 I/O count was updated.

"Automotive ProASIC3 Ordering Information" was updated with the QN132. iii

"Temperature Grade Offerings" was updated with the QN132. iii

Advance v0.4

(November 2005)

The "I/Os Per Package" table was updated for the following devices and

packages:

Device Package

A3P250/M7ACP250 VQ100

A3P250/M7ACP250 FG144

A3P1000 FG256

Previous Version Changes in Current Version (v1.1) Page

ProASIC3 Device Family Overview

v1.1 1-9

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

Advance v0.3 M7 device information is new. N/A

The I/O counts in the "I/Os Per Package" table were updated. ii

Advance v0.2 The "I/Os Per Package" table was updated. ii

Previous Version Changes in Current Version (v1.1) Page

v1.3 2-1

2 – ProASIC3 DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VMV DC I/O input buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V

(when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

ProASIC3 DC and Switching Characteristics

2-2 v1.3

Table 2-2 • Recommended Operating Conditions 1

Symbol Parameter Commercial Industrial Units

TAAmbient temperature 0 to +70 4,6 –40 to +85 5,6 °C

VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation 30 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.4 to 1.6 1.4 to 1.6 V

VCCI and VMV 21.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-18 on page 2-19. VMV and VCCI should be at the same voltage within a

given I/O bank.

3. VPUMP can be left floating during operation (not programming mode).

4. Maximum TJ = 85°C.

5. Maximum TJ = 100°C.

6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

ProASIC3 DC and Switching Characteristics

v1.3 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3 DC and Switching Characteristics

2-4 v1.3

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3 DC and Switching Characteristics

v1.3 2-5

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 100°C70°C–

20.5°C/W

------------------------------------ 1 . 4 6 3 W

===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W

A3P060 132 0.3 21.2 16.6 15.0 C/W

A3P125 132 0.2 21.1 16.5 14.9 C/W

A3P250 132 0.1 21.0 16.4 14.8 C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W

Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W

PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W

See note* 256 3.8 26.6 22.8 21.5 C/W

See note* 484 3.2 20.5 17.0 15.9 C/W

A3P1000 144 6.3 31.6 26.2 24.2 C/W

A3P1000 256 6.6 28.1 24.4 22.7 C/W

A3P1000 484 8.0 23.3 19.0 16.7 C/W

*This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal

information will be available in future revisions of the datasheet.

ProASIC3 DC and Switching Characteristics

2-6 v1.3

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.425 0.87 0.92 0.95 1.00 1.02 1.05

1.500 0.83 0.88 0.90 0.95 0.97 0.99

1.575 0.80 0.85 0.87 0.92 0.93 0.96

Table 2-7 • Quiescent Supply Current Characteristics

A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Typical (25°C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA

Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA

Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA

Notes:

1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution,

which is shown in Table 2-11 and Table 2-12 on page 2-8.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD

and higher I/O leakage.

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

VMV (V)

Static Power

PDC2 (mW) 1 Dynamic Power PAC9

(µW/MHz) 2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.69

2.5 V LVCMOS 2.5 – 5.12

1.8 V LVCMOS 1.8 – 2.13

1.5 V LVCMOS (JESD8-11) 1.5 – 1.45

3.3 V PCI 3.3 – 18.11

3.3 V PCI-X 3.3 – 18.11

Differential

LVDS 2.5 2.26 1.20

LVPECL 3.3 5.72 1.87

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

ProASIC3 DC and Switching Characteristics

v1.3 2-7

Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

VMV (V)

Static Power

PDC2 (mW) 1 Dynamic Power

PAC9 (µW/MHz) 2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.72

2.5 V LVCMOS 2.5 – 5.14

1.8 V LVCMOS 1.8 – 2.13

1.5 V LVCMOS (JESD8-11) 1.5 – 1.48

3.3 V PCI 3.3 – 18.13

3.3 V PCI-X 3.3 – 18.13

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

VMV (V)

Static Power

PDC2 (mW) 1 Dynamic Power

PAC9 (µW/MHz) 2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.79

2.5 V LVCMOS 2.5 – 5.19

1.8 V LVCMOS 1.8 – 2.18

1.5 V LVCMOS (JESD8-11) 1.5 – 1.52

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

1. PAC9 is the total dynamic power measured on VCC and VMV.

ProASIC3 DC and Switching Characteristics

2-8 v1.3

Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

35 3.3 – 468.67

2.5 V LVCMOS 35 2.5 – 267.48

1.8 V LVCMOS 35 1.8 – 149.46

1.5 V LVCMOS

(JESD8-11)

35 1.5 – 103.12

3.3 V PCI 10 3.3 – 201.02

3.3 V PCI-X 10 3.3 – 201.02

Differential

LVDS – 2.5 7.74 88.92

LVPECL – 3.3 19.54 166.52

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1

Applicable to Standard Plus I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

35 3.3 – 452.67

2.5 V LVCMOS 35 2.5 – 258.32

1.8 V LVCMOS 35 1.8 – 133.59

1.5 V LVCMOS

(JESD8-11)

35 1.5 – 92.84

3.3 V PCI 10 3.3 – 184.92

3.3 V PCI-X 10 3.3 – 184.92

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. PDC3 is the static power (where applicable) measured on VMV.

3. PAC10 is the total dynamic power measured on VCC and VMV.

ProASIC3 DC and Switching Characteristics

v1.3 2-9

Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1

Applicable to Standard I/O Banks

CLOAD (pF) VCCI (V)

Static Power

PDC3 (mW) 2Dynamic Power

PAC10 (µW/MHz) 3

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

35 3.3 – 431.08

2.5 V LVCMOS 35 2.5 – 247.36

1.8 V LVCMOS 35 1.8 – 128.46

1.5 V LVCMOS

(JESD8-11)

35 1.5 – 89.46

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

ProASIC3 DC and Switching Characteristics

2-10 v1.3

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Parameter Definition

Device Specific Dynamic Contributions

(µW/MHz)

A3P1000

A3P600

A3P400

A3P250

A3P125

A3P060

A3P030

A3P015

PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30

PAC2 Clock contribution of a Global Spine 2.48 1.85 1.35 1.58 0.81 0.81 0.41 0.41

PAC3 Clock contribution of a VersaTile row 0.81

PAC4 Clock contribution of a VersaTile used as a

sequential module

0.12

PAC5 First contribution of a VersaTile used as a

sequential module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a

combinatorial Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin (standard

dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

PAC10 Contribution of an I/O output pin (standard

dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

PAC11 Average contribution of a RAM block during

a read operation

25.00

PAC12 Average contribution of a RAM block during

a write operation

30.00

PAC13 Dynamic contribution for PLL 2.60

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power

spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE) software.

ProASIC3 DC and Switching Characteristics

v1.3 2-11

Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices

Parameter

Definition Device Specific Static Power (mW)

A3P1000

A3P600

A3P400

A3P250

A3P125

A3P060

A3P030

A3P015

PDC1 Array static power in Active mode See Table 2-7 on page 2-6.

PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

PDC4 Static PLL contribution 2.55 mW

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel

ProASIC3 DC and Switching Characteristics

2-12 v1.3

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on

page 2-14.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-17 on page 2-14.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-17 on page 2-14. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in

Table 2-16 on page 2-14.

NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-16

on page 2-14.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

FCLK is the global clock signal frequency.

ProASIC3 DC and Switching Characteristics

v1.3 2-13

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-14.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on

page 2-14.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated

by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include

each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL

contribution.

ProASIC3 DC and Switching Characteristics

2-14 v1.3

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3 DC and Switching Characteristics

v1.3 2-15

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case

VCC =1.425V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

LVTTL Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

tPD = 0.56 ns tPD = 0.49 ns

tDP = 1.34 ns

tPD = 0.87 ns tDP = 2.64 ns (Advanced I/O Banks)

tPD = 0.47 ns

tDP = 3.66 ns (Advanced I/O Banks)

tPD = 0.47 ns tDP = 3.97 ns (Advanced I/O Banks)

tPD = 0.47 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tCLKQ = 0.55 ns tOCLKQ = 0.59 ns

tSUD = 0.43 ns tOSUD = 0.31 ns

tDP = 2.64 ns

(Advanced I/O Banks)

tPY = 0.76 ns (Advanced I/O Banks)

tPY = 1.20 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.05 ns

ProASIC3 DC and Switching Characteristics

2-16 v1.3

Figure 2-3 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3 DC and Switching Characteristics

v1.3 2-17

Figure 2-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3 DC and Switching Characteristics

2-18 v1.3

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3 DC and Switching Characteristics

v1.3 2-19

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8

1.5 V LVCMOS 4 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 44

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V LVCMOS 2 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 22

Note: Currents are measured at 85°C junction temperature.

ProASIC3 DC and Switching Characteristics

2-20 v1.3

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

Table 2-22 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

3.3 V PCI 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V PCI-X 0.285 * VCCI (RR)

0.615 * VCCI (FF)

Table 2-23 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3 DC and Switching Characteristics

v1.3 2-21

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,

Worst Case VCCI = 3.0 V

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 High 35 – 0.492.640.030.760.322.692.112.402.684.363.78 ns

2.5 V LVCMOS 12 High 35 – 0.492.660.030.980.322.712.562.472.574.384.23 ns

1.8 V LVCMOS 12 High 35 – 0.492.640.030.910.322.692.272.763.054.363.94 ns

1.5 V LVCMOS 12 High 35 – 0.493.050.031.070.323.102.672.953.144.774.34 ns

3.3 V PCI Per PCI spec. High 10 25 20.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

3.3 V PCI-X Per PCI-X spec. High 10 25 20.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

LVDS 24 High––0.491.370.031.20–––––––n

LVPECL 24 High––0.491.340.031.05–––––––ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

ProASIC3 DC and Switching Characteristics

2-22 v1.3

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case

VCCI =3.0V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 35 pF – 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

2.5 V LVCMOS 12 mA High 35 pF – 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

1.8 V LVCMOS 8 mA High 35 pF – 0.49 3.03 0.030.900.322.873.032.192.324.544.70 ns

1.5 V LVCMOS 4 mA High 35 pF – 0.49 3.61 0.031.060.323.353.612.262.345.025.28 ns

3.3 V PCI Per PCI spec. High 10 pF 25 20.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

3.3 V PCI-X Per PCI-X spec. High 10 pF 25 20.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,

Worst Case VCCI = 3.0 V

Standard I/O Banks

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 35 pF – 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

2.5 V LVCMOS 8 mA High 35 pF – 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

1.8 V LVCMOS 4 mA High 35 pF – 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

1.5 V LVCMOS 2 mA High 35 pF – 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

ProASIC3 DC and Switching Characteristics

v1.3 2-23

Detailed I/O DC Characteristics

Table 2-27 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-28 • I/O Output Buffer Maximum Resistances1

Applicable to Advanced I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3 DC and Switching Characteristics

2-24 v1.3

Table 2-29 • I/O Output Buffer Maximum Resistances 1

Applicable to Standard Plus I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 25 75

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3 DC and Switching Characteristics

v1.3 2-25

Table 2-30 • I/O Output Buffer Maximum Resistances1

Applicable to Standard I/O Banks

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

ProASIC3 DC and Switching Characteristics

2-26 v1.3

Table 2-32 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 127 132

24 mA 181 268

3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 127 132

24 mA 181 268

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

12 mA 74 65

16 mA 87 83

24 mA 124 169

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

6 mA 44 35

8 mA 51 45

12 mA 74 91

16 mA 74 91

1.5 V LVCMOS 2 mA 16 13

4 mA 33 25

6 mA 39 32

8 mA 55 66

12 mA 55 66

3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103

*TJ = 100°C

ProASIC3 DC and Switching Characteristics

v1.3 2-27

Table 2-33 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 109 103

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

12 mA 74 65

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

6 mA 44 35

8 mA 44 35

1.5 V LVCMOS 2 mA 16 13

4 mA 33 25

3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103

*TJ = 100°C

Table 2-34 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

1.5 V LVCMOS 2 mA 16 13

*TJ = 100°C

ProASIC3 DC and Switching Characteristics

2-28 v1.3

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-35 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

No requirement 10 ns * 10 years (100°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

ProASIC3 DC and Switching Characteristics

v1.3 2-29

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-37 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 23.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-38 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 23.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics

2-30 v1.3

Table 2-39 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 23.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-6 • AC Loading

Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.435

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 DC and Switching Characteristics

v1.3 2-31

Timing Characteristics

Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 9.20 0.05 1.22 0.51 9.37 7.91 3.18 3.14 12.05 10.60 ns

Std. 0.66 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns

–1 0.56 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns

–2 0.49 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns

6 mA –F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns

Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns

–1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns

–2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns

8 mA –F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns

Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns

–1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns

–2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns

12 mA –F 0.79 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns

Std. 0.66 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns

–1 0.56 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns

–2 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

16 mA –F 0.79 4.00 0.05 1.22 0.51 4.08 3.08 3.92 4.42 6.76 5.77 ns

Std. 0.66 3.33 0.04 1.02 0.43 3.39 2.56 3.26 3.68 5.63 4.80 ns

–1 0.56 2.83 0.04 0.86 0.36 2.89 2.18 2.77 3.13 4.79 4.08 ns

–2 0.49 2.49 0.03 0.76 0.32 2.53 1.91 2.44 2.75 4.20 3.58 ns

24 mA –F 0.79 3.69 0.05 1.22 0.51 3.76 2.54 3.99 4.88 6.45 5.23 ns

Std. 0.66 3.08 0.04 1.02 0.43 3.13 2.12 3.32 4.06 5.37 4.35 ns

–1 0.56 2.62 0.04 0.86 0.36 2.66 1.80 2.83 3.45 4.57 3.70 ns

–2 0.49 2.30 0.03 0.76 0.32 2.34 1.58 2.48 3.03 4.01 3.25 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-32 v1.3

Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns

Std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns

–1 0.56 8.72 0.04 0.86 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns

–2 0.49 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns

6 mA –F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns

Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns

–1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns

–2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns

8 mA –F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns

Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns

–1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns

–2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns

12 mA –F 0.79 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns

Std. 0.66 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns

–1 0.56 4.75 0.04 0.86 0.36 4.84 4.14 2.73 2.91 6.74 6.05 ns

–2 0.49 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns

16 mA –F 0.79 6.25 0.05 1.22 0.51 6.37 5.48 3.91 4.22 9.06 8.17 ns

Std. 0.66 5.21 0.04 1.02 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns

–1 0.56 4.43 0.04 0.86 0.36 4.51 3.88 2.77 2.99 6.41 5.79 ns

–2 0.49 3.89 0.03 0.76 0.32 3.96 3.41 2.43 2.62 5.63 5.08 ns

24 mA –F 0.79 5.83 0.05 1.22 0.51 5.93 5.46 3.98 4.67 8.62 8.15 ns

Std. 0.66 4.85 0.04 1.02 0.43 4.94 4.54 3.32 3.88 7.18 6.78 ns

–1 0.56 4.13 0.04 0.86 0.36 4.20 3.87 2.82 3.30 6.10 5.77 ns

–2 0.49 3.62 0.03 0.76 0.32 3.69 3.39 2.48 2.90 5.36 5.06 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-33

Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 8.65 0.05 1.20 0.51 8.81 7.55 2.73 2.81 11.50 10.24 ns

Std. 0.66 7.20 0.04 1.00 0.43 7.34 6.29 2.27 2.34 9.57 8.52 ns

–1 0.56 6.13 0.04 0.85 0.36 6.24 5.35 1.93 1.99 8.14 7.25 ns

–2 0.49 5.38 0.03 0.75 0.32 5.48 4.69 1.70 1.75 7.15 6.36 ns

6 mA –F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns

Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns

–1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns

–2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns

8 mA –F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns

Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns

–1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns

–2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns

12 mA –F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns

Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns

–1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns

–2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

16 mA –F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns

Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns

–1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns

–2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

Notes:

1. Software default selection highlighted in gray.

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-34 v1.3

Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 11.63 0.05 1.20 0.51 11.84 10.12 2.74 2.65 14.53 12.81 ns

Std. 0.66 9.68 0.04 1.00 0.43 9.86 8.42 2.28 2.21 12.09 10.66 ns

–1 0.56 8.23 0.04 0.85 0.36 8.39 7.17 1.94 1.88 10.29 9.07 ns

–2 0.49 7.23 0.03 0.75 0.32 7.36 6.29 1.70 1.65 9.03 7.96 ns

6 mA –F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns

Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns

–1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns

–2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns

8 mA –F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns

Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns

–1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns

–2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns

12 mA –F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns

Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns

–1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns

–2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 ns

16 mA –F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns

Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns

–1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns

–2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-35

Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns

Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns

–1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns

–2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns

4 mA –F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns

Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns

–1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns

–2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns

6 mA –F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns

Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns

–1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns

–2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

8 mA –F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns

Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns

–1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns

–2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-36 v1.3

Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns

Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns

–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns

–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns

4 mA –F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns

Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns

–1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns

–2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns

6 mA –F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns

Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns

–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns

–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns

8 mA –F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns

Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns

–1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns

–2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-37

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

16 mA –0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10

24 mA –0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics

2-38 v1.3

Table 2-49 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.235

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 DC and Switching Characteristics

v1.3 2-39

Timing Characteristics

Table 2-51 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.22 2.77 12.09 13.09 ns

Std. 0.60 8.66 0.04 1.31 0.43 7.83 8.66 2.68 2.30 10.07 10.90 ns

–1 0.51 7.37 0.04 1.11 0.36 6.66 7.37 2.28 1.96 8.56 9.27 ns

–2 0.45 6.47 0.03 0.98 0.32 5.85 6.47 2.00 1.72 7.52 8.14 ns

6 mA –F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns

Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns

–1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns

–2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns

8 mA –F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns

Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns

–1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns

–2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns

12 mA –F 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns

Std. 0.60 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns

–1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns

–2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

16 mA –F 0.72 4.03 0.05 1.57 0.51 4.10 3.68 4.04 4.26 6.79 6.36 ns

Std. 0.60 3.35 0.04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns

–1 0.51 2.85 0.04 1.11 0.36 2.90 2.60 2.86 3.02 4.81 4.51 ns

–2 0.45 2.50 0.03 0.98 0.32 2.55 2.29 2.51 2.65 4.22 3.96 ns

24 mA –F 0.72 3.71 0.05 1.57 0.51 3.78 2.93 4.13 4.80 6.47 5.62 ns

Std. 0.60 3.09 0.04 1.31 0.43 3.15 2.44 3.44 4.00 5.38 4.68 ns

–1 0.51 2.63 0.04 1.11 0.36 2.68 2.08 2.92 3.40 4.58 3.98 ns

–2 0.45 2.31 0.03 0.98 0.32 2.35 1.82 2.57 2.98 4.02 3.49 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-40 v1.3

Table 2-52 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.72 13.69 0.05 1.57 0.51 13.48 13.69 3.22 2.65 16.16 16.38 ns

Std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns

–1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns

–2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns

6 mA –F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns

Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns

–1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns

–2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns

8 mA –F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns

Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns

–1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns

–2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns

12 mA –F 0.72 7.42 0.05 1.57 0.51 7.56 7.11 3.97 3.99 10.25 9.80 ns

Std. 0.60 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns

–1 0.51 5.26 0.04 1.11 0.36 5.35 5.03 2.81 2.83 7.26 6.94 ns

–2 0.45 4.61 0.03 0.98 0.32 4.70 4.42 2.47 2.48 6.37 6.09 ns

16 mA –F 0.72 6.92 0.05 1.57 0.51 7.05 6.64 4.04 4.13 9.74 9.32 ns

Std. 0.60 5.76 0.04 1.31 0.43 5.87 5.53 3.36 3.44 8.11 7.76 ns

–1 0.51 4.90 0.04 1.11 0.36 4.99 4.70 2.86 2.92 6.90 6.60 ns

–2 0.45 4.30 0.03 0.98 0.32 4.38 4.13 2.51 2.57 6.05 5.80 ns

24 mA –F 0.72 6.61 0.05 1.57 0.51 6.61 6.61 4.13 4.65 9.30 9.30 ns

Std. 0.60 5.51 0.04 1.31 0.43 5.50 5.51 3.43 3.87 7.74 7.74 ns

–1 0.51 4.68 0.04 1.11 0.36 4.68 4.68 2.92 3.29 6.58 6.59 ns

–2 0.45 4.11 0.03 0.98 0.32 4.11 4.11 2.56 2.89 5.78 5.78 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-41

Table 2-53 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 9.94 0.05 1.56 0.51 8.90 9.94 2.70 2.49 11.58 12.63 ns

Std. 0.66 8.28 0.04 1.30 0.43 7.41 8.28 2.25 2.07 9.64 10.51 ns

–1 0.56 7.04 0.04 1.10 0.36 6.30 7.04 1.92 1.76 8.20 8.94 ns

–2 0.49 6.18 0.03 0.97 0.32 5.53 6.18 1.68 1.55 7.20 7.85 ns

6 mA –F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns

Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns

–1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns

–2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns

8 mA –F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns

Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns

–1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns

–2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns

12 mA –F 0.79 3.85 0.05 1.56 0.51 3.92 3.77 3.39 3.74 6.61 6.46 ns

Std. 0.66 3.21 0.04 1.30 0.43 3.27 3.14 2.82 3.11 5.50 5.38 ns

–1 0.56 2.73 0.04 1.10 0.36 2.78 2.67 2.40 2.65 4.68 4.57 ns

–2 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-42 v1.3

Table 2-54 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 13.02 0.05 1.56 0.51 12.78 13.02 2.71 2.39 15.46 15.71 ns

Std. 0.66 10.84 0.04 1.30 0.43 10.64 10.84 2.26 1.99 12.87 13.08 ns

–1 0.56 9.22 0.04 1.10 0.36 9.05 9.22 1.92 1.69 10.95 11.12 ns

–2 0.49 8.10 0.03 0.97 0.32 7.94 8.10 1.68 1.49 9.61 9.77 ns

6 mA –F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns

Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns

–1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns

–2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns

8 mA –F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns

Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns

–1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns

–2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns

12 mA –F 0.79 6.76 0.05 1.56 0.51 6.89 6.61 3.40 3.62 9.57 9.30 ns

Std. 0.66 5.63 0.04 1.30 0.43 5.73 5.51 2.83 3.01 7.97 7.74 ns

–1 0.56 4.79 0.04 1.10 0.36 4.88 4.68 2.41 2.56 6.78 6.59 ns

–2 0.49 4.20 0.03 0.97 0.32 4.28 4.11 2.11 2.25 5.95 5.78 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-43

Table 2-55 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns

Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns

–1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns

–2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns

4 mA –F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns

Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns

–1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns

–2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns

6 mA –F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns

Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns

–1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns

–2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

8 mA –F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns

Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns

–1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns

–2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-44 v1.3

Table 2-56 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns

Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns

–1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns

–2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns

4 mA –F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns

Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns

–1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns

–2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns

6 mA –F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns

Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns

–1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns

–2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns

8 mA –F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns

Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns

–1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns

–2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-45

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 51 45 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 74 91 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 16 16 74 91 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-58 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 44 35 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics

2-46 v1.3

Table 2-59 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.935

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 DC and Switching Characteristics

v1.3 2-47

Timing Characteristics

Table 2-61 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns

Std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns

–1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns

–2 0.49 8.86 0.03 0.91 0.32 6.82 8.86 2.07 1.24 8.49 10.53 ns

4 mA –F 0.79 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns

Std. 0.66 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns

–1 0.56 5.88 0.04 1.04 0.36 4.99 5.88 2.74 2.41 6.89 7.78 ns

–2 0.49 5.16 0.03 0.91 0.32 4.38 5.16 2.41 2.12 6.05 6.83 ns

6 mA –F 0.79 5.34 0.05 1.46 0.51 5.02 5.34 4.24 4.06 7.71 8.03 ns

Std. 0.66 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns

–1 0.56 3.78 0.04 1.04 0.36 3.56 3.78 3.00 2.88 5.46 5.69 ns

–2 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 ns

8 mA –F 0.79 4.71 0.05 1.46 0.51 4.72 4.71 4.32 4.23 7.40 7.40 ns

Std. 0.66 3.92 0.04 1.22 0.43 3.93 3.92 3.60 3.52 6.16 6.16 ns

–1 0.56 3.34 0.04 1.04 0.36 3.34 3.34 3.06 3.00 5.24 5.24 ns

–2 0.49 2.93 0.03 0.91 0.32 2.93 2.93 2.69 2.63 4.60 4.60 ns

12 mA –F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns

Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns

–1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns

–2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

16 mA –F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns

Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns

–1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns

–2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-48 v1.3

Table 2-62 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns

Std. 0.66 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns

–1 0.56 13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns

–2 0.49 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns

4 mA –F 0.79 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns

Std. 0.66 10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns

–1 0.56 8.91 0.04 1.04 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns

–2 0.49 7.82 0.03 0.91 0.32 7.77 7.82 2.41 2.04 9.44 9.49 ns

6 mA –F 0.79 9.67 0.05 1.46 0.51 9.85 9.42 4.25 3.93 12.53 12.11 ns

Std. 0.66 8.05 0.04 1.22 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns

–1 0.56 6.85 0.04 1.04 0.36 6.97 6.67 3.01 2.78 8.88 8.57 ns

–2 0.49 6.01 0.03 0.91 0.32 6.12 5.86 2.64 2.44 7.79 7.53 ns

8 mA –F 0.79 9.01 0.05 1.46 0.51 9.18 8.77 4.33 4.10 11.87 11.45 ns

Std. 0.66 7.50 0.04 1.22 0.43 7.64 7.30 3.61 3.41 9.88 9.53 ns

–1 0.56 6.38 0.04 1.04 0.36 6.50 6.21 3.07 2.90 8.40 8.11 ns

–2 0.49 5.60 0.03 0.91 0.32 5.71 5.45 2.69 2.55 7.38 7.12 ns

12 mA –F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns

Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns

–1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns

–2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns

16 mA –F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns

Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns

–1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns

–2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-49

Table 2-63 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 13.61 0.05 1.44 0.51 10.48 13.61 2.70 1.83 13.17 16.30 ns

Std. 0.66 11.33 0.04 1.20 0.43 8.72 11.33 2.24 1.52 10.96 13.57 ns

–1 0.56 9.64 0.04 1.02 0.36 7.42 9.64 1.91 1.29 9.32 11.54 ns

–2 0.49 8.46 0.03 0.90 0.32 6.51 8.46 1.68 1.14 8.18 10.13 ns

4 mA –F 0.79 7.79 0.05 1.44 0.51 6.58 7.79 3.18 3.13 9.27 10.47 ns

Std. 0.66 6.48 0.04 1.20 0.43 5.48 6.48 2.65 2.60 7.72 8.72 ns

–1 0.56 5.51 0.04 1.02 0.36 4.66 5.51 2.25 2.21 6.56 7.42 ns

–2 0.49 4.84 0.03 0.90 0.32 4.09 4.84 1.98 1.94 5.76 6.51 ns

6 mA –F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns

Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns

–1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns

–2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

8 mA –F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns

Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns

–1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns

–2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-50 v1.3

Table 2-64 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 17.78 0.05 1.44 0.51 16.21 17.78 2.70 1.76 18.90 20.47 ns

Std. 0.66 14.80 0.04 1.20 0.43 13.49 14.80 2.25 1.46 15.73 17.04 ns

–1 0.56 12.59 0.04 1.02 0.36 11.48 12.59 1.91 1.25 13.38 14.49 ns

–2 0.49 11.05 0.03 0.90 0.32 10.08 11.05 1.68 1.09 11.75 12.72 ns

4 mA –F 0.79 11.89 0.05 1.44 0.51 11.69 11.89 3.19 3.00 14.38 14.58 ns

Std. 0.66 9.90 0.04 1.20 0.43 9.73 9.90 2.65 2.50 11.97 12.13 ns

–1 0.56 8.42 0.04 1.02 0.36 8.28 8.42 2.26 2.12 10.18 10.32 ns

–2 0.49 7.39 0.03 0.90 0.32 7.27 7.39 1.98 1.86 8.94 9.06 ns

6 mA –F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns

Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns

–1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns

–2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns

8 mA –F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns

Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns

–1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns

–2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-65 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 13.47 0.05 1.44 0.51 10.25 13.47 2.39 1.45 ns

Std. 0.66 11.21 0.04 1.20 0.43 8.53 11.21 1.99 1.21 ns

–1 0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03 ns

–2 0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90 ns

4 mA –F 0.79 7.62 0.05 1.44 0.51 6.46 7.62 2.89 2.98 ns

Std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns

–1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns

–2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-51

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-66 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 18.03 0.05 1.44 0.51 15.80 18.03 2.40 2.40 ns

Std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns

–1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns

–2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns

4 mA –F 0.79 12.13 0.05 1.44 0.51 11.48 12.13 2.90 2.85 ns

Std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns

–1 0.56 8.59 0.04 1.02 0.36 8.13 8.59 2.05 2.02 ns

–2 0.49 7.54 0.03 0.90 0.32 7.13 7.54 1.80 1.77 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-67 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10

6 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10

8 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10

12 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics

2-52 v1.3

Table 2-68 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 22 0 0 1010

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 0 0 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 1.5 0.75 35

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 DC and Switching Characteristics

v1.3 2-53

Timing Characteristics

Table 2-71 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP t

DIN t

PY t

EOUT t

ZL t

ZH t

LZ t

HZ t

ZLS t

ZHS Units

2 mA –F 0.79 10.05 0.05 1.73 0.51 8.20 10.05 4.07 3.32 10.88 12.73 ns

Std. 0.66 8.36 0.04 1.44 0.43 6.82 8.36 3.39 2.77 9.06 10.60 ns

–1 0.56 7.11 0.04 1.22 0.36 5.80 7.11 2.88 2.35 7.71 9.02 ns

–2 0.49 6.24 0.03 1.07 0.32 5.10 6.24 2.53 2.06 6.76 7.91 ns

4 mA –F 0.79 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns

Std. 0.66 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns

–1 0.56 4.52 0.04 1.22 0.36 4.13 4.52 3.18 2.89 6.03 6.42 ns

–2 0.49 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns

6 mA –F 0.79 5.61 0.05 1.73 0.51 5.46 5.61 4.59 4.28 8.15 8.29 ns

Std. 0.66 4.67 0.04 1.44 0.43 4.55 4.67 3.82 3.56 6.78 6.90 ns

–1 0.56 3.97 0.04 1.22 0.36 3.87 3.97 3.25 3.03 5.77 5.87 ns

–2 0.49 3.49 0.03 1.07 0.32 3.40 3.49 2.85 2.66 5.07 5.16 ns

8 mA –F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns

Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns

–1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns

–2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

12 mA –F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns

Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns

–1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns

–2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-54 v1.3

Table 2-72 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04 ns

Std. 0.66 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns

–1 0.56 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns

–2 0.49 9.55 0.03 1.07 0.32 9.57 9.55 2.54 1.97 11.24 11.22 ns

4 mA –F 0.79 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns

Std. 0.66 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns

–1 0.56 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns

–2 0.49 7.47 0.03 1.07 0.32 7.61 7.13 2.80 2.44 9.28 8.80 ns

6 mA –F 0.79 11.21 0.05 1.73 0.51 11.42 10.68 4.60 4.12 14.11 13.37 ns

Std. 0.66 9.33 0.04 1.44 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns

–1 0.56 7.94 0.04 1.22 0.36 8.09 7.56 3.26 2.92 9.99 9.47 ns

–2 0.49 6.97 0.03 1.07 0.32 7.10 6.64 2.86 2.56 8.77 8.31 ns

8 mA –F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns

Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns

–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns

–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns

12 mA –F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns

Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns

–1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns

–2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-55

Table 2-73 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 9.41 0.05 1.71 0.51 7.71 9.41 3.25 3.06 10.40 12.09 ns

Std. 0.66 7.83 0.04 1.42 0.43 6.42 7.83 2.71 2.55 8.65 10.07 ns

–1 0.56 6.66 0.04 1.21 0.36 5.46 6.66 2.31 2.17 7.36 8.56 ns

–2 0.49 5.85 0.03 1.06 0.32 4.79 5.85 2.02 1.90 6.46 7.52 ns

4 mA –F 0.79 5.81 0.05 1.71 0.51 5.39 5.81 3.64 3.76 8.08 8.50 ns

Std. 0.66 4.84 0.04 1.42 0.43 4.49 4.84 3.03 3.13 6.72 7.08 ns

–1 0.56 4.12 0.04 1.21 0.36 3.82 4.12 2.58 2.66 5.72 6.02 ns

–2 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-74 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.51 0.05 1.71 0.51 14.42 14.51 3.26 2.91 17.11 17.20 ns

Std. 0.66 12.08 0.04 1.42 0.43 12.01 12.08 2.72 2.43 14.24 14.31 ns

–1 0.56 10.27 0.04 1.21 0.36 10.21 10.27 2.31 2.06 12.12 12.18 ns

–2 0.49 9.02 0.03 1.06 0.32 8.97 9.02 2.03 1.81 10.64 10.69 ns

4 mA –F 0.79 11.15 0.05 1.71 0.51 11.35 10.71 3.65 3.60 14.04 13.40 ns

Std. 0.66 9.28 0.04 1.42 0.43 9.45 8.91 3.04 3.00 11.69 11.15 ns

–1 0.56 7.89 0.04 1.21 0.36 8.04 7.58 2.58 2.55 9.94 9.49 ns

–2 0.49 6.93 0.03 1.06 0.32 7.06 6.66 2.27 2.24 8.73 8.33 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-56 v1.3

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-10.

Table 2-75 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 9.18 0.05 1.70 0.51 7.58 9.18 2.94 2.94 ns

Std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns

–1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns

–2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-76 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units

2 mA –F 0.79 14.81 0.05 1.70 0.51 14.17 14.81 2.94 2.79 ns

Std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns

–1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns

–2 0.49 9.21 0.03 1.06 0.32 8.81 9.21 1.83 1.73 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-77 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1Max, mA1µA2µA2

Per PCI specification Per PCI curves 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-10 • AC Loading

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

ProASIC3 DC and Switching Characteristics

v1.3 2-57

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-78.

Timing Characteristics

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Table 2-79 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.30 5.97 5.03 ns

Std. 0.66 2.68 0.04 0.86 0.43 2.73 1.95 3.21 3.58 4.97 4.19 ns

–1 0.56 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 4.22 3.56 ns

–2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-80 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.77 0.05 1.02 0.51 2.82 2.05 3.35 3.87 5.51 4.73 ns

Std. 0.66 2.31 0.04 0.85 0.43 2.35 1.70 2.79 3.22 4.59 3.94 ns

–1 0.56 1.96 0.04 0.72 0.36 2.00 1.45 2.37 2.74 3.90 3.35 ns

–2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-58 v1.3

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

140 Ω100 Ω

Z0 = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

ProASIC3 DC and Switching Characteristics

v1.3 2-59

Timing Characteristics

Table 2-81 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 1 2.375 2.5 2.625 V

VOL Output Low Voltage 0.9 1.075 1.25 V

VOH Output High Voltage 1.25 1.425 1.6 V

IOL 4 Output Lower Current 0.65 0.91 1.16 mA

IOH 4 Output High Current 0.65 0.91 1.16 mA

VI Input Voltage 0 2.925 V

IIH 3Input High Leakage Current 10 µA

IIL 3Input Low Leakage Current 10 µA

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common Mode Voltage 1.125 1.25 1.375 V

VICM Input Common Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 2 100 350 mV

Notes:

1. ±5%

2. Differential input voltage = ±350 mV.

3. Currents are measured at 85°C junction temperature.

4. IOL/I

OH defined by VODIFF/(Resistor Network).

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.075 1.325 Cross point

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Table 2-83 • LVDS

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.20 0.05 1.92 ns

Std. 0.66 1.83 0.04 1.60 ns

–1 0.56 1.56 0.04 1.36 ns

–2 0.49 1.37 0.03 1.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-60 v1.3

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output

buffer delays are available in the LVDS section in Table 2-83.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

RS=60Ω and RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

RTRT

BIBUF_LVDS

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

stub

ProASIC3 DC and Switching Characteristics

v1.3 2-61

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Timing Characteristics

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-84 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V)

1.64 1.94 Cross point

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

187 W 100 Ω

Z0 = 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

Table 2-86 • LVPECL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.16 0.05 1.69 ns

Std. 0.66 1.80 0.04 1.40 ns

–1 0.56 1.53 0.04 1.19 ns

–2 0.49 1.34 0.03 1.05 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-62 v1.3

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC3 DC and Switching Characteristics

v1.3 2-63

Table 2-87 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-14 on page 2-62 for more information.

ProASIC3 DC and Switching Characteristics

2-64 v1.3

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

ProASIC3 DC and Switching Characteristics

v1.3 2-65

Table 2-88 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-15 on page 2-64 for more information.

ProASIC3 DC and Switching Characteristics

2-66 v1.3

Input Register

Timing Characteristics

Figure 2-16 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50% 50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-89 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns

tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-67

Output Register

Timing Characteristics

Figure 2-17 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

OSUE

50%

OSUD

OHD

50% 50%

OCLKQ

OHE

ORECPRE

OREMPRE

ORECCLR

OREMCLR

OWCLR

OWPRE

OPRE2Q

OCLR2Q

OCKMPWH

OCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-90 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns

tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data

0.22 0.25 0.30 0.36 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data

0.22 0.25 0.30 0.36 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-68 v1.3

Output Enable Register

Figure 2-18 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

tOESUE

50%

tOESUD tOEHD

50% 50%

tOECLKQ

tOEHE

tOERECPRE

tOEREMPRE

tOERECCLR tOEREMCLR

tOEWCLR

tOEWPRE

tOEPRE2Q tOECLR2Q

tOECKMPWH tOECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

ProASIC3 DC and Switching Characteristics

v1.3 2-69

Timing Characteristics

Table 2-91 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 0.95 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 0.50 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 0.70 ns

tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable

0.22 0.25 0.30 0.36 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable

0.22 0.25 0.30 0.36 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 0.57 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-70 v1.3

DDR Module Specifications

Input DDR Module

Figure 2-19 • Input DDR Timing Model

Table 2-92 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3 DC and Switching Characteristics

v1.3 2-71

Timing Characteristics

Figure 2-20 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

246

357

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 2-93 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

Parameter Description –2–1Std. –FUnits

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 0.44 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 0.62 ns

tDDRISUD Data Setup for Input DDR (Fall) 0.25 0.28 0.33 0.40 ns

Data Setup for Input DDR (Rise) 0.25 0.28 0.33 0.40 ns

tDDRIHD Data Hold for Input DDR (Fall) 0.00 0.00 0.00 0.00 ns

Data Hold for Input DDR (Rise) 0.00 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 0.74 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 0.92 ns

tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 0.57 ns

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 0.52 ns

FDDRIMAX Maximum Frequency for Input DDR MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-72 v1.3

Output DDR Module

Figure 2-21 • Output DDR Timing Model

Table 2-94 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3 DC and Switching Characteristics

v1.3 2-73

Timing Characteristics

Figure 2-22 • Output DDR Timing Diagram

116

910

28 3 9

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

7104

Table 2-95 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 1.13 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 1.29 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 0.57 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 0.52 ns

FDDOMAX Maximum Frequency for the Output DDR TBD TBD TBD TBD MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-74 v1.3

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section,

timing characteristics are presented for a sample of the library. For more details, refer to the

Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide.

Figure 2-23 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3

NAND2

ProASIC3 DC and Switching Characteristics

v1.3 2-75

Figure 2-24 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC3 DC and Switching Characteristics

2-76 v1.3

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are

presented for a representative sample from the library. For more details, refer to the Fusion,

IGLOO/e, and ProASIC3/E Macro Library Guide.

Table 2-96 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. –F Units

INV Y = !A tPD 0.40 0.46 0.54 0.65 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 0.76 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 0.76 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 0.78 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 0.78 ns

XOR2 Y = A ⊕ Bt

PD 0.74 0.84 0.99 1.19 ns

MAJ3 Y = MAJ(A, B, C) tPD 0.70 0.79 0.93 1.12 ns

XOR3 Y = A ⊕ B ⊕ Ct

PD 0.87 1.00 1.17 1.41 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 0.81 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 0.90 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Figure 2-25 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC3 DC and Switching Characteristics

v1.3 2-77

Timing Characteristics

Figure 2-26 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50% 50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-97 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 0.89 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 0.69 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 0.73 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 0.52 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 0.57 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-78 v1.3

Global Resource Characteristics

A3P250 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing.

The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250

device. It is used to drive all D-flip-flops in the device.

Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC3 DC and Switching Characteristics

v1.3 2-79

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be

driven and conditioned internally by the CCC module. For more details on clock conditioning

capabilities, refer to the "Clock Conditioning Circuits" section on page 2-83. Table 2-99 to

Table 2-105 on page 2-82 present minimum and maximum global clock delays within each device.

Minimum and maximum delays are measured with minimum and maximum loading.

Timing Characteristics

Table 2-98 • A3P015 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2

Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.66 0.81 0.75 0.92 0.88 1.08 1.06 1.30 ns

tRCKH Input HIGH Delay for Global Clock 0.67 0.84 0.76 0.96 0.89 1.13 1.07 1.36 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.18 0.21 0.25 0.30 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-99 • A3P030 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31 ns

tRCKH Input HIGH Delay for Global Clock 0.680.850.770.970.911.141.091.37 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.18 0.21 0.24 0.29 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-80 v1.3

Table 2-100 • A3P060 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns

tRCKH Input HIGH Delay for Global Clock 0.700.960.801.090.941.281.131.54 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-101 • A3P125 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns

tRCKH Input HIGH Delay for Global Clock 0.761.020.871.161.021.371.231.64 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-81

Table 2-102 • A3P250 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns

tRCKH Input HIGH Delay for Global Clock 0.781.040.891.181.041.391.251.66 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-103 • A3P400 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

tRCKH Input HIGH Delay for Global Clock 0.861.110.981.271.151.491.381.79 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock Mhz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-82 v1.3

Table 2-104 • A3P600 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

tRCKH Input HIGH Delay for Global Clock 0.861.110.981.271.151.491.381.79 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-105 • A3P1000 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns

tRCKH Input HIGH Delay for Global Clock 0.931.191.061.351.241.591.491.91 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-83

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-106 • ProASIC3 CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Serial Clock (SCLK) for Dynamic PLL1125 MHz

Delay Increments in Programmable Delay Blocks2, 3 200 ps

Number of Programmable Values in Each Programmable

Delay Block

Input Period Jitter 1.5 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

Network

Used

3 Global

Networks

Used

0.75 MHz to 24 MHz 0.50% 0.70%

24 MHz to 100 MHz 1.00% 1.20%

100 MHz to 250 MHz 1.75% 2.00%

250 MHz to 350 MHz 2.50% 5.60%

Acquisition Time

(A3P250 and A3P1000 only) LockControl = 0 300 µs

LockControl = 1 300 µs

(all other dies) LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter 5

(A3P250 and A3P1000 only) LockControl = 0 1.6 ns

LockControl = 1 1.6 ns

(all other dies) LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay 12, 3 0.6 5.56 ns

Delay Range in Block: Programmable Delay 22, 3 0.025 5.56 ns

Delay Range in Block: Fixed Delay2, 3 2.2 ns

Notes:

1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific

junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.

3. TJ = 25°C, VCC = 1.5 V

4. The A3P030 device does not contain a PLL.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL

input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by

the period jitter parameter.

ProASIC3 DC and Switching Characteristics

2-84 v1.3

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.

Figure 2-28 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC3 DC and Switching Characteristics

v1.3 2-85

Embedded SRAM and FIFO Characteristics

SRAM

Figure 2-29 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3 DC and Switching Characteristics

2-86 v1.3

Timing Waveforms

Figure 2-30 • RAM Read for Pass-Through Output

Figure 2-31 • RAM Read for Pipelined Output

CLK

ADD

BLK_B

WEN_B

CYC

CKH

CKL

BKS

ENS

ENH

DOH1

BKH

CKQ1

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC3 DC and Switching Characteristics

v1.3 2-87

Figure 2-32 • RAM Write, Output Retained (WMODE = 0)

Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1)

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS tENH

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

(pass-through) DI1

DnDI0

(pipelined) DI0DI1

DI2

ProASIC3 DC and Switching Characteristics

2-88 v1.3

Figure 2-34 • Write Access after Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DI2

DO2

(pass-through)

DO2

(pipelined)

CCKH

CKQ1

CKQ2

DnD0

A0A4

ProASIC3 DC and Switching Characteristics

v1.3 2-89

Figure 2-35 • Read Access after Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DO2

(pass-through)

DO2

(pipelined)

WRO

CKQ1

CKQ2

A0A1A4

DnD0

D0D1

ProASIC3 DC and Switching Characteristics

2-90 v1.3

Figure 2-36 • Write Access after Read onto Same Address

Figure 2-37 • RAM Reset

CKQ1

CKQ2

CCKH

CLK1

ADD1

WEN_B1

DO1

(pass-through)

DO1

(pipelined)

CLK2

ADD2

DI2

WEN_B2

D0D1

CLK

RESET_B

DO D

CYC

CKH

CKL

RSTBQ

ProASIC3 DC and Switching Characteristics

v1.3 2-91

Timing Characteristics

Table 2-107 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address setup time 0.25 0.28 0.33 0.40 ns

tAH Address hold time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B setup time 0.14 0.16 0.19 0.23 ns

tENH REN_B, WEN_B hold time 0.10 0.11 0.13 0.16 ns

tBKS BLK_B setup time 0.23 0.27 0.31 0.37 ns

tBKH BLK_B hold time 0.02 0.02 0.02 0.03 ns

tDS Input data (DI) setup time 0.18 0.21 0.25 0.29 ns

tDH Input data (DI) hold time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.36 2.68 3.15 3.79 ns

Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 1.79 2.03 2.39 2.87 ns

tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write

on same address

TBDTBDTBDTBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBDTBDTBDTBD ns

tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B minimum pulse width 0.21 0.24 0.29 0.34 ns

tCYC Clock cycle time 3.23 3.68 4.32 5.19 ns

FMAX Maximum frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-92 v1.3

Table 2-108 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address setup time 0.25 0.28 0.33 0.40 ns

tAH Address hold time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B setup time 0.13 0.15 0.17 0.21 ns

tENH REN_B, WEN_B hold time 0.10 0.11 0.13 0.16 ns

tDS Input data (DI) setup time 0.18 0.21 0.25 0.29 ns

tDH Input data (DI) hold time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns

tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write

on same address

TBDTBDTBDTBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBDTBDTBDTBD ns

tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to data out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B minimum pulse width 0.21 0.24 0.29 0.34 ns

tCYC Clock cycle time 3.23 3.68 4.32 5.19 ns

FMAX Maximum frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-93

FIFO

Figure 2-38 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC3 DC and Switching Characteristics

2-94 v1.3

Timing Waveforms

Figure 2-39 • FIFO Reset

Figure 2-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A

)

MPWRSTB

RSTFG

RSTCK

RSTAF

RCLK/

WCLK

RESET_B

EMPTY

AEMPTY

WA/RA

(Address Counter)

RSTFG

RSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

tCKAF

tRCKEF

EMPTY

AEMPTY

tCYC

WA/RA

(Address Counter)

ProASIC3 DC and Switching Characteristics

v1.3 2-95

Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion

Figure 2-42 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 2-43 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

tRCKEF

tCKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

tWCKF

tCKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC3 DC and Switching Characteristics

2-96 v1.3

Timing Characteristics

Table 2-109 • FIFO (for all dies except A3P250)

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 1.34 1.52 1.79 2.15 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.921.051.231.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

v1.3 2-97

Table 2-110 • FIFO (for A3P250 only, aspect-ratio-dependent)

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 3.26 3.71 4.36 5.24 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.921.051.231.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC3 DC and Switching Characteristics

2-98 v1.3

Table 2-111 • A3P250 FIFO 512×8

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 3.75 4.27 5.02 6.04 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.921.051.231.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC3 DC and Switching Characteristics

v1.3 2-99

Table 2-112 • A3P250 FIFO 1k×4

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.05 4.61 5.42 6.52 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC3 DC and Switching Characteristics

2-100 v1.3

Table 2-113 • A3P250 FIFO 2k×2

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.39 5.00 5.88 7.06 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency for FIFO 310 272 231 193 MHz

ProASIC3 DC and Switching Characteristics

v1.3 2-101

Table 2-114 • A3P250 FIFO 4k×1

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 4.86 5.53 6.50 7.81 ns

tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

ProASIC3 DC and Switching Characteristics

2-102 v1.3

Embedded FlashROM Characteristics

Timing Characteristics

Figure 2-44 • Timing Diagram

HOLD

CKQ2

CLK

Address

Data D

Table 2-115 • Embedded FlashROM Access Time

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 21.42 24.40 28.68 ns

FMAX Maximum Clock Frequency 15 15 15 MHz

ProASIC3 DC and Switching Characteristics

v1.3 2-103

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays

to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-15 for more details.

Timing Characteristics

Table 2-116 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns

tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns

tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns

tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns

tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 ns

tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns

FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz

tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns

tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns

tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6

for derating values.

ProASIC3 DC and Switching Characteristics

2-104 v1.3

Part Number and Revision Date

Part Number 51700097-002-3

Revised August 2008

List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Previous Version Changes in Current Version (v1.3) Page

v1.2

(June 2008)

TJ, Maximum Junction Temperature, was changed to 100° from 110º in the

"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum

Power Allowed has thus changed to 1.463 W from 1.951 W.

2-5

Values for the A3P015 device were added to Table 2-7 · Quiescent Supply

Current Characteristics.

2-6

Values for the A3P015 device were added to Table 2-14 · Different Components

Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14 was

removed. Table 2-15 · Different Components Contributing to the Static Power

Consumption in ProASIC3 Devices is new.

2-10,

2-11

The "PLL Contribution—PPLL" section was updated to change the PPLL formula

from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.

2-13

Both fall and rise values were included for tDDRISUD and tDDRIHD in

Table 2-93 · Input DDR Propagation Delays.

2-71

Table 2-98 · A3P015 Global Resource is new. 2-79

The typical value for Delay Increments in Programmable Delay Blocks was

changed from 160 to 200 in Table 2-106 · ProASIC3 CCC/PLL Specification.

2-83

v1.1

(January 2008)

Table note references were added to Table 2-2 · Recommended Operating

Conditions 1, and the order of the table notes was changed.

2-2

The title for Table 2-4 · Overshoot and Undershoot Limits 1 was modified to

remove "as measured on quiet I/Os." Table note 1 was revised to remove

"estimated SSO density over cycles." Table note 2 was revised to remove "refers

only to overshoot/undershoot limits for simultaneous switching I/Os."

2-3

The "Power per I/O Pin" section was updated to include 3 additional tables

pertaining to input buffer power and output buffer power.

2-6

Table 2-29 · I/O Output Buffer Maximum Resistances 1 was revised to include

values for 3.3 V PCI/PCI-X.

2-24

Table 2-81 · LVDS Minimum and Maximum DC Input and Output Levels was

updated.

2-59

v1.0

(January 2008)

In Table 2-2 · Recommended Operating Conditions 1, TJ was listed in the symbol

column and was incorrect. It was corrected and changed to TA.

2-2

In Table 2-3 · Flash Programming Limits – Retention, Storage and Operating

Temperature1, Maximum Operating Junction Temperature was changed from

110°C to 100°C for both commercial and industrial grades.

2-2

The "PLL Behavior at Brownout Condition" section is new. 2-3

In the "PLL Contribution—PPLL" section, the following was deleted:

FCLKIN is the input clock frequency.

2-13

In Table 2-21 · Summary of Maximum and Minimum DC Input Levels, the note

was incorrect. It previously said TJ and it was corrected and changed to TA.

2-20

ProASIC3 DC and Switching Characteristics

v1.3 2-105

v1.0

(continued)

In Table 2-106 · ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1

are new.

2-83

Table 2-116 · JTAG 1532 was populated with the parameter data, which was not

in the previous version of the document.

2-103

v2.2

(July 2007)

This document was previously in datasheet v2.2. As a result of moving to the

handbook format, Actel restarted the version numbers so the new version

number is v1.0.

N/A

v2.1

(May 2007)

The TJ parameter in Table 3-2 • Recommended Operating Conditions was

changed to TA, ambient temperature, and table notes 4–6 were added.

3-2

v2.0

(April 2007)

Table 3-5 • Package Thermal Resistivities was updated with A3P1000

information. The note below the table is also new.

3-5

Advance v0.7

(January 2007)

The timing characteristics tables were updated. N/A

The "PLL Macro" section was updated to add information on the VCO and PLL

outputs during power-up.

2-15

The "PLL Macro" section was updated to include power-up information. 2-15

Table 2-11 • ProASIC3 CCC/PLL Specification was updated. 2-29

Figure 2-19 • Peak-to-Peak Jitter Definition is new. 2-18

The "SRAM and FIFO" section was updated with operation and timing

requirement information.

2-21

The "RESET" section was updated with read and write information. 2-25

The "Introduction" in the "Advanced I/Os" section was updated to include

information on input and output buffers being disabled.

2-28

PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible Standards. 2-29

In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance

descriptions were updated for levels 3 and 4.

2-34

Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3

Devices was updated.

2-64

Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–

Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum

current was updated from 4 x 52.7 to 5 x 52.7.

2-40

The "VCCPLF PLL Supply Voltage" section was updated. 2-50

The "VPUMP Programming Supply Voltage" section was updated. 2-50

The "GL Globals" section was updated to include information about direct input

into quadrant clocks.

2-51

VJTAG was deleted from the "TCK Test Clock" section. 2-51

In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK

was changed to TCK in note 2. Note 3 was also updated.

2-51

Ambient was deleted from Table 3-2 • Recommended Operating Conditions.

VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".

3-2

Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on

quiet I/Os)1.

3-2

Previous Version Changes in Current Version (v1.3) Page

ProASIC3 DC and Switching Characteristics

2-106 v1.3

Advance v0.7

(continued)

In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. 3-5

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was

updated.

3-6

Table 3-5 • Package Thermal Resistivities was updated. 3-5

Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input

Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were

updated.

3-17 to

3-17

Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings

(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software

Default Settings (Standard Plus) were updated.

3-20 to

3-20

Table 3-11 • Different Components Contributing to Dynamic Power

Consumption in ProASIC3 Devices was updated.

3-9

Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-

25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.

3-22 to

3-22

Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to

Commercial and Industrial Conditions was updated.

3-18

Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O

Short Currents IOSH/IOSL (Standard Plus) were updated.

3-24 to

3-26

The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O

Reliability was updated.

3-27

Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read

Access After Write onto Same Address, and Figure 3-35 • Write Access After

Read onto Same Address are new.

3-82 to

3-84

Figure 3-43 • Timing Diagram was updated. 3-96

Advance v0.5

(January 2006)

B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Figure 2-7 • Efficient Long-Line Resources was updated. 2-7

The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,

CLKBUF_LVDS/LVPECL, and CLKINT were updated.

2-16

The Delay Increments in the Programmable Delay Blocks specification in Figure

2-24 • ProASIC3E CCC Options.

2-24

The "SRAM and FIFO" section was updated. 2-21

The "RESET" section was updated. 2-25

The "WCLK and RCLK" section was updated. 2-25

The "RESET" section was updated. 2-25

The "RESET" section was updated. 2-27

The "Introduction" of the "Advanced I/Os" section was updated. 2-28

Previous Version Changes in Current Version (v1.3) Page

ProASIC3 DC and Switching Characteristics

v1.3 2-107

Advance v0.5

(continued)

The "I/O Banks" section is new. This section explains the following types of I/Os:

Advanced

Standard+

Standard

Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is

new. This table describes the standards listed above.

2-29

PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-

11 • VCCI Voltages and Compatible Standards

2-29

Table 2-13 • ProASIC3 I/O Features was updated. 2-30

The "Double Data Rate (DDR) Support" section was updated to include

information concerning implementation of the feature.

2-32

The "Electrostatic Discharge (ESD) Protection" section was updated to include

testing information.

2-35

Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V

Input Tolerance Capabilities in ProASIC3 Devices.

2-64

The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in

ProASIC3 Devices were updated.

2-64

The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"

section is new.

2-41

A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended

and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum

drive strength and high slew selected).

2-30

Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications 2-45

Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type

(A3P030 device)

2-83

Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated. 2-84

Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated. 2-84

The "x" was updated in the "User I/O Naming Convention" section. 2-48

The "VCC Core Supply Voltage" pin description was updated. 2-50

The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include

information concerning leaving the pin unconnected.

2-50

The "VJTAG JTAG Supply Voltage" pin description was updated. 2-50

The "VPUMP Programming Supply Voltage" pin description was updated to

include information on what happens when the pin is tied to ground.

2-50

The "I/O User Input/Output" pin description was updated to include information

on what happens when the pin is unused.

2-50

The "JTAG Pins" section was updated to include information on what happens

when the pin is unused.

2-51

The "Programming" section was updated to include information concerning

serialization.

2-53

The "JTAG 1532" section was updated to include SAMPLE/PRELOAD

information.

2-54

"DC and Switching Characteristics" chapter was updated with new information. 3-1

Previous Version Changes in Current Version (v1.3) Page

ProASIC3 DC and Switching Characteristics

2-108 v1.3

Advance v0.3 M7 device information is new. N/A

Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include the

number or rows in each top or bottom spine.

2-16

EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options. 2-24

The "PLL Macro" section was updated. EXTFB information was removed from

this section.

2-15

The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-

11 • ProASIC3 CCC/PLL Specification

2-29

EXTFB was removed from Figure 2-27 • CCC/PLL Macro. 2-28

Table 2-13 • ProASIC3 I/O Features was updated. 2-30

The "Hot-Swap Support" section was updated. 2-33

The "Cold-Sparing Support" section was updated. 2-34

"Electrostatic Discharge (ESD) Protection" section was updated. 2-35

The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance

Capabilities in ProASIC3 Devices was updated.

2-64

In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was

changed to VCCIB1.

2-97

The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"

section.

2-50

The "JTAG Pins" section was updated. 2-51

"128-Bit AES Decryption" section was updated to include M7 device

information.

2-53

Table 3-6 was updated. 3-6

Table 3-7 was updated. 3-6

In Table 3-11, PAC4 was updated. 3-93-8

Table 3-20 was updated. 3-20

The note in Table 3-32 was updated. 3-27

All Timing Characteristics tables were updated from LVTTL to Register Delays 3-31 to

3-73

The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. 3-85 to

3-90

FTCKMAX was updated in Table 3-110. 3-97

Advance v0.2 Figure 2-11 was updated. 2-9

The "Clock Resources (VersaNets)" section was updated. 2-9

The "VersaNet Global Networks and Spine Access" section was updated. 2-9

The "PLL Macro" section was updated. 2-15

Figure 2-27 was updated. 2-28

Figure 2-20 was updated. 2-19

Table 2-5 was updated. 2-25

Table 2-6 was updated. 2-25

Previous Version Changes in Current Version (v1.3) Page

ProASIC3 DC and Switching Characteristics

v1.3 2-109

Advance v0.2

(continued)

The "FIFO Flag Usage Considerations" section was updated. 2-27

Table 2-13 was updated. 2-30

Figure 2-24 was updated. 2-31

The "Cold-Sparing Support" section is new. 2-34

Table 2-43 was updated. 2-64

Table 2-18 was updated. 2-45

Pin descriptions in the "JTAG Pins" section were updated. 2-51

The "User I/O Naming Convention" section was updated. 2-48

Table 3-7 was updated. 3-6

The "Methodology" section was updated. 3-10

Table 3-40 and Table 3-39 were updated. 3-33,

3-32

Previous Version Changes in Current Version (v1.3) Page

ProASIC3 DC and Switching Characteristics

2-110 v1.3

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status datasheet may not have completed Actel’s