CY7C335 Universal Synchronous EPLD Features e Three separate clockstwo input clocks, two output clocks operation output registered @ Common (pin 14-controlled) or . product termcontrolled output en- e Twelve 1/O macrocelis, each having: able for each I/O pin Registered, three-state I/O pins 256 product terms32 per pair of Input and output register clock se- macrocells, variable distribution lect multiplexer @ Global, synchronous, product term Feed back multiplexer Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to implement JK or RS flip-flops and T or D registers Input multiplexer per pair of I/O ma- crocells allows I/O pin associated with Programmable security bit a hidden macrocell state register to be Functional Description saved for use as an input Four dedicated hidden registers The CY7C335 is a high-performance, eras- able, programmable logic device (EPLD) Twelve dedicated registered inputs hi hi has b imized with individually programmable by- whose architecture has been optimized to pass option enable the user to easily and efficiently controlled, state register set and re- setinputs to product term are clocked by input clock 2-ns input set-up and 9-ns output register clock to output 10-ns input register clock to state register clock 28-pin, 300-mil DIP, LCC, PLCC Erasable and reprogrammable construct very high performance state ma- chines. The architecture of the CY7C335, consist- ing of the user-configurable output macro- cell, bidirectional I/O capability, input reg- isters, and three separate clocks, enables the user to design high-performance state machines that can communicate either with each other or with microprocessors over bidirectional parallel buses of user- definable widths. The four clocks permit independent, syn- chronous state machines to be synchro- nized to each other. The user-configurable macrocells enable the designer to designate JK-, RS-, T-, or D-type devices so that the number of prod- uct terms required to implement the logic is minimized. The CY7C335S is available in a wide variety of packages including 28-pin, 300-mil plas- tic and ceramic DIPs, PLCCs, and LCCs, Logic Block Diagram OEM ho Ig Ig 7 lg Ves Is ta Ig 14 13 PROGRAM TK AND ARRAY 2 58 x 6B) WO, O49 Og VOg WOz WOg Vss Voc WOs VWO4 Ib H/CLK3IpfCLK2 CLK 3 2 1 V3 Wp VO, WO gagg4 2-84 MM 258%bbe 0016584 033 =Pin Configurations PLCC Top View bosons Naso 3 =. g 4.3.21 282726 Vs lg Gs H 10, WO, is 6 2 HI WO, Ws 5 G7 23) 1/05 Yeo Vss G8 228) Veo Wes is U9 210 Veg 6 I 10 208 1/0, Wr ie 11 H wo; aorrOD 335-2 TZ gggg 0335-3 B ss Selection Guide CY7C335~-100 | CY7C33583 | CY7C33566 | CY7C33550 | CY7C335-40 Maximum Operating Commercial 100 83.3 66.6 50 Frequency (MHz) Military 83.3 66.6 50 40.0 Icci (mA) Commercial 140 140 140 140 Military 160 160 160 160 Architecture Configuration Bits The architecture configuration bits are used to program the multiplex- ers. The function of the architecture bits is outlined in Table J. Table 1. Architecture Configuration Bits Architecture Configuration Bit Number of Bits Value Function co Output Enable 12 Bits, 1 Per 0Virgin State Output Enable Controlled by Product Term Hl Select MUX VO Macroce 1Programmed Output Enable Controlled by Pin 14 Cl State Register 12 Bits, 1 Per 0Virgin State State Register Output is Fed Back to Input Array C H Feed Back MUX | I/O Macroce 1Programmed T/O Macrocell is Configured as an Input and / Output of Input Path is Fed to Array C2 1/O Macrocell 12 Bits, 1 Per 0Virgin State ICLK1 Controls the Input Register I/O Macrocell Input Register V/O Macrocell Input Register Clock Input Clock Select - MUX 1Programmed | ICLK2 Controls the Input Register I/O Macrocell Input Register Clock Input C3 Input Register 12 Bits, 1 Per 0Virgin State Selects Input to Feedback MUX from Input Bypass MUX YO Macrocell Register YOM 1 10 Macroce 1Programmed Selects Input to Feedback MUX from I/O pin c4 Output Register 12 Bits, 1 Per 0Virgin State Selects Output from the State Register B MUX M. ll ypass MU VO Macroce 1Programmed Selects Output from the Array, Bypassing the State Register C5 State Clock MUX | 16 Bits, 1 Per YO 0Virgin State State Clock 1 Controls the State Register Macrocell and 1 Per Hidden Macrocell 1Programmed State Clock 2 Controls the State Register C6 Dedicated Input 12 Bits, 1 Per O0Virgin State ICLK1 Controls the Input Register I/O Macrocell Register Clock Dedicated Input Dedicated Input Register Clock Input Select MUX Cell ee 1Programmed ICLK2 Controls the Input Register I/O Macrocell Dedicated Input Register Clock Input 2-85 Mf 258%bbe 00165469 TTT I EECY7C335 FY Ss = CYPRESS Table 1. Architecture Configuration Bits (continued) Architecture Configuration Bit Number of Bits Value Function C7 Input Register 12 Bits, 1 Per 0Virgin State Selects Input to Array from Input Register Bypass MUX Dedicated Input - Input Cell Cell 1Programmed Selects Input to Array from Input Pin C8 ICLK2 Select 1 Bit 0Virgin State Input Clock 2 Controlled by Pin 2 MUX IProgrammed Input Clock 2 Controlled by Pin 3 co ICLK1 Select 1 Bit 0Virgin State Input Clock t Controlled by Pin 2 MUX U 1Programmed Input Clock 1 Controlled by Pin 1 c10 SCLK2 Select 1 Bit 0Virgin State State Clock 2 Grounded MUX 1Programmed State Clock 2 Controlled by Pin 3 CX T/O Macrocell 6 Bits, 1 Per 0Virgin State Selects Data from I/O Macrocell Input Path of (11-16) ] Pair Input Y/O Macrocell Macrocell A of Macrocell Pair Select MUX Pai ele an 1Programmed | Selects Data from I/O Macrocell Input Path of Macrocell B of Macrocell Pair INPUT INPUT REGISTER REG TO ARRAY INPUT OX MUX PIN D Q 0 C7 ICLKi INPUT cLock |-+> ICLK2 1] MUX c 338-4 Figure 1. CY7C335 Input Macrocell 2-86 |x*_ =F = CYPRESS CY7C335 co 0 TO ARRAY SHARED INPUT MUX 1 CX (11 16) FROM ADJACENT MAGROCELL 1 OUTPUT REG OF _ OUTPUT BYPASS MUX PIN 14: OE ENABLE OUTPUT ENABLE PRODUCT TERM 0} MUX SET PRODUCT TERM c4 EX OR PRODUCT TERM 5 => me Oo SCLK1 ] STATE a , | clk > p SCLK2 | MUX C5 ] RESET PRODUCT TER 0 TO ARRAY FEED 1 BACK pet MUX 1 co INPUT REGISTER BYPASS | | ce MUX Ly Q D ke C1 ] ] 0 ICLKA INPUT c3 CLOCK 1| mux | Ld ICLK2 > 0 Figure 2, CY7C335 Input/Output Macrocell 2-87 Me 254%bbe 0016591 625 0335-5CY7C335 SET PRODUCT TERM SCLK1 STATE 4} clK SCLK2 MUX C5 TO ARRAY RESET PRODUCT TERM C335-6 Figure 3. CY7C335 Hidden Macrocell SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS PIN 1 | 1 SCLK1 TO OUTPUT MACROCELLS AND HIDDEN Ly ICLK1 ICLK2 MACROCELLS o | MUX _- ce PIN2 1 o | MUX > Ot + | MUX __ ce i TO ARRAY o [MUX PINS | | 5 2 o | Mux > | , o | MUX ae cio 0336-7 Figure 4. CY7C335 Input Clocking Scheme 2-88 Me 258%bbe 6016592 Shy me| = = CY7C335 ss CYPRESS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage .......06.. 00 .ceccueeuae >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................6. -65Cto 150C - Latch-Up Current... .. 0.0... seve eeeeeeeeees >200 mA Ambient Temperature with DC Programming Voltage ............ 0.00 c cece nee 13.0V Power Applied ............... rte 55C to +125C Operating Range Supply Voltage to Ground Potential (Pin 22 to Pins 8 and 21) ................. 0.SV to +7.0V Ambient DC Voltage Applied to Outputs Range Temperature Vec in High Z State .... 22.2220 0.5V to +7.0V Commercial 0C to +75C 5V + 10% DC Input Voltage ...............0.0.000. -3.0V to +7.0V Industrial ~40C to +85C SV + 10% Output Current into Outputs (Low) ............... 12 mA Military 55C to 4125C 3V + 10% Electrical Characteristics Over the Operating Rangel] Parameter Description Test Conditions Min. | Max. | Unit Vou Output HIGH Voltage Vec = Min., Ion = 3.2mA Com'l 24 Vv Vin = VinorVit [57> 2mA Mil/ind VoL Output LOW Voltage Voc = Min., Io_ = 12 mA Com] 0.5 Vv Vin = VinorVit 5 =8mA Mil/ind Vin Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs] 1 2.2 Vv Vit Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputsl?] 0.8 Vv Ix Input Leakage Current Vss < Vin < Veco; Voc = Max. -10 10 pA loz Output Leakage Current Vcc = Max., Vss < Vout < Vcc 40 40 pA Isc Output Short Circuit Current | Voc = Max., Vout = 0.5Vi451 -30 | -90 | mA Iec1 Standby Power Vcc = Max., Vin = GND Com! 140 mA Supply Current Outputs Open Milind 160 | mA "ce at Fre meee syrent ose nts Disabled (in High Z State) com! 0 | mA aveney Device Operating at faa External (EMaxs) Mil/ind 200 mA Capacitancel) Parameter Description Test Conditions Min. Max. Unit Cin Input Capacitance Vin = 2.0V @ f = 1 MHz 10 pF Cout Output Capacitance Vout = 2.0V @ f = 1 MHz 10 pF vies is the instant on case temperature. 4. Not more than one output should be tested at a time. Duration of the 2. See the last page of this specification for Group A subgroup testing in- formation. 3. These are absolute values with respect to device ground and all over- shoots due to system or tester noise are included. short circuit should not be more than one second. Vout = 0.5V has been chosen to avoid test problems caused by ground degradation. 5. Tested initially and after any design or process changes that may affect these parameters. 2-89 Me 254%bb2 0016593 4TO me) ar CY7C335 === 2 CYPRESS AC Test Loads and Waveforms (Commercial) Ri 3132 (4702 MIL/IND) 3svO0w ouput Ft < R2208Q F i (3192 Mil/Ind) 80 p INCLUDING L JIG AND SCOPE (a) 335-8 R = 125Q (1902 MIL) OUTPUT' VrH = 2.00V = 50 pF | I (2.02V MIL) ov OV 335-9 (c) Thvenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND <3ns (b) C335-11 R = 1259 (1902 MIL} wee TOL c=5 T I Vy ov OV caa5-10 (d) Three-state Delay Load (Load 2) Parameter Vx Output WaveformMeasurement Level tpxz () 15V Vv, On 0.5V Vx 335-12 tpxz (+) 2.6V Vv 0.5V = Vx OL 0335~13 tezx (+) Vin Vv 0.5V _ Vou x 335-14 tpzx () Vth V x 0.5V VoL C335~-15 tcer (-) 15V Vv, OR "05V Vx 335-16 tcer (+) 2.6V Vv 0.5V Vx OL 0336-17 tcpa (+) Vth Vv. 0.5V pe VO x < 0335-18 tcea (~) Vin Vv. | x T05V VoL 335-19 Figure 5. Test Waveforms 2-90 me 2589%bbe 0016594 33? =, 7 CY7C335 SS Cypress Commercial AC Characteristics 7C335-100 | 7335-83 7C335-66 7335-50 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Combinatorial Mode Parameters tpp Input to Output Propagation Delay 15 15 20 25 ns TEA Input to Output Enable 15 15 20 25 ns tER Input to Output Disable 15 15 20 25 ns Input Registered Mode Parameters tw Input and Output Clock Width HIGHP] 4 5 6 8 ns twL Input and Output Clock Width LOWP! 4 5 6 8 ns tis Input or Feedback Set-Up Time to Input Clock 2 2 2 3 ns tr Input Register Hold Time from Input Clock 2 2 2 3 ns tico Input Register Clock to Output Delay 18 18 20 25 ns tion Output Data Stable Time from Input Clock 3 3 3 3 ns tion 4H | Output Data Stable from Input Clock Minus Input Regis- | 0 0 0 0 ns 33x ter Hold Time for 7C330, 7C332, and 7C335101 tpzx Pin 14 Enable to Output Enabled 12 12 15 20 ns tpxz Pin 14 Disable to Output Disabled 12 12 15 20 ns fMAX1 Maximum Frequency of (2) CY7C335s in Input Registered | 50 50 45.4 35.7 MHz Mode (Lowest of 1/(tico + tis) & 1/(twit twa] fMax2 Maximum Frequency Data Path in Input Registered Mode | 55.5 55.5 50 40 MHz (Lowest of (U(tioo), twat two), W(tis + ty) EP) tCEA Input Clock to Output Enabled V7 7 20 25 ns tiCER Input Clock to Output Disabled 15 15 20 25 ns Output Registered Mode Parameters tCEA Output Clock to Output Enabled] 17 17 20 25 | ns tcER Output Clock to Output Disabled!! 15 15 20 25 | ns ts Output Register Input Set-Up Time from Output Clock | 8 9 12 15 ns ty Output Register Input Hold Time from Output Clock 0 0 0 0 ns tco Output Register Clock to Output Delay 9 10 12 15 ns tco2 Input Output Register Clock or Latch Enable to 17 18 23 30 ns Combinatorial Output Delay (Through Logic Array)5l tou Output Data Stable Time from Output Clock 2 2 2 2 ns ton2 Output Data Stable Time From Output Clock (Through | 3 3 3 3 ns Memory Array)|>l ton2-tny | Output Data Clock Stable Time From Output Clock Mi- | 0 0 0 0 ns nus Input Register Hold Timel>] fax3 Maximum Frequency with Internal Feedback in Output | 100 83.3 66.6 50 MHz Registered Model>! fMax4 Maximum Frequency of (2) CY7C335s in Output Registered | 58.8 50 41.6 33.3 MHz Made (Lowest of I/(teo + ts) & Itwr + twn))or fMaxs Maximum Frequency Data Path in Output Registered | 111 100 83.3 62.5 MHz Mode (Lowest of 1/(tco), (tw + twa), ts + ty))P) tou try | Output Data Stable from Output Clock Minus Input Reg- | 0 0 0 0 ns 33x ister Hold Time for 7C330, 7C332, and 733511 2-91 Mf 2589%bbe 0016595 273This part has been designed with the capability to reset during system power-up. Following power-up, the input and output registers will be reset to a logic LOW state. The output state will depend on how the array is programmed. Se = CY7C335 SF CYPRESS Commercial AC Characteristics (continued) 7C335-100 | 7C335-83 | 7C335-66 | 7C33550 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Pipelined Mode Parameters tcos Input Clock to Output Clock 10 12 15 20 ns fMaxe Maximum Frequency Pipelined Mode (Lowest of | 100 83.3 66.6 30 MHz 1(tcos), U(tco), W(twe + twH)), Wis + tra) fMAx7 Maximum Frequency of (2) CY7C335s in Pipelined Mode | 90.9 83.3 66.6 50 MHz (Lowest of 1/(tco + tis) or L/tcos) Power-Up Reset Parameters tpor | Power-Up Reset Timel: 7] | } 1 | } 1 | [1 | 1 1 | os Military/Industrial AC Characteristics 7C335-83 | 7C335-66 | 7C335-50 | 7C33540 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. } Unit Combinatorial Mode Parameters tpp Input to Output Propagation Delay 20 20 25 30 ns tEA Input to Output Enable 20 20 25 30 ns teR Input to Output Disable 20 20 25 30 ns Input Registered Mode Parameters twH Input and Output Clock Width HIGH! 5 6 8 10 ns twL Input and Output Clock Width LOWE] 5 6 8 10 ns tis Input or Feedback Set-Up Time to Input Clock 3 3 3 4 ns ty Input Register Hold Time from Input Clock 3 3 3 4 ns tico Input Register Clock to Output Delay 23 23 25 30 ns tiou Output Data Stable Time from Input Clock 3 3 3 3 ns tion try | Output Data Stable from Input Clock Minus Input 0 0 0 0 ns 33x Register Hold Time for 7C330, 7C332, and 7C335(] tpzx Pin 14 Enable to Output Enabled 15 15 20 30 ns tpxz. Pin 14 Disable to Output Disabled 15 15 20 30 ns fmaxi Maximum Frequency of (2) CY7C335s in Input 38.4 38.4 35.7 29.4 MHz Registered Mode (Lowest of 1/(tico + tis) & U(twe + twu))E! fax2 Maximum Frequency Data Path in Input Registered | 43.4 43.4 40 33.3 MHz Mode (Lowest of (1/(tico), U(twH + twr), 1A tis + thy)) PI , CEA Input Clock to Output Enabled 20 20 25 30 ns | CER Input Clock to Output Disabled 20 20 25 30 ns Output Registered Mode Parameters tCBA Output Clock to Output Enabled EF] 20 20 25 30 | ns | tcER Output Clock to Output Disabled [1 20 20 25 30 | ns ts Output Register Input Set-Up Time to Output Clock { 10 12 5 20 ns ty Output Register Input Hold Time from Output Clock | 0 0 0 0 ns tco Output Register Clock to Output Delay 11 12 15 20 ns tco2z Output Register Clock or Latch Enable to Combinatorial 22 23 30 35 ns Output Delay (Through Logic Array)P] Notes: 6. This specification is intended to guarantee interface compatibility of 7. the other members of the CY7C330 family with the CY7C335. This specification is met for the devices operating at the same ambient tem- perature and at the same power supply voltage. 2-92 ME 258%bbe OO1lbSdb LOTee CY7C335 === CYPRESS Military/Industrial AC Characteristics (continued) 7C33583 | 7C335-66 | 7C335-50 | 70335-40 Parameter Description Min, | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tou Output Data Stable Time from Output Clock 2 2 2 2 lis tou2 Output Data Stable Time From Output Clock} 3 3 3 3 ns (Through Memory Array) ton2tny | Output Data Clock Stable Time From Output Clock | 0 0 0 0 ns Minus Input Register Hold Timel>] fmax3 Maximum Frequency with Internal Feedback in Out- | 83.3 66.6 50 40 MHz put Registered Model>] fmaxa Maximum Frequency of (2) CY7C335s in Output Regis- | 47.6 41.6 33.3 25 MHz tered Mode (Lower of I/(tea + tg) & 1(twr + twy))Pl EMAXs Maximum Frequency Data Path in Output Registered | 90.9 83.3 62.5 50 MHz Mode (Lowest of 1/(tco), 1tw + twa), Its + ty))FI tou ti | Output Data Stable from Output Clock Minus Input | 0 Q 0 0 ns 33x Register Hold Time for 7C330, 7C332, and 7C33516] Pipelined Mode Parameters tcos Input Clock to Output Clock 12 15 20 25 ns fMaxe Maximum Frequency Pipelined Mode 83.3 66.6 50 40 MHz (Lowest of 1 tcos), 1/(tis), or 1(tco)), W(tis + tra) fax? Maximum Frequency of (2) CY7C335s in Pipelined | 71.4 66.6 50 40 MHz Mode (Lowest of 1/(tco + ts) or 1/tcos) Power-Up Reset Parameters tpoRr | Power-Up Reset Timel>: 7] | } i | {i | j 1] | 1 | ps 2-93 me 258%bbe 0016597 O4L i aaSS = z= CY7C335 SSeare CYPRESS Switching Waveform INPUT OR v i VO PIN t tig ere tH M ty eee ty INPUT REG. / | CLOCK / twH al twe tcas tWH twe OUTPUT : < tico >| REG. CLOCK / [og >| toh Kt ton | OUTPUT XOX > NX tpp e- ten I ticeR [ ticea ter texz I tzx -] PIN 14 AS OE Power-Up Reset Waveform!] 33520 90% Je Vcc / tpon tcos - ook TYNAN twin Ca35-21 2-94 . 2e569bbe 0016596 Tac =| S = =. oa SS" (C9) CY7C335 64 RESET node=29 (C6,7) (Ca) (C1 (C6 node=40 node=39 node=38 node=34 (C8,7) node=33 (C6,7) TO LOWER SECTION Ca35-22 2-95 M@@ 25869662 0016595 919Sie a = CY7C335 =? Cypress Block Diagram (Page 2 of 2) - TO UPPER SECTION node=37 node=32 node=31 node=36 7 (C45) node=35 15 mm 258%bbe 0395-23= . CY7C335 == CYPRESS Ordering Information fax Icci Package Operating (MHz) (mA) Ordering Code Name Package Type Range 100 140 CY7C335100HC H64 28-Pin Windowed Leaded Chip Carrier ] Commercial CY7C335100JC J64 28-Lead Plastic Leaded Chip Carrier CY7C335100PC P21 28-Lead (300-Mil) Molded DIP CY7C335100WC W22 28-Lead (300-Mil) Windowed CerDIP 83.3 160 CY7C33583DI1 D22 28-Lead (300-Mil) CerDIP Industrial CY7C33583HI H64 28-Pin Windowed Leaded Chip Carrier CY7C33583PI P21 28-Lead (300-Mil) Molded DIP CY7C33583WI W22 28-Lead (300-Mil) Windowed CerDIP CY7C33583DMB D22 28-Lead (300-Mil) CerDIP Military CY7C33583HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C335 -83LMB L64 28-Square Leadless Chip Carrier CY7C335 -83QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C335-83WMB W22 28-Lead (300-Mil) Windowed CerDIP 83.3 140 CY7C335 -83HC H64 28-Pin Windowed Leaded Chip Carrier | Commercial CY7C335835C J64 28-Lead Plastic Leaded Chip Carrier CY7C33583PC P21 28-Lead (300-Mil) Molded DIP CY7C335 -83WC W22 28-Lead (300-Mil) Windowed CerDIP 66.6 160 CY7C335 66DI D22 28-Lead (300-Mil) CerDIP Industrial CY7C33566HI H64 28-Pin Windowed Leaded Chip Carrier CY7C33566PI P21 28-Lead (300-Mil) Molded DIP CY7C33566WI1 W22 28-Lead (300-Mil) Windowed CerDIP CY7C335 -66DMB D22 28-Lead (300-Mil) CerDIP Military CY7C335 -66HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C335-66LMB L64 28-Square Leadless Chip Carrier CY7C33566QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C335-66WMB W22 28-Lead (300-Mil) Windowed CerDIP 66.6 140 CY7C335-66HC H64 28-Pin Windowed Leaded Chip Carrier | Commercial CY7C335663C J64 28-Lead Plastic Leaded Chip Carrier CY7C33566PC P21 28-Lead (300-Mil) Molded DIP CY7C335 66WC W22 28-Lead (300-Mil) Windowed CerDIP 50 140 CY7C335 S0OHC H64 28-Pin Windowed Leaded Chip Carrier | Commercial CY7C335 S0JC 164 28-Lead Plastic Leaded Chip Carrier CY7C33550PC P21 28-Lead (300-Mil) Molded DIP CY7C33550WC Ww22 28-Lead (300-Mil) Windowed CerDIP 2-97 MB 2548%bb2 OOLbb01 37? aSee, CY7C335 S97 CYPRESS Ordering Information (continued) fax Icc1 Package Operating (MHz) (mA) Ordering Code Name Package Type Range 50 160 CY7C335S0DI D22 28-Lead (300-Mil) CerDIP Industrial CY7C33550HI H64 28-Pin Windowed Leaded Chip Carrier CY7C335S0PI P21 28-Lead (300-Mil) Molded DIP CY7C335SOWI W22 28-Lead (300-Mil) Windowed CerDIP CY7C335SO0DMB D22 28-Lead (300-Mil) CerDIP Military CY7C335-SOHMB H64 28-Pin Windowed Leaded Chip Carrier CY7C335S0LMB L64 . | 28-Square Leadless Chip Carrier CY7C33550QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C335-SOWMB Ww22 28-Lead (300-Mil) Windowed CerDIP 40 160 CY7C33540DI D22 28-Lead (300-Mil) CerDIP Industrial CY7C33540HI H64 28-Pin Windowed Leaded Chip Carrier CY7C33540PI P21 28-Lead (300-Mil) Molded DIP CY7C33540WI1 W22 28-Lead (300-Mil) Windowed CerDIP CY7C33540DMB D22 28-Lead (300-Mil) CerDIP Military CY7C335 -40HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C33540LMB L64 28-Square Leadless Chip Carrier CY7C335-40QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C335 -40WMB W22 28-Lead (300-Mil) Windowed CerDIP MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou 1, 2,3 VoL 1, 2,3 Vin 1, 2,3 Vit 1, 2,3 Tix 1, 2,3 Ioz 1,2,3 Tec 1, 2,3 Switching Characteristics Parameter Subgroups tpp 9, 10, 11 tico 9, 10, 11 tis 9, 10, 11 tco 9, 10, 11 ts 9, 10, 11 try 9, 10, 11 tcos 9, 10, 11 Document #: 38-00186-C 2-98 MH 258%9bbe 00164602 233