1
®
FN6228.1
ISL55110, ISL55111
Dual, High Speed MOSFET Driver
The ISL55110 and ISL55111 are dual high speed mosfet
drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include
Ultrasound, CCD Imaging, Automotive Piezoelectric
distance sensing and clock generation circuits.
With a wide output voltage range and low on resistance,
these devices can drive a variety of resistive and capacitive
loads with fast rise and fall times, allowing high speed
operation with low skew as required in large CCD array
imaging applications.
The ISL55110 and ISL55111 are compatible with 3.3V and
5V logic families and incorporate tightly controlled input
thresholds to minimize the effect of input rise time on output
pulse width. The ISL55110 has a pair of in-phase drivers
while the ISL55111 has two drivers operating in antiphase.
Both inputs of the device have independent inputs to allow
external time phasing if required.
The ISL55110 has a power down mode for low power
consumption during equipment standby times, making it
ideal for portable products.
The ISL55110 and ISL55111 are available in 16 Ld Exposed
pad QFN packaging and 8 Ld TSSOP. Both devices are
specified for operation over the full -40°C to +85°C
temperature range.
Functional Block Diagram
Features
• 5V to 12V Pulse Magnitude
• High Current Drive 3.5A
• 6ns Minimum Pulse Width
• 1.5ns Rise and Fall Times, 100pF Load Time
•Low Skew
• 3.3V and 5V Logic Compatible
• In-Phase and Anti-Phase Outputs
• Small QFN and TSSOP Packaging
• Low Quiescent Current
• Pb-free Plus Anneal Available (RoHS compliant)
Applications
• Ultrasound Mosfet Driver
• CCD Array Horizontal Driver
• Automotive Piezo Driver Applications
• Clock Driver Circuits
ISLl55110 and ISL55111 DUAL DRIVER
VH
OA
OB
IN-A
oo
o
o
o
IN-B
o
o
GND
oPOWER DOWN
oVDD
oHIZ-QFN*
* HIZ AVAILABLE IN QFN PACKAGE ONLY
* ISL551 11 IN-B IS INVERTING
*
Ordering Information
PART
NUMBER PART
MARKING TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
ISL55110IRZ*
(Note) 55 110IRZ -40 to +85 16 Ld QFN
(Pb-free) L16.4x4A
ISL55110IVZ*
(Note) 55110 IVZ -40 to +85 8 Ld TSSOP
(Pb-free) M8.173
ISL55111IRZ*
(Note) 55 11IRZ -40 to +85 16 Ld QFN
(Pb-free) L16.4x4A
ISL55111IVZ*
(Note) 55111 IVZ -40 to +85 8 Ld TSSOP
(Pb-free) M8.173
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Data Sheet March 21, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6228.1
March 21, 2007
Pinout ISL55110
(16 LD QFN)
TOP VIEW
ISL55111
(16 LD QFN)
TOP VIEW
ISL55110
(8 LD TSSOP)
TOP VIEW
ISL55111
(8 LD TSSOP)
TOP VIEW
16 15 14 13
OB
GND
VH
OA
1
2
3
4
12
11
10
9
VDD
ENABLE
PD
IN-B
5678
IN-A
NC
NC
NC NC
16 15 14 13
OB
GND
VH
OA
1
2
3
4
12
11
10
9
VDD
ENABLE
PD
IN-B
5678
IN-A
NC
NC
NC
NC
NC
NC
NC
6
7
8
5
1
2
3
4
VDD
PD
IN-B
IN-A
OB
VH
OA
GND
6
7
8
5
1
2
3
4
VDD
PD
IN-B
IN-A
OB
VH
OA
GND
Pin Descriptions
PIN FUNCTION
VDD Logic Power.
VH Driver High Rail Supply
GND Ground, return for both VH rail and VDD Logic Supply.
PD Power Down. Active Logic High places part in Power Down Mode.
ENABLE QFN Packages only. Provides high speed logic HIZ control of driver outputs while leaving device logic power on.
IN-A Logic level input that drives OA to VH Rail or Ground. Not Inverted.
IN-B, INB Logic level input that drive OB to VH Rail or Ground. Not inverted on ISL55110, Inverted on ISL55111.
OA Driver output related to IN-A.
OB Driver output related to IN-B.
ISL55110, ISL55111
NC
NC
NC
3FN6228.1
March 21, 2007
Absolute Maximum Ratings (TA = +25°C) Thermal Information
VH+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
VIN_A, VIN_V, PDN, ENABLE. . . . . . . . (GND-0.5V) to (VDD+0.5V)
OA, OB. . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND-0.5) to (VH+0.5V)
Maximum Peak Output Current . . . . . . . . . . . . . . . . . . . . . . (300mA)
ESD HBM Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3KV
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Thermal Resistance θJA (°C/W)
16 Ld (4x4) QFN Package (Note 2) . . . . . . . . . . . . . 45
8 Ld TSSOP Package (Note 1) . . . . . . . . . . . . . . . . 140
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperatur e Range. . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefor e: TJ = TC = TA
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Recommended Operating Conditions
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
VH Driver Supply Voltage 5 12 13.2 V
VDD Logic Supply Voltage 2.7 5.5 V
TAAmbient Temperature -40 +85 °C
TJJunction Temperature +150 °C
DC Electrical Specifications VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
LOGIC CHARACTERISTICS
VIX_LH Logic Input Threshold - Low to High lIH = 1µA: VIN_A, VIN_B 1.32 1.42 1.52 V
VIX_HL Logic Input Threshold - High to Low lIL = 1µA: VIN_A, VIN_B 1.12 1.22 1.32 V
VHYS Logic Input Hysteresis VIN_A,VIN_B 0.2 V
VIH Logic Input High Threshold PDN 2.0 VDD V
VIL Logic Input Low Threshold PDN 0 0.8 V
VIH Logic Input High Threshold ENABLE - QFN only 2.0 VDD V
VIL Logic Input Low Threshold ENABLE - QFN only 0 0.8 V
IIX_H Input Current Logic High VIN_A,VIN_B = VDD 10 20 nA
IIX_L Input Current Logic Low VIN_A, VIN_B = 0V 10 20 nA
II_H Input Current Logic High PDN = VDD 10 20 nA
II_L Input Current Logic Low PDN = 0V 10 15 nA
II_H Input Current Logic High ENABLE = VDD - QFN only 12 mA
II_L Input Current Logic Low ENABLE = 0V - QFN only -25 nA
ISL55110, ISL55111
4FN6228.1
March 21, 2007
DRIVER CHARACTERISTICS
RDS Driver Output Resistance OA, OB 3 6 Ω
IDC Driver Output DC current (>2s) 100 mA
IAC Peak Output Current Design Intent verified via
simulation. 3.5 A
VOH to VOL Driver Output Swing Range VH voltage to Ground 3 13.2 V
SUPPLY CURRENTS
IDD Logic Supply Quiescent Current PDN = Low 4.0 6.0 mA
IDD-PDN Logic Supply Power Down Current PDN = High 12 μA
IH Driver Supply Quiescent Current PDN = Low, No resistive load
DOUT 15 μA
IH_PDN Driver Supply Power Down Current PDN = High 1 μA
DC Electrical Specifications (Continued)VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
AC Electrical Specifications VH = +12V, VDD = +3.6, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING CHARACTERISTICS
tR,tFDriver Rise/Fall Time OA,OB: CL = No Load
10% to 90%, VOH-VOL = 12V
10% to 90%, VOH-VOL = 10V 1.0
1.0 ns
ns
tR,tFDriver Rise/Fall Time OA, OB CL = 1nF
10% to 90%, VOH-VOL = 12V 6.7 ns
tpdR Input to Output Propagation Delay Figure 2, Load 100pF/1k 12.0 ns
tpdF Input to Output Propagation Delay 9.3 ns
tpdR Input to Output Propagation Delay Figure 2, Load 220pF 12.5 ns
tpdF Input to Output Propagation Delay 10.2 ns
tpdR Input to Output Propagation Delay Figure 2, Load 330pF 12.9 ns
tpdF Input to Output Propagation Delay 10.6 ns
tpdR Input to Output Propagation Delay Figure 2, Load 680pF 14.1 ns
tpdF Input to Output Propagation Delay 12.1 ns
tSkewR Channel to Channel tpdR Spread with same
loads both Channels Figure 2, All Loads <0.5 ns
tSkewF Channel to Channel tpdF Spread with same
loads both channels. Figure 2, All Loads <0.5 ns
FMAX Maximum Operating Frequency 70 MHz
TMIN Minimum Pulse Width 6 ns
PDEN* Power-down to Power-on Time 0.7 1.0 ms
PDDIS* Power-on to Power-down Time 1.4 1.6 ms
TEN* ENABLE to ENABLE Time (HIZ Off) 0.3 0.7 ms
TDIS* ENABLE to ENABLE TIme (HIZ On) 1.4 1.6 ms
ISL55110, ISL55111
5FN6228.1
March 21, 2007
FIGURE 1. TEST CIRCUIT RISE (TR)/FALL(TF) THRESHOLDS
FIGURE 2. TEST CIRCUIT PROPAGATION TPD DELAY
ISL55110
INPUT
INPUT RISE AND
FALL TIMES ≤2ns
CL
4.7μF0.1μF
+
OUTPUT
VH = 12V
50%
50%
50%
50%
tpdR tpdF
≈0.4V
12V
INPUT
+3V
0V
OUTPUT OA AND OB ISLS55110
IN-X
IN
OUTPUT OA ISLS55111
50%
50%
12V
0V
OUTPUT OB ISLS55111
tSKEWR = tpdR CHN1 - tpdR CHN2
ISL55110
INPUT
INPUT RISE AND
FALL TIMES ≤2ns
CL
4.7μF0.1μF
+
OUTPUT
VH = 12V
10%
10%
90%
tf
90%
tr
≈0.4V
12V
INPUT
+3V
0V
OUTPUT
INX
IN
ISL55110, ISL55111
6FN6228.1
March 21, 2007
Typical Performance Curves (See Typical Performance Curves Discussion)
FIGURE 3. DRIVER RON vs VH SOURCE RESISTANCE FIGURE 4. DRIVER RON vs VH SINK RESISTANCE
FIGURE 5. RON vs VDD SOURCE RESISTANCE FIGURE 6. RON vs VDD SINK RESISTANCE
FIGURE 7. IDD vs VDD QUIESCENT CURRENT FIGURE 8. IDD vs VH @ 50MHz (NO LOAD)
7.0
6.3
5.6
4.9
4.2
3.5
2.8
2.1
1.4
0.7
0.0345678910111213
VH, DRIVE RAIL (V)
+85°C +25°C
-40°C
RON
VDD 3.6V
-50mA
7.0
6.3
5.6
4.9
4.2
3.5
2.8
2.1
1.4
0.7
0.0
345678910111213
VH, DRIVE RAIL (V)
+85°C
+25°C
-40°C
RON
+50mA
VDD 3.6V
4.00
3.66
3.33
2.66
2.33
2.002.5 3.5 4.5 5.5
VDD (V)
VH 5.0V
RON (Ω)
50mA
VH 12.0V
4.00
3.66
3.33
2.66
2.33
2.00
2.5 3.5 4.5 5.5
VDD (V)
VH 12.0V
RON (Ω)
50mA
VH 5.0V
4.0
3.8
3.6
3.4
3.2
3.0
2.5 3.5 4.5 5.5
VDD (V)
IDD (mA)
VH 5V AND 12V
10
9
8
7
6
5
4
3
2
1
04812
IDD (mA)
VDD 3.6V
VH, DRIVE RAIL (V)
ISL55110, ISL55111
7FN6228.1
March 21, 2007
FIGURE 9. QUIESCENT IH vs VH FIGURE 10. IH vs VH @ 50MHz (NO LOAD)
FIGURE 1 1. IDD vs FREQUENCY (DUAL CHANNEL, NO
LOAD)L FIGURE 12. IH vs FREQUENCY (DUAL CHANNEL, NO LOAD)
FIGURE 13. VIH LOGIC THRESHOLDS FIGURE 14. VIL LOGIC THRESHOLDS
Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
100
90
80
70
60
50
40
30
20
10
0 4812
VH, DRIVE RAIL (V)
IH (µA)
VDD 3.6V 200
180
160
140
120
100
80
60
40
20
0 4812
VH, DRIVE RAIL (V)
IH (mA)
VDD 3.6V
15.0
13.5
12.0
10.5
9.00
7.50
6.00
4.50
2.00
0.50
0.00
50M 66M 100M 124M 128M
TOGGLE FREQUENCY IN Hz
IDD (mA)
VH 5.0V
VDD 3.6V
200
180
160
140
120
100
80
60
40
20
0
50M 100M 128M
TOGGLE FREQUENCY IN Hz
66M 124M
IH (mA)
VH 5.0V
VDD 3.6V
1.5
1.4
1.3
1.2
1.1
1.02.5 3.5 4.5 5.5
VDD (V)
-40°C +85°C
LOGIC (V)
1.5
1.4
1.3
1.2
1.1
1.02.5 3.5 4.5 5.5
VDD (V)
LOGIC (V)
-40°C
+85°C
ISL55110, ISL55111
8FN6228.1
March 21, 2007
FIGURE 15. tr vs TEMPERATURE FIGURE 16. tf vs TEMPERATURE
FIGURE 17. tpdr vs TEMPERATURE FIGURE 18. tpdf vs TEMPERATURE
FIGURE 19. tr vs VDD FIGURE 20. tfvs VDD
Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
10
9
8
7
6
5
4
3
2
1
0
-40 -10 +20 +50 + 85
PACKAGE TEMP (°C)
RISE TIME (ns)
1000pF
680pF
330pF
100pF/1k
VH 12.0V
VDD 3.6V
10
9
8
7
6
5
4
3
2
1
0
-40 -10 +20 +50 +85
PACKAGE TEMP (°C)
FALL TIME (ns)
100pF/1k 680pF330pF 1000pF
VDD 3.6V
VH 12.0V
20
18
16
14
12
10
8
6
4
2
0
-40 -10 +20 +50 +85
PACKAGE TEMP (°C)
PROPAGATION DELAY (ns)
100pF/1k 330pF
680pF 1000pF
VH 12.0V
VDD 3.6V VH 12.0V
VDD 3.6V
20
18
16
14
12
10
8
6
4
2
0
-40 -10 +20 +50 +85
PACKAGE TEMP (°C)
PROPAGATION DELAY (ns)
100pF/1k 330pF
680pF 1000pF
10
9
8
7
6
5
4
3
2
1
0
2.5 3.5 5.5
VDD (V)
RISE TIME (ns)
VH 12.0V
4.5
1000pF
680pF
330pF
100pF/1k
10
9
8
7
6
5
4
3
2
1
0
2.5 3.5 5.5
VDD (V)
FALL TIME (ns)
VH 12.0V
4.5
1000pF
680pF
330pF
100pF/1k
ISL55110, ISL55111
9FN6228.1
March 21, 2007
FIGURE 21. tr vs VH FIGURE 22. tf vs VH
FIGURE 23. tpdr vs VDD FIGURE 24. tpdf vs VDD
FIGURE 25. tpdr vs VH FIGURE 26. tpdf vs VH
Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
12.0
10.8
9.6
8.4
7.2
6.0
4.8
3.6
2.4
1.2
0.036 12
VH (V)
RISE TIME (ns)
VDD 3.3V
9
1000pF
680pF
330pF
100pF/1k
36 12
VDD (V)
FALL TIME (ns)
VDD 3.3V
9
10.8
9.6
8.4
7.2
6.0
4.8
3.6
2.4
1.2
0.0
12.0 1000pF
680pF
330pF
100pF/1k
20
18
16
14
12
10
8
6
4
2
0
2.5 3.5 VDD (V)
PROPAGATION DELAY (ns)
VH 12.0V
4.5
1000pF
680pF
330pF
100pF/1k
5.5
20
18
16
14
12
10
8
6
4
2
0
2.5 3.5 5.5
VDD (V)
PROPAGATION DELAY (ns)
VH 12.0V
4.5
1000pF
680pF
330pF
100pF/1k
20
18
16
14
12
10
8
6
4
2
0 36 12
VH (V)
PROPAGATION DELAY (ns)
VDD 3.3V
9
1000pF
680pF
330pF
100pF/1k
20
18
16
14
12
10
8
6
4
2
036 12
VH (V)
PROPAGATION DELAY (ns)
VDD 3.3V
9
1000pF
680pF
330pF
100pF/1k
ISL55110, ISL55111
10 FN6228.1
March 21, 2007
FIGURE 27. tskewr vs TEMPERATURE FIGURE 28. tskewf vs TEMPERATURE
FIGURE 29. tskewr vs VDD FIGURE 30. tskewf vs VDD
FIGURE 31. tskewr vs VH FIGURE 32. tskewf vs VH
Typical Performance Curves (Continued) (See Typical Performance Curves Discussion)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 -10 +20 +50 +85
PACKAGE TEMP (°C)
tskewR (ns)
680pF 330pF
VH 12.0V
VDD 3.6V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 -10 +20 +50 +85
PACKAGE TEMP (°C)
tskewF (ns)
680pF AND 330pF
VH 12.0V
VDD 3.6V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.02.5 3.5 5.5
VDD (V)
SKEW (ns)
VH 12.0V
4.5
680pF
330pF
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.5 3.5 5.5
VDD (V)
SKEW (ns)
VH 12.0V
4.5
680pF
330pF
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 36 12
VDD (V)
SKEW (ns)
VDD 3.3V
9
680pF
330pF
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 36 12
VDD (V)
SKEW (ns)
VDD 3.3V
9
680pF
330pF
ISL55110, ISL55111
11 FN6228.1
March 21, 2007
Typical Performance Curves Discussion
RON
RON Source tested by placing device in Constant Drive High
Condition and connecting -50mA constant current source to
the Driver Output. V oltage Drop measured from VH to Driver
Output for RON calculations.
RON Sink tested by placing device in Constant Driver Low
Condition and connecting a +50mA constant current source.
Voltage Drop from Driver Out to Ground measured for RON
Calculations.
Dynamic Tests
All dynamic tests are conducted with ISL55110, ISL55111
Evaluation Board(s). Driver Loads are soldered to the
Evaluation board. Measurements are collected with P62 45
Active Fet Probes and TDS5104 Oscilloscope. Pulse
Stimulus is provided by HP8131 pulse generator.
The ISL55110, ISL55111 Evaluation Boards provide Test
Point Fields for leadless connection to either an Active Fet
Probe or Differential probe. TP-IN fields are used for
monitoring pulse input stimulus. TP-OA/B monitor Driver
Output wavefo rms. C6 and C7 are the usual placement for
Driver loads. R3 and R4 are not populated and provided for
User-Specified, more complex load characterization.
Pin Skew
Pin Skew measurements are based on the difference in
propagation delay of the two channels. Measurements are
made on each channel from the 50% point on the stimulus
point to the 50% point on the driver output. The difference in
the propagation delay for Channel A and Channel B is
considered to be Skew.
Both Rising Propagation Delay and Falling Propagation
Delay are measured and reports as tSkewR and tSkewF.
50MHz Tests
50MHz Tests reported as No Load actually include
Evaluation board parasitics and a single TEK 6545 fet probe.
However no driver load components are installed, C6
through C9 and R3 through R6 are not popula ted.
General
Most dynamic measurements are presented in three ways.
First over temperature with a VDD of 3.6V and VH of 12.0V.
Second, at ambient with VH set to 12V and VDD data points
of 2.5V, 3.5V, 4.5V and 5.50V. Third, the ambient tests are
repeated with VDD of 3.3V and VH data points of 3V, 6V, 9V
and 12V.
ISL55110, ISL55111
12 FN6228.1
March 21, 2007
Detailed Description
The ISL55110 and ISL55111 are Dual High Speed Mosfet
Drivers intended for applications requiring accurate pulse
generation and buffering. Target applications include
Ultrasound, CCD Imaging, Automotive Piezoelectric
distance sensing and clock generation circuits.
With a wide output voltage range and low On Resistance,
these devices can drive a variety of resistive and capacitive
loads with fast rise and fall times, allowing high speed
operation with low skew as required in large CCD array
imaging applications.
The ISL55110 and ISL55111 are compatible with 3.3V and
5V logic families and incorporate tightly controlled input
thresholds to minimize the effect of input rise time on output
pulse width. The ISL55110 has a pair of in-phase drivers
while the ISL55111 two drivers operating in antiphase. Both
inputs of the device have independent inputs to allow
external time phasing if required.
In addition to power MOS drivers, the ISL551 10, ISL5511 1 is
well suited for other applications such as bus, control signal,
and clock drivers on large memory of microprocessor
boards, where the load capacitance is large and low
propagation delays are required. Other potential applications
include peripheral power drivers and charge-pump voltage
inverters.
Input Stage
The input stage is a high impedance input with rise/fall
hysteresis. This means that the inputs will be directly
compatible with both TTL and lower voltage logic over the
entire VDD range. The user should treat the inputs as high
speed pins and keep rise and fall times to <2ns.
Output Stage
The ISL55110, ISL55111 output is a high-power CMOS
driver, swinging between ground and VH. At VH = 12V, the
output impedance of the inverter is typically 3.0Ω. The high
peak current capability of the ISL55110, ISL5511 1 enables it
to drive a 330pF load to 12V with a rise time of <3.0ns over
the full temperature range. The output swing of the
ISL55110, ISL55111 comes within < 30mV of the VH and
Ground rails.
Application Notes
Although the ISL55110, ISL55111 is simply a dual level-
shifting driver, there are several areas to which care ful
attention must be paid.
Grounding
Since the input and the high current output current paths
both include the ground pin, it is very important to minimize
and common impedance in the ground return. Since the
ISL55111 has one inverting input, any common impedance
will generate negative feedback, and may degrade the delay ,
rise and fall times. Use a ground plane if possible, or use
separate ground returns for the input and output circuits. To
minimize any common inductance in the ground return,
separate the input and output circuit ground returns as close
to the ISL55110, ISL55111 as is possible.
Bypassing
The rapid charging and disch arging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.7μF
tantalum capacitor in parallel with a low inductance 0.1μF
capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
1. Reduce inductance by making printed circuit board traces
as short as possible.
2. Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3. Use small damping resistor in series with the output of the
ISL551 10, ISL5511 1. Although this reduces ringing, it will
also slightly increase the rise and fall times.
4. Use good by passing techniques to prevent supply volt-
age ringing.
Power Dissipation Calculation
The Power dissipation equation has three components:
Quiescent Power Dissipation, Power dissipation due to
Internal Parasitics and Power Dissipation because of the
Load Capacitor.
Power dissipation due to internal parasitics is usually the
most difficult to accurately quantitize. This is primarily due to
Crow-Bar current which is a product of both the high and low
drivers conducting effectively at the same time during driver
transitions. Design goals always target the minimum time for
this condition to exist. Given th at how often this occurs is a
product of frequency, Crowbar effects can be characterized
as internal capacitance.
Lab tests are conducted with Driver Outputs disconnected
from any load. With design verification packaging, bond
wires are removed to aid in the characterization process.
Base on laboratory tests and simulation correlation of those
results, the following equation defines the ISL55110,
ISL55111 Power Dissipation per channel:
P = VDD*3.3e-3 + 10pF*VDD^2*f + 135pF*VH^2*f +
CL*VH^2*f (Watts/Channel)
ISL55110, ISL55111
13 FN6228.1
March 21, 2007
Where:
1. 3.3mA is the quiescent Current from the VD D. This
forms a small portion of the total calculation. When figuring
two channel power cons umption, only include this current
once.
2. 10pF is the approximate parasitic Capacitor
(Inverters, etc.), which the VDD drives
3. 135pF is the approximate parasitic at the DOUT and its
Buffers. This includes the effect of the Crow-bar Current.
4. CL is the Load capacitor being driven
Power Dissipation Discussion
Specifying continuous pulse rates, driver loads and driver
level amplitudes are key in de te rmining power supply
requirements as well as dissipation / cooling necessities.
Driver Output patterns also impact these needs. The faster
the pin activity, the greater the need to supply current and
remove heat.
As detailed in the Power Dissipation Calculation Section,
Power Dissipation of the device is calculated by taking the
DC current of the VDD (logic) and VH Current (Driver rail)
times the respective voltages and adding the product of both
calculations. The average DC current measurements of IDD
and IH should be done while running the device with the
planned VDD and VH levels and driving the required pulse
activity of both channels at the desired operating frequency
and driver loads.
Therefore the user must address power dissipation relative
to the planned operating conditions. Even with a device
mounted per Note 1 or 2 under Thermal Information, given
the high speed pulse rate and amplitude capability of the
ISL55110, ISL55111, it is possible to exceed the +150°C
“absolute-maximum junction tempe ratu re”. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if operating conditions need to
be modified for the device to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to:
where:
•T
JMAX = Maximum junction temperature
•T
AMAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
•P
DMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads.
Power also depends on numb er of chan nels changing state
and frequency of operation. The extent of continuous active
pulse generation will greatly effect dissipation requirements.
The user should evaluate various heat sink/cooling options
in order to control the ambient temperature part of the
equation. This is especially true if th e user’s applications
require continuous, high speed operation. A review of the
Theta-j ratings of the TSSOP and QFN package clearly
show the QFN package to have better thermal
characteristics.
The reader is cautioned against assuming a calculated
level of thermal performance in actual application s. A
careful inspection of con ditions in your application
should be conduc ted. Great care must be taken to
ensure Die Temperature does not exceed 150°C Absolute
Maximum Thermal Limits.
Important Note: The ISL55110, IS L55111 QFN package
metal plane is used for heat sinking of the d evice. It is
electrically connected to the negative supply potential
ground.
Power Supply Sequencing
The ISL55110, ISL55111 refe rences both VDD and the VH
driver supplies with respect to Ground. Therefore apply
VDD, then VH. Digital Inputs should never be open. Do not
apply slow analog ramps to the inputs. Again place
decoupling as close to the package as possible for both VDD
and especially VH.
Special Loading
With most applications the user will usuall y have a special
load requirement. Please contact Intersil for Evaluation
Boards or to request a device characterization to your
requirements in our lab.
PDMAX TJMAX - TAMAX
θJA
---------------------------------------------
=
ISL55110, ISL55111
14 FN6228.1
March 21, 2007
ISL55110, ISL55111
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGD-10)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.25 0.30 5, 8
D 4.00 BSC -
D1 3.75 BSC 9
D2 2.30 2.40 2.55 7, 8
E 4.00 BSC -
E1 3.75 BSC 9
E2 2.30 2.40 2.55 7, 8
e 0.50 BSC -
k0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 3
P- -0.609
θ--129
Rev. 2 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present.
L minus L1 to be equal to or greater than 0.3mm.
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or it s sub sidi ari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6228.1
March 21, 2007
ISL55110, ISL55111
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N8 87
α0o8o0o8o-
Rev. 1 12/00
