FR015L3EZ (15m, -20V) Low-Side Reverse Bias / Reverse Polarity Protector Features Description Up to -20V Reverse-Bias Protection +12V 24-Hour "Withstand" Rating Reverse bias is an increasingly common fault event that may be generated by user error, improperly installed batteries, automotive environments, erroneous connections to third-party chargers, negative "hot plug" transients, inductive transients, and readily available negatively biased rouge USB chargers. Nano Seconds of Reverse-Bias Blocking Response Time 15m Typical Series Resistance at 3.0V Fairchild circuit protection is proud to offer a new type of reverse bias protection devices. The FR devices are low resistance, series switches that, in the event of a reverse bias condition, shut off power and block the negative voltage to help protect downstream circuits. 18m Typical Series Resistance at 2.1V Integrated TVS Over Voltage Suppression MicroFET2x2mm Package Size RoHs Compliant The FR devices are optimized for the application to offer best in class reverse bias protection and voltage capabilities while minimizing size, series voltage drop, and normal operating power consumption. USB VBUS Compatible Applications In the event of a reverse bias application, FR015L3EZ devices effectively provide a full voltage block and can easily protect -0.3V rated silicon. 3V+ Battery Operated Systems Reverse Battery Protection From a power perspective, in normal bias, a 15m FR device in a 0.1A application will generate only 1.5mV of voltage drop or 0.15mW of power loss. In reverse bias, FR devices dissipate less then 10W in a 3V reverse bias event. This type of performance is not possible with a diode solution. 2 to 5 Cell Alkaline Battery Operated Systems USB 1.0, 2.0 and 3.0 Devices USB Charging Mobile Devices Mobile Medical Benefits extend beyond the device. Due to low power dissipation, not only is the device small, but heat sinking requirements and cost can be minimized as well. Toys Any DC Barrel Jack Powered Device Any DC Devices subject to Negative Hot Plug or Inductive Transients Ordering Information Operating Part Number Temperature Range Top Mark -55C ~ 125C 019L FR015L3EZ (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 Package Packing Method 6-Lead, Molded Leadless Package (MLP), Dual, 3000 on Tape & Reel; Non-JEDEC, 2mm Square, Single-Tied DAP 7-inch Reel, 12mm Tape www.fairchildsemi.com 1 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector October 2014 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Diagrams CTL Power Switch Startup Diode Inrush Reducer NEG PO OV Bypass Protection Figure 1. Block Diagram Figure 2. Typical Schematic Pin Configuration Pin 1 CTL NEG POS MicroFET 2x2 mm Figure 3. Pin Assignments Pin Definitions Name Pin Description POS 4 The ground of the load circuit to be protected. Current flows into this pin during normal bias operation. CTL 3 The control pin of the device. A positive voltage on this pin with regard to NEG pin turns the switch on and a negative voltage turns the switch to a high impedance state. NEG 1, 2, 5, 6 The ground of the input power source. Current flows out of this pin during normal bias operation. (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 2 Values are at TA=25C unless otherwise noted. Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Steady-State Normal Operating Voltage between CTL and NEG Pins (VIN = V+ MAX_OP, IIN = 1.5A, Switch On) +8 V+ 24 24-Hour Normal Operating Voltage Withstand Capability between CTL and (1) NEG Pins (VIN = V+ 24, IIN = 1.5A, Switch On) 12 V- MAX_OP Steady-State Reverse Bias Standoff Voltage between CTL and NEG Pins (VIN = V- MAX_OP) -20 V+ MAX_OP (2) IIN Input Current VIN = 3V, Continuous TJ Operating Junction Temperature (2) PD Power Dissipation TA = 25C (see Figure 4) 150 C 2.4 0.9 Human Body Model, JESD22-A114 ESD A (see Figure 4) IDIODE_PULSE Pulsed Diode Forward Current from POS to NEG (300s Pulse) V 8 TA = 25C(2) (see Figure 5) IDIODE_CONT Steady-State Diode Continuous Forward Current from POS to NEG Unit W 2 A 190 2500 Charged Device Model, JESD22-C101 Electrostatic Discharge POS is shorted to CTL System Model, Capability IEC61000-4-2 No external connection between POS and CTL 2000 Contact 5000 Air 7000 Contact 300 Air 3000 V Notes: 1. The V+24 rating is NOT a survival guarantee. It is a statistically calculated survivability reference point taken on qualification devices, where the predicted failure rate is less than 0.01% at the specified voltage for 24 hours. It is intended to indicate the device's ability to withstand transient events that exceed the recommended operating voltage rating. Specification is based on qualification devices tested using accelerated destructive testing at higher voltages, as well as production pulse testing at the V+24 level. Production device field life results may vary. Results are also subject to variation based on implementation, environmental considerations, and circuit dynamics. Systems should never be designed with the intent to normally operate at V+24 levels. Contact Fairchild Semiconductor for additional information. 2. The device power dissipation and thermal resistance (R) are characterized with device mounted on the following FR4 printed circuit boards, as shown in Figure 4 and Figure 5 Figure 4. 1 Square Inch of 2-ounce copper Figure 5. Minimum Pads of 2-ounce Copper Thermal Characteristics Symbol RJA RJA Parameter (2) Thermal Resistance, Junction to Ambient (2) Thermal Resistance, Junction to Ambient (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 Value (see Figure 4) 60 (see Figure 5) 150 Unit C/W www.fairchildsemi.com 3 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Absolute Maximum Ratings Values are at TA = 25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. VIN = +1.7V, IIN = 1.5A 22 30 VIN = +2.1V, IIN = 1.5A 18 25 VIN = +3V, IIN = 1.5A 15 20 VIN = +5V, IIN = 1.5A 14 19 VIN = +3V, IIN = 1.5A, TJ = 125C 22 30 1.0 1.3 Unit Positive Bias Characteristics RON VON Device Resistance, Switch On Input Voltage, VIN, at which Voltage at POS, VPOS, Reaches a Certain Level at Given Current IIN = 100mA, VPOS = 50mV, VNEG = 0V VON / TJ Temperature Coefficient of VON IDIODE_CONT Continuous Diode Forward Current VCTL = VPOS Diode Forward Voltage VCTL = VPOS, IDIODE = 3A, Pulse width < 300s Bias Current Flowing out of NEG Pin during Normal Bias Operation VCTL = 8V, VNEG = 0V, No Load VF IBIAS 0.7 -1.7 0.65 0.80 m V mV/C 2 A 0.95 V 10 A -20 V Negative Bias Characteristics V- MAX_OP Reverse Bias Breakdown Voltage Reverse Bias Breakdown Voltage Temperature Coefficient IIN = -250A, VCTL = VPOS =0V I- Leakage Current from NEG to POS in Reverse-Bias Condition VNEG = 16V, VCTL = VPOS = 0V 1 A tRN Time to Respond to Negative Bias Condition VNEG = 2.7V, VCTL = 0V, CLOAD = 10F, Reverse Bias Startup Inrush Current = 0.2A 50 ns 13 14.5 V V- MAX_OP / TJ 16 mV/C Integrated TVS Performance VZ Breakdown Voltage @ IT IT = 1mA IR Leakage Current from CTL to POS, NEG is Open VCTL - VPOS = 8V 2 10 VCTL - VPOS = -8V -2 -10 Max Pulse Current from CTL to POS VCTL > VPOS 0.6 IPPM VCTL < VPOS 0.4 Clamping Voltage form CTL to POS VCTL > VPOS 15.0 VC VCTL < VPOS 14.3 IEC61000-4-5 8x20s pulse, NEG is Open 12 A A V Dynamic Characteristics CI Input Capacitance between CTL and NEG CS Switch Capacitance between POS and NEG CO Output Capacitance between CTL and POS RC Control Internal Resistance (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 900 VIN = 3V, VNEG = VPOS = 0V, f = 1MHz 133 pF 967 2 www.fairchildsemi.com 4 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Electrical Characteristics 40 35 30 Input Voltage, VIN = 1.7V 25 2.1V 20 3V 15 5V 10 0 4 8 12 16 20 2.0 1.8 ON THE SWITCH (V) VON, MINIMUM INPUT VOLTAGE TURNING RON, SWITCH ON-RESISTANCE (m) TJ = 25C unless otherwise specified. 1.6 1.4 1.2 1.0 0.8 0.0 0.5 IIN, INPUT CURRENT (A) 1.0 o TJ = 25 C 0.8 IIN = 0.1A 0.6 0.9A 0.4 1.5A 0.2 2.0 3.5 5.0 6.5 8.0 2.5 3.0 IIN = 0.1A 21 18 VIN = 3V 15 12 8V 9 6 -75 -50 -25 0 25 50 75 100 125 150 o TJ, JUNCTION TEMPERATURE ( C) Figure 9. Switch On Resistance vs. Junction Temperature at 0.1A Figure 8. Effective Switch Resistance RSW vs. Input Voltage VIN 24 100 IIN = 1.5A PEAK PACKAGE POWER (W) RON, SWITCH ON-RESISTANCE (m) 2.0 24 VIN, INPUT VOLTAGE (V) 21 18 VIN = 3V 15 12 8V 9 6 -75 1.5 Figure 7. Minimum Input Voltage to Turn On Switch vs. Current at 50mV Switch Voltage Drop RON, SWITCH ON-RESISTANCE (m) RSW, EFFECTIVE SWITCH RESISTANCE () Figure 6. Switch On Resistance vs. Switch Current 0.0 0.5 1.0 IIN, INPUT CURRENT (A) -50 -25 0 25 50 75 1 0.1 1E-3 100 125 150 0.01 0.1 1 10 100 1000 t, PULSE WIDTH (s) o TJ, JUNCTION TEMPERATURE ( C) Figure 10. Switch On Resistance vs. Junction Temperature at 1.5A (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 10 Figure 11. Single-Pulse Maximum Power vs. Time www.fairchildsemi.com 5 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Typical Characteristics FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Typical Characteristics (Continued) IF, STARTUP DIODE FORWARD CURRENT (A) TJ = 25C unless otherwise specified. 100 VPOS = VCTL = 0V 10 1 o TJ = 125 C 0.1 o 25 C 0.01 1E-3 0.2 o -55 C 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VF, STARTUP DIODE FORWARD VOLTAGE (V) Figure 12. Startup Diode Current vs. Forward Voltage (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 6 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Application Test Configurations Figure 13. Startup Test Circuit - Normal Bias with FR015L3EZ Device Figure 14. Startup Test Circuit - Reverse Bias with FR015L3EZ Device (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 7 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Application Test Configurations Figure 15. Startup Test Circuit - No Reverse Polarity Protection Typical Application Waveforms VIN, 2V/div. The input voltage between CTL and NEG VOUT, 2V/div. The output voltage between CTL and POS VD, 1V/div. The startup diode voltage between POS and NEG iIN, 5A/div. The input current flowing out of NEG Time: 2s/div Figure 16. Normal Bias Startup Waveform, VIN=3V, V1=3V, C1=5200F, C2=C3=10F, R1=R2=33k, R3=2 (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 8 VIN, 5V/div. The input voltage between CTL and NEG VD, 5V/div. The startup diode voltage between POS and NEG VOUT, 0.5V/div. The output voltage between CTL and POS Time: 100ns/div Figure 17. Reverse Bias Startup Waveform, VIN=3V, V1=3V, C1=5200F, C2=C3=10F, R1=R2=33k, R3=2 VIN, 1V/div. The voltage applied on the load circuit iIN, 10A/div. The input current Time: 2s/div Figure 18. Startup Waveform without FR015L3EZ Device, VIN=3V, V1=3V, C1=5200F, C2=C3=10F, R1=R2=33k, R3=2 (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 9 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Typical Application Waveforms (Continued) The FR015L3EZ is capable of being turned on at a voltage as low as 1.5V, therefore is especially suitable for low voltage application like AA, AAA or single lithium-ion battery operated devices. The voltage and current waveforms in Figure 16 and Figure 18 are both captured with a 2 load at 3V input. Figure 16, while the reverse bias protector is present, the input voltage, VIN, and the output voltage, VO, are separated and look different. When this reverse bias protector is removed, VIN and VO merge, as shown in Figure 18 as VIN. This VIN is also the voltage applied to the load circuit. It can be seen that, with reverse bias protection, the voltage applied to the load and the current flowing into the load look very much the same as without reverse bias protection. When the DC power source is connected to the circuit (refer to Figure 1 and Figure 2), the built-in startup diode initially conducts the current such that the load circuit powers up. Due to the initial diode voltage drop, the FR015L3EZ effectively reduces the peak inrush current of a hot plug event. Under these test conditions, the input inrush current reaches about 19A peak. While the current flows, the input voltage increases. The speed of this input voltage increase depends on the time constant formed by the load resistance R3 and load capacitance C3, assuming the input voltage source holds itself during turn on. The larger the time constant, the slower the input voltage increase. As the input voltage approaches a level equal to the protector's turn-on voltage, VON, the protector turns on and operates in Low-Resistance Mode as defined by VIN and operating current IIN. In Figure 16, negative voltage spikes are seen on VIN and VD before VIN starts to rise from 0; and in both Figures 16 and 18, negative input current is seen after FR015L3EZ is fully turned on. These phenomena are a combined effect of parasitic inductance and all the capacitors in the input voltage control circuit enclosed in the broken line as shown in Figures 13 to 15. This is not a problem as long as the load circuit doesn't see a negative voltage at anytime, which is what the reverse bias protector is meant for. Indeed, we can see from Figures 16 and 18, the output voltage on the load circuit is always equal to or greater than 0V. In the event of a negative voltage transient between CTL and NEG, or when the DC power source, VIN, is reversely connected to the circuit, while no residual voltage presents between CTL and POS, the device blocks the flow of current and holds off the voltage, thereby protecting the load circuit. Figure 17 shows the startup waveforms while a passive load circuit is reversely biased. It can be clearly seen that the output voltage is near 0 or at a level that is harmless to the load circuit. Benefits of Reverse Bias Protection The most important benefit is, of course, to prevent accidently reverse-biased voltage from damaging the load circuit. Another benefit is that the peak startup inrush current can be reduced. How fast the input voltage rises, the input/output capacitance, the input voltage, and how heavy the load is determine how much the inrush current can be reduced. In this specific 3V / 2A application, for example, the inrush current has been reduced from 24A to 19A, a 21% reduction. This can offer a system designer the option of increasing C3 while keeping "effective" load circuit capacitance down. Figure 18 shows the voltage and current waveforms when no reverse bias protection is implemented. In (c) 2012 Fairchild Semiconductor Corporation FR015L3EZ * Rev. A2 www.fairchildsemi.com 10 FR015L3EZ -- Low Side Reverse Bias / Reverse Polarity Protector Application Information 2.0 0.05 C A B 2X 2.0 1.70 (0.20) 1.00 PIN#1 IDENT 0.05 C TOP VIEW No Traces allowed in this Area 4 6 2X 1.05 2.30 0.10 C 0.47(6X) 0.08 C 1 SIDE VIEW C 0.40(6X) 0.65 RECOMMENDED LAND PATTERN OPT 1 SEATING PLANE (0.15) 3 (0.50) 1.70 PIN #1 IDENT 1 0.45 (0.20) (0.20)4X 3 1.00 6 (6X) 4 (0.50) 1.05 6 4 0.65 1.30 0.10 0.05 BOTTOM VIEW NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO-229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E. DRAWING FILENAME: MKT-MLP06Lrev4. (6X) C A B C 0.66 2.30 0.47(6X) 1 0.65 3 0.40(7X) RECOMMENDED LAND PATTERN OPT 2 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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