Nonvolatile Memory, Dual
1024-Position Digital Potentiometer
Enhanced Product AD5235-EP
Rev. B Document Feedback
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FEATURES
Dual-channel, 1024-position resolution
25 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement
instructions
SPI-compatible serial interface
+2.7 V to +5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined
information
100-year typical data retention, TA = 55°C
Power-on refreshed with EEMEM settings
Enhanced Features
Supports defense and aerospace applications (AQEC)
Temperature range: −40°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
GENERAL DESCRIPTION
The AD5235-EP is a dual-channel, nonvolatile memory,1
digitally controlled potentiometer2 with 1024-step resolution.
The device performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient performance.
The AD5235-EP’s versatile programming via an SPI®-compatible
serial interface allows 16 modes of operation and adjustment
including scratchpad programming, memory storing and restoring,
increment/decrement, ±6 dB/step log taper adjustment, wiper setting
readback, and extra EEMEM1 for user-defined information such as
memory data for other components, look-up tables, or system
identification information.
FUNCTIONAL BLOCK DIAGRAM
ADDR
DECODE
AD5235-EP
RDAC1
SERIAL
INTERFACE
CS
CLK
SDI
SDO
PR
WP
RDY
RDAC1
REGISTER
EEMEM1
RDAC2
REGISTER
EEMEM2
26 BYTES
RTOL* USER EEMEM
POWER-ON
RESET
W1
B1
RDAC2
W2
B2
A1
VDD
A2
VSS
GND
EEMEM
CONTROL
*RAB TOLERANCE
09185-001
Figure 1.
In scratchpad programming mode, a specific setting can be
programmed directly to the RDAC2 register that sets the resistance
between Terminal W and Terminal A, and Terminal W and
Terminal B. This setting can be stored into the EEMEM and
is restored automatically to the RDAC register during system
power-on.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM contents.
To simplify the programming, the independent or simultaneous
linear-step increment or decrement commands can be used to move
the RDAC wiper up or down, one step at a time. For logarithmic
±6 dB changes in the wiper setting, the left or right bit shift
command can be used to double or halve the RDAC wiper setting.
The AD5235-EP patterned resistance tolerance is stored in the
EEMEM. Therefore, in readback mode, the host processor can
know the actual end-to-end resistance. The host can execute the
appropriate resistance step through a software routine that simplifies
open-loop applications as well as precision calibration and
tolerance matching applications.
The AD5235-EP is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
Full details about this enhanced product, including theory of
operation, register details, and applications information, are
available in the AD5235 data sheet, which should be consulted
in conjunction with this data sheet.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
AD5235-EP Enhanced Product
Rev. B | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Interface Timing and EEMEM Reliability Characteristics ..... 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ..............................................9
Test Circuits ..................................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/2018—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 14
7/2012—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Changes to Electrical Characteristics Section and Table 1 ......... 3
Changes to Interface Timing and EEMEM Reliability
Characteristics Section and Table 2 ............................................... 5
Changes to Typical Performance Characteristics Section ........... 9
Added Figure 14 and Figure 16, Renumbered Sequentially ..... 10
Deleted Figure 21 ............................................................................ 11
Added Figure 23 .............................................................................. 12
7/2010—Revision 0: Initial Version
Enhanced Product AD5235-EP
Rev. B | Page 3 of 14
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
(All RDACs)
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
−2
+2
LSB
Nominal Resistor Tolerance ∆RAB/RAB Code = full-scale −8 +8 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW IW = 1 V/RWB, VDD = 5 V, code =
half scale
30 65 Ω
I
W
= 1 V/R
WB
, V
DD
= 3 V, code =
half scale
50
Ω
Nominal Resistance Match RAB1/RAB2 Code = full-scale, TA = 25°C ±0.1 %
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (All RDACs)
Resolution N 10 Bits
Differential Nonlinearity3 DNL −1 +1 LSB
Integral Nonlinearity3 INL −1 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Code = half scale 15 ppm/°C
Full-Scale Error
V
WFSE
Code = full-scale
−7
0
LSB
Zero-Scale Error VWZSE Code = zero scale 0 5 LSB
RESISTOR TERMINALS
Terminal Voltage Range
4
V
A
, V
B
, V
W
V
SS
V
DD
V
Capacitance Ax, Bx5 CA, CB f = 1 MHz, measured to GND,
code = half scale
11 pF
Capacitance Wx5 CW f = 1 MHz, measured to GND,
code = half scale
80 pF
Common-Mode Leakage Current5, 6
I
CM
V
W
= V
DD
/2
0.01
±1
µA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low
V
IL
With respect to GND, V
DD
= 5 V
0.8
V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
2.0 V
Input Logic Low VIL With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
0.5 V
Output Logic High (SDO, RDY) VOH RPULL-UP = 2.2 kΩ to 5 V 4.9 V
Output Logic Low VOL IOL = 1.6 mA, VLOGIC = 5 V 0.4 V
Input Current IIL VIN = 0 V or VDD ±2.25 µA
Input Capacitance5 CIL 5 pF
AD5235-EP Enhanced Product
Rev. B | Page 4 of 14
Parameter Symbol Conditions Min Typ1 Max Unit
POWER SUPPLIES
Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 2 7 µA
Negative Supply Current
I
SS
V
IH
= V
DD
or V
IL
= GND, V
DD
= +2.5 V,
VSS = −2.5 V
−6
−2
µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
2 mA
ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current7 IDD (restore) VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
320 µA
ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA
Power Dissipation8 PDISS VIH = VDD or VIL = GND 10 40 µW
Power Supply Sensitivity5 PSS ΔVDD = 5 V ± 10% 0.006 0.01 %/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth BW −3 dB, VDD/VSS = ±2.5 V 125 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.009 %
VW Settling Time tS VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to Code 0x200
4 µs
Resistor Noise Density eN_WB TA = 25°C 20
nV/√Hz
Crosstalk (CW1/CW2) CT VA = VDD, VB = 0 V, measured VW1
with VW2 making full-scale change
30
nV-s
Analog Crosstalk
C
TA
VDD = VA1 = +2.5 V,
VSS = VB1 = −2.5 V, measured
VW1 with VW2 = 5 V p-p at f = 1 kHz,
Code 1 = 0x200, Code 2 = 0x3FF
−110
dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V (see Figure 25).
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.
7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To
minimize power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).
8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
Enhanced Product AD5235-EP
Rev. B | Page 5 of 14
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
Clock Cycle Time (tCYC) t1 20 ns
CS Setup Time t2 10 ns
CLK Shutdown Time to CS Rise t3 1 tCYC
Input Clock Pulse Width t4, t5 Clock level high or low 10 ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire t8 40 ns
CS to SDO-SPI Line Release t9 50 ns
CLK to SDO Propagation Delay2 t10 RP = 2.2 kΩ, CL < 20 pF 50 ns
CLK to SDO Data Hold Time
t
11
R
P
= 2.2 kΩ, C
L
< 20 pF
0
ns
CS High Pulse Width3 t12 10 ns
CS High to CS High3 t13 4 tCYC
RDY Rise to CS Fall t14 0 ns
CS Rise to RDY Fall Time t15 0.15 0.3 ms
Store EEMEM Time4, 5 t16 Applies to Instructions 0x2, 0x3 15 50 ms
Read EEMEM Time
4
t
16
Applies to Instructions 0x8, 0x9, 0x10
7
30
µs
CS Rise to Clock Rise/Fall Setup t17 10 ns
Preset Pulse Width (Asynchronous)6 tPRW 50 ns
Preset Response Time to Wiper Setting6 tPRESP PR pulsed low to refresh wiper positions 30 µs
Power-On EEMEM Restore Time6 tEEMEM 30 µs
FLASH/EE MEMORY RELIABILITY
Endurance7 TA = 25°C 1 MCycles
100 kCycles
Data Retention8
100
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3 Valid for commands that do not activate the RDY pin.
4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 µs.
5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6 Not shown in Figure 2 and Figure 3.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +125°C.
8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
AD5235-EP Enhanced Product
Rev. B | Page 6 of 14
Timing Diagrams
CPOL = 1
t
12
t
13
t3
t17
t9
t11
t
5
t
4
t
2
t
1
CLK
t
8
B24* B23 (MS B) B0 (L S B)
B23 (MS B)
HIGH
OR LOW HIGH
OR LOW
B23 B0
B0 (L S B)
RDY
CPHA = 1
t
10
t
7
t
6
t
14
t
15
t
16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY T HE LSB O F T HE CHARACTER PRE V IO USLY T RANS M ITTED.
THE CP OL = 1 MI CROCONTRO LLE R COMM AND ALIGNS THE INCOMING DATATO THE POSITIVE EDGE OF THE CLOCK.
SDO
SDI
CS
09185-002
Figure 2. CPHA = 1 Timing Diagram
t12
t13
t3
t17
t9
t
11
t5
t4
t2
t1
CLK
CPOL = 0
t
8
B23 (MS B OUT) B0 (LSB)
SDO
B23 (MS B IN)
B23 B0
HIGH
OR LOW HIGH
OR LOW
B0 (LSB)
SDI
RDY
CPHA = 0
t10
t7
t6
t14
t15 t16
*THE E X TRA BI T T HAT IS NOT DE FINE D IS NO RMALLY THE MS B OF THE CHARACT E R JUS T RECE IVED.
THE CP OL = 0 MI CROCONTRO LLE R COMM AND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
*
CS
09185-003
Figure 3. CPHA = 0 Timing Diagram
Enhanced Product AD5235-EP
Rev. B | Page 7 of 14
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
SS
to GND
+0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW
Pulsed1 ±2.5 mA
Continuous
±1.1 mA
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec)
215°C
Infrared (15 sec) 220°C
Thermal Resistance
Junction-to-Ambient, θJA 150°C/W
Junction-to-Case, θJC 28°C/W
Package Power Dissipation (TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package and the maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Includes programming of nonvolatile memory.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5235-EP Enhanced Product
Rev. B | Page 8 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDI
SDO
GND
A1
V
SS
W1
CLK
B1
CS
PR
WP
V
DD
A2
W2
B2
RDY
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5235-EP
TOP VIEW
(Not to Scale)
09185-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
4 GND Ground Pin, Logic Ground Reference.
5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
35 mA for 30 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP
high. Tie WP to VDD, if not used.
14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PR.
Enhanced Product AD5235-EP
Rev. B | Page 9 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
DIGITAL CODE
INL ERROR (LSB)
–40
+25
+85
+125
09185-005
0 200 400 600 800 1000
Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
0.04
0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
DNL ERROR (LSB)
DIGITAL CODE
–40
+25
+85
+125
09185-006
0 200 400 600 800 1000
Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0 200 400 600 800 1000
R-INL ERROR (LSB)
DIGITAL CODE
–40
+25
+85
+125
09185-007
Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 200 400 600 800 1000
R-DNL ERROR (LSB)
DIGITAL CODE
–40
+25
+85
+125
09185-008
Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/°C)
200
180
160
140
120
100
80
60
40
20
00 1023768512256
09185-009
Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco
CODE (Decimal)
RHEOSTAT MODE TEMPCO (ppm/°C)
200
180
160
140
120
100
80
60
40
20
00 1023768512256
09185-010
Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco
AD5235-EP Enhanced Product
Rev. B | Page 10 of 14
CODE (Decimal)
0 200 400 800600 1000
WIPER ON RESISTANCE (Ω)
60
50
40
30
20
10
0
2.7V
3.0V
3.3V
5.0V
5.5V
09185-011
Figure 11. Wiper On Resistance vs. Code
09185-012
TEMPERATURE (°C)
–55 –50 –40 –20 0 25 40 60 85 100 110 125
I
DD
/I
SS
(µA)
3
–3
–2
–1
0
1
2
I
DD
= 2.7V
I
DD
= 3.3V
I
DD
= 3.0V
I
DD
= 5.5V
I
DD
= 5.0V
I
SS
= 2.7V
I
SS
= 3.3V
I
SS
= 3.0V
I
SS
= 5.5V
I
SS
= 5.0V
Figure 12. IDD vs. Temperature
FREQUENCY (MHz)
11098765432
I
DD
(µA)
50
10
20
30
40
0
FULL SCALE
MIDSCALE
ZERO SCALE
09185-013
Figure 13. IDD vs. Clock Frequency
0
100
200
300
400
I
DD
(µA)
VDIO (V)
2.7V
3.0V
3.3V
5.0V
5.5V
012345
09185-014
Figure 14. IDD vs. Digital Input Voltage
0.12
0
0.02
0.04
0.06
0.08
0.10
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09185-015
Figure 15. THD + Noise vs. Frequency
10
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10
THD + N (%)
AMPLITUDE (V rms)
09185-016
Figure 16. THD + Noise vs. Amplitude
Enhanced Product AD5235-EP
Rev. B | Page 11 of 14
FREQUENCY (Hz)
1k 10k 100k 1M
GAIN (dB)
3
–3
0
–6
–9
–12
V
DD
/V
SS
=±2.5V
V
A
= 1V rms
D = MIDSCALE
f
–3dB
= 125kHz
09185-017
Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 31)
1k 10k 100k 1M
GAIN (dB)
0
–20
–10
–30
–40
–50
–60
CODE 0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
09185-018
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code (See Figure 31)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M
PSRR (dB)
–80
–60
–70
–50
–40
–30
–20
–10
0V
DD
= 5V ± 10% AC
V
SS
= 0V, V
A
= 4V, V
B
= 0V
MEASURED AT V
W
WITH CODE = 0x200
T
A
= 25°C
09185-019
Figure 19. PSRR vs. Frequency
V
DD
= 5V
V
A
= 5V
V
B
= 0V
T
A
= 25°C
1V/DIV
10µs/DIV
V
DD
V
W
(FULL SCALE)
09185-020
Figure 20. Power-On Reset
TIME (µs)
0 20406080100120 144
AMPLITUDE (V)
2.5196
2.484
2.488
2.492
2.496
2.500
2.504
2.508
2.512
2.516
2.4796
V
DD
= V
SS
= 5V
CODE = 0x200 TO 0x1FF
09185-021
Figure 21. Midscale Glitch Energy
02816-023
CS (5V/DIV)
CLK (5V/DIV)
SDI (5V/DIV)
I
DD
(2mA/DIV)
V
DD
= 5V
T
A
= 25°C
Figure 22. IDD vs. Time When Storing Data to EEMEM
AD5235-EP Enhanced Product
Rev. B | Page 12 of 14
2.60
2.55
2.50
2.45
2.40 00.5 1.0 1.5 2.0
WIPER VOLTAGE (V)
TIME (µs)
09185-024
Figure 23. Digital Feedthrough
CODE ( Decimal )
100
1
0.01 1023
THE O RE CTI CAL (I
WB_MAX
– mA)
0.1
10
896768640512384128 2560
V
A
= V
B
= OPEN
T
A
= 25° C
R
AB
= 25kΩ
09185-125
Figure 24. IWB_MAX vs. Code
Enhanced Product AD5235-EP
Rev. B | Page 13 of 14
TEST CIRCUITS
Figure 25 to Figure 35 define the test conditions used in the Specifications section.
A
W
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
09185-026
Figure 25. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
A
W
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V+/2
N
09185-027
Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL)
A
W
B
DUT IW= VDD/RNOMINAL
V
MS1
V
MS2
V
W
RW = [VMS1 – VMS2]/IW
09185-028
Figure 27. Wiper Resistance
AW
BV
MS
V+ = V
DD
±10%
PSRR (dB) = 20 LOG
V
MS
∆V
DD
()
~
V
A
V
DD
∆V
MS%
∆V
DD%
PSS (%/%) =
V+
∆
09185-029
Figure 28. Power Supply Sensitivity (PSS, PSRR)
OFFSET BIAS
OFFSET
GND
ABDUT
W
5V
VIN
VOUT
OP279
09185-030
Figure 29. Inverting Gain
OFFSET BIAS
OFFSET
GND ABDUT
W
5
V
V
IN
V
OUT
OP279
09185-031
Figure 30. Noninverting Gain
OFFSET
GND
A
B
DUT
W
+15
V
V
IN
V
OUT
OP42
–15V
2.5V
09185-032
Figure 31. Gain vs. Frequency
+
–
DUT
CODE = 0x00
0.1V
V
SS
TO V
DD
R
SW
=0.1
V
I
SW
I
SW
W
B
A = NC
09185-033
Figure 32. Incremental On Resistance
DUT
V
SS
I
CM
W
B
V
DD
NC
NC
V
CM
GND
A
NC = NO CONNECT
0
9185-034
Figure 33. Common-Mode Leakage Current
A1
RDAC1 RDAC2
W1
NC
B1
A2
W2
B2
CTA = 20 LOG[VOUT/VIN]
NC = NO CONNECT
VIN
VOUT
VSS
VDD
0
9185-035
Figure 34. Analog Crosstalk
200µAI
OL
200µAI
OH
V
OH
(MIN)
OR
V
OL
(MAX)
TO OUTPUT
PIN C
L
50pF
09185-036
Figure 35. Load Circuit for Measuring VOH and VOL (The diode bridge test
circuit is equivalent to the application circuit with RPULL-UP of 2.2 kΩ.)
AD5235-EP Enhanced Product
Rev. B | Page 14 of 14
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Temperature Range Package Description Package Option
AD5235BRU25-EP-RL7 25 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
AD5235BRUZ25-EP-R7 25 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
1 Z = RoHS Compliant Part.
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D09185-0-1/18(B)
