LTC3612
1
3612fa
Typical applicaTion
FeaTures
applicaTions
DescripTion
3A, 4MHz Monolithic
Synchronous Step-Down
DC/DC Converter
The LTC
®
3612 is a low quiescent current monolithic syn-
chronous buck regulator using a current mode, constant
frequency architecture. The no-load DC supply current
in sleep mode is only 70µA while maintaining the output
voltage (Burst Mode operation) at no load, dropping to zero
current in shutdown. The 2.25V to 5.5V input supply voltage
range makes the LTC3612 ideally suited for single Li-Ion
as well as fixed low voltage input applications. 100% duty
cycle capability provides low dropout operation, extending
the operating time in battery-powered systems.
The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
For switching noise-sensitive applications, the LTC3612
can be synchronized to an external clock at up to 4MHz.
Forced continuous mode operation in the LTC3612 reduces
noise and RF interference. Adjustable compensation allows
the transient response to be optimized over a wide range
of loads and output capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external catch diode, saving
external components and board space. The LTC3612 is
offered in a leadless 20-pin 3mm × 4mm QFN or a thermally
enhanced 20-pin TSSOP package.
Efficiency and Power Loss vs Load Current
n 3A Output Current
n 2.25V to 5.5V Input Voltage Range
n Low Output Ripple Burst Mode
®
Operation: IQ = 70µA
n ±1% Output Voltage Accuracy
n Output Voltage Down to 0.6V
n High Efficiency: Up to 95%
n Low Dropout Operation: 100% Duty Cycle
n Shutdown Current: ≤1µA
n Adjustable Switching Frequency: Up to 4MHz
n Optional Active Voltage Positioning (AVP) with
Internal Compensation
n Selectable Pulse-Skipping/Forced Continuous/
Burst Mode Operation with Adjustable Burst Clamp
n Programmable Soft-Start
n Inputs for Start-Up Tracking or External Reference
n DDR Memory Mode, IOUT = ±1.5A
n Available in Thermally Enhanced 20-Pin
(3mm × 4mm) QFN and TSSOP Packages
n Point-of-Load Supplies
n Distributed Power Supplies
n Portable Computer Systems
n DDR Memory Termination
n Handheld Devices L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466,
6611131.
RUN
TRACK/SS
RT/SYNC
PGOOD
ITH
SGND
PGND
VIN
2.5V TO 5.5V
PVIN_DRV
DDR
SVIN
LTC3612 SW
PVIN
560nH
665k
210k
3612 TA01a
22µF
s2
MODE VFB
47µF
VOUT
2.5V
3A
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
POWER LOSS (W)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3612 TA01b
0
10
0.001
1
0.1
0.01
10
VIN = 5V
VIN = 3.3V
VIN = 2.8V
LTC3612
2
3612fa
absoluTe MaxiMuM raTings
PVIN, SVIN, PVIN_DRV Voltages ..................... –0.3V to 6V
SW Voltage ..................................–0.3V to (PVIN + 0.3V)
ITH, RT/SYNC Voltages ............... –0.3V to (SVIN + 0.3V)
DDR, TRACK/SS Voltages ........... –0.3V to (SVIN + 0.3V)
MODE, RUN, VFB Voltages .......... –0.3V to (SVIN + 0.3V)
PGOOD Voltage ............................................ –0.3V to 6V
(Notes 1, 11)
20 19 18 17
7 8
TOP VIEW
21
UDC PACKAGE
20-LEAD (3mm s 4mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
DDR
RT/SYNC
SGND
NC
SW
SW
PGOOD
RUN
SVIN
PVIN_DRV
SW
SW
TRACK/SS
ITH
VFB
MODE
NC
PVIN
PVIN
NC
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
SVIN
RUN
PGOOD
MODE
VFB
ITH
TRACK/SS
DDR
RT/SYNC
SGND
PVIN_DRV
SW
NC
SW
PVIN
PVIN
SW
NC
SW
NC
21
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3612EUDC#PBF LTC3612EUDC#TRPBF LDQT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3612IUDC#PBF LTC3612IUDC#TRPBF LDQT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3612EFE#PBF LTC3612EFE#TRPBF LTC3612FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3612IFE#PBF LTC3612IFE#TRPBF LTC3612FE 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Operating Junction Temperature Range
(Notes 2, 11) .......................................... –40°C to 125°C
Storage Temperature .............................. –65°C to 150°C
Reflow Peak Body Temperature (QFN) .................. 260°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
LTC3612
3
3612fa
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT/SYNC = SVIN, unless otherwise specified (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range l2.25 5.5 V
VUVLO Undervoltage Lockout Threshold SVIN Ramping Down
SVIN Ramping Up
l
l
1.7
2.25
V
V
VFB Feedback Voltage Internal Reference (Notes 3, 4) VTRACK/SS = SVIN, VDDR = 0V
0°C < TJ < 85°C
–40°C < TJ < 125°C
l
0.594
0.591
0.6
0.606
0.609
V
V
Feedback Voltage External Reference
(Note 7)
(Notes 3, 4) VTRACK/SS = 0.3V, VDDR = SVIN 0.289 0.3 0.311 V
(Notes 3, 4) VTRACK/SS = 0.5V, VDDR = SVIN 0.489 0.5 0.511 V
IFB Feedback Input Current VFB = 0.6V l±30 nA
∆VLINEREG Line Regulation SVIN = PVIN = 2.25V to 5.5V
(Notes 3, 4) TRACK/SS = SVIN
l0.2 %/V
∆VLOADREG Load Regulation ITH from 0.5V to 0.9V (Notes 3, 4)
VITH = SVIN (Note 5)
0.25
2.6
%
%
ISActive Mode VFB = 0.5V, VMODE = SVIN (Note 6) 1100 µA
Sleep Mode VFB = 0.7V, VMODE = 0V, ITH = SVIN
(Note 5)
70 100 µA
VFB = 0.7V, VMODE = 0V (Note 4) 120 160 µA
Shutdown SVIN = PVIN = 5.5V, VRUN = 0V 0.1 1 µA
RDS(ON) Top Switch On-Resistance PVIN = 3.3V (Note 10) 70 mΩ
Bottom Switch On-Resistance PVIN = 3.3V (Note 10) 45 mΩ
ILIM Top Switch Current Limit Sourcing (Note 8), VFB = 0.5V
Duty Cycle <35%
Duty Cycle = 100%
5.2
4
6
6.8
A
A
Bottom Switch Current Limit Sinking (Note 8), VFB = 0.7V,
Forced Continuous Mode
–3 –4 –5 A
gm(EA) Error Amplifier Transconductance –5µA < IITH < 5µA (Note 4) 200 µS
IEAO Error Amplifier Max Output Current (Note 4) ±30 µA
tSS Internal Soft-Start Time VFB from 0.06V to 0.54V,
TRACK/SS = SVIN
0.65 1 1.5 ms
VTRACK/SS Enable Internal Soft-Start (Note 7 ) 0.62 V
tTRACK/SS_DIS Soft-Start Discharge Time at
Start-Up
70 µs
RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistor at
Start-Up
200 Ω
fOSC Oscillator Frequency RT/SYNC = 370k l0.8 1 1.2 MHz
Internal Oscillator Frequency VRT/SYNC = SVIN l1.8 2.25 2.7 MHz
fSYNC Synchronization Frequency 0.3 4 MHz
VRT/SYNC SYNC Level High 1.2 V
SYNC Level Low . 0.3 V
ISW(LKG) Switch Leakage Current SVIN = PVIN = 5.5V, VRUN = 0V 0.1 1 µA
VDDR DDR Option Enable Voltage SVIN – 0.3 V
VMODE
(Note 9)
Internal Burst Mode Operation 0.3 V
Pulse-Skipping Mode SVIN – 0.3 V
Forced Continuous Mode 1.1 SVIN • 0.58 V
External Burst Mode Operation 0.45 0.8 V
LTC3612
4
3612fa
Efficiency vs Load Current
(VMODE = 0V)
Efficiency vs Load Current
(VMODE = 0V)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3612 is tested under pulsed load conditions such that
TJ
≈
TA. The LTC3612E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3612I is guaranteed over the full –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (PD, in watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT/SYNC = SVIN, unless otherwise specified (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Power Good Voltage Windows TRACK/SS = SVIN, Entering Window
VFB Ramping Up
VFB Ramping Down
–3.5
3.5
–6
6
%
%
TRACK/SS = SVIN, Leaving Window
VFB Ramping Up
VFB Ramping Down
9
–9
11
–11
%
%
tPGOOD Power Good Blanking Time Entering and Leaving Window 70 105 140 µs
RPGOOD Power Good Pull-Down On-Resistance 8 17 33 Ω
VRUN RUN Voltage Input High
Input Low
l
l
1
0.4
V
V
Note 3: This parameter is tested in a feedback loop which servos VFB to
the midpoint for the error amplifier (VITH = 0.75V).
Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SVIN enables the internal compensation and
AVP mode.
Note 6: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 7: See description of the TRACK/SS pin in the Pin Functions section.
Note 8: In sourcing mode the average output current is flowing out of SW
pin. In sinking mode the average output current is flowing into the SW Pin.
Note 9: See description of the MODE pin in the Pin Functions section.
Note 10: Guaranteed by correlation and design to wafer level
measurements for QFN packages.
Note 11: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Typical perForMance characTerisTics
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3612 G01
0
10
VIN = 5V
VIN = 3.3V
VIN = 2.5V
VOUT = 1.8V
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3612 G02
0
10
VIN = 5V
VIN = 3.3V
VIN = 2.5V
VOUT = 1.2V
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
LTC3612
5
3612fa
Typical perForMance characTerisTics
Efficiency vs Load Current
Efficiency vs Input Voltage
(VMODE = 0V)
Efficiency vs Frequency
(VMODE = 0V), IOUT = 1A
Load Regulation Line Regulation Burst Mode Operation
Pulse-Skipping Mode Operation Forced Continuous Mode Operation
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3612 G03
0
10
Burst Mode
EXTERNAL
CLAMP = 0.7V
Burst Mode
INTERNAL
CLAMP
PULSE-
SKIPPING
MODE
FORCED
CONTINUOUS
MODE
VOUT = 1.8V
INPUT VOLTAGE (V)
2.25
30
EFFICIENCY (%)
40
60
70
80
100
3612 G04
50
90
3.75
3.25 5.25
2.75 4.25 4.75
IOUT = 3mA
IOUT = 300mA
IOUT = 1A
IOUT = 3A
VOUT = 1.8V
FREQUENCY (MHz)
0.5
82
EFFICIENCY (%)
83
84
85
86
95
89
91
93
94
92
88
90
1.0 1.5 2.0 3.02.5 3.5
3612 G05
4.0 4.5
87
1µH
0.68µH
0.33µH
VOUT = 1.8V
OUTPUT CURRENT (mA)
0
–0.3
VOUT ERROR (%)
–0.1
0.3
0.5
0.7
2000
1.5
3612 G06
0.1
1000
500 2500
1500 3000
0.9
1.1
1.3
FORCED CONTINUOUS MODE
INTERNAL Burst Mode OPERATION
PULSE-SKIPPING MODE
VOUT = 1.8V
INPUT VOLTAGE (V)
2.20
–0.3
VOUT ERROR (%)
–0.2
–0.1
0
0.1
0.3
2.75 3.30 3.85 4.40
3612 G07
4.95 5.50
0.2
VOUT
20mV/DIV
IL
500mA/DIV
20µs/DIV 3612 G08
VOUT = 1.8V
IOUT = 75mA
VMODE = 0V
VOUT
20mV/DIV
IL
500mA/DIV
20µs/DIV 3612 G09
VOUT = 1.8V
IOUT = 75mA
VMODE = 3.3V
VOUT
20mV/DIV
IL
200mA/DIV
1µs/DIV 3612 G10
VOUT = 1.8V
IOUT = 100mA
VMODE = 1.5V
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
LTC3612
6
3612fa
Sinking Current
Load Step Transient in Forced
Continuous Mode without AVP Mode
Load Step Transient in Forced
Continuous Mode with AVP Mode
Load Step Transient in Forced
Continuous Mode Sourcing and
Sinking Current
VOUT
200mV/DIV
IL
1A/DIV
50µs/DIV 3612 G13
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
COMPENSATION FIGURE 1
VOUT
100mV/DIV
IL
1A/DIV
50µs/DIV 3612 G14
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
VITH = VIN
OUTPUT CAPACITOR VALUE FIGURE 1
VOUT
200mV/DIV
IL
2A/DIV 0A
50µs/DIV 3612 G15
VOUT = 1.8V
ILOAD = –1.5A TO 3A
VMODE = 1.5V
COMPENSATION FIGURE 1
VOUT
20mV/DIV
SW
2V/DIV
IL
500mA/DIV
1µs/DIV 3612 G16
VOUT = 1.2V
IOUT = –1A
VMODE = 1.5V
Typical perForMance characTerisTics
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Load Step Transient in
Pulse-Skipping Mode
Load Step Transient in
Burst Mode Operation
VOUT
200mV/DIV
IL
1A/DIV
50µs/DIV 3612 G11
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 3.3V
COMPENSATION FIGURE 1
VOUT
200mV/DIV
IL
1A/DIV
50µs/DIV 3612 G12
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 0V
COMPENSATION FIGURE 1
LTC3612
7
3612fa
Internal Start-Up in Forced
Continuous Mode
Tracking Up/Down in
Forced Continuous Mode,
DDR Pin Tied to 0V
Tracking Up/Down in Forced
Continuous Mode, DDR Pin Tied
to SVIN
Reference Voltage
vs Temperature
Switch On-Resistance
vs Input Voltage
VOUT
500mV/DIV
RUN
1V/DIV
IL
1A/DIV
PGOOD
2V/DIV
500µs/DIV 3612 G17
VOUT = 1.8V
IOUT = 3A
VMODE = 1.5V
VOUT
1V/DIV
VTRACK/SS
500mV/DIV
PGOOD
2V/DIV
2ms/DIV 3612 G18
VOUT = 0V TO 1.8V
IOUT = 3A
VTRACK/SS = 0V TO 0.7V
VMODE = 1.5V
VDDR = 0V
VTRACK/SS
200mV/DIV
VOUT
500mV/DIV
PGOOD
2V/DIV
2ms/DIV 3612 G19
VOUT = 0V TO 1.2V
IOUT = 3A
VTRACK/SS = 0V TO 0.4V
VMODE = 1.5V
VDDR = 3.3V
TEMPERATURE (°C)
–50
0.594
REFERENCE VOLTAGE (V)
0.596
0.600
0.602
0.604
–10 30 50 130
3612 G20
0.598
–30 10 70 90 110
0.606
INPUT VOLTAGE (V)
2.5
RDS(0N) (Ω)
0.06
0.08
0.10
4.5
3612 G21
0.04
0.02
0.05
0.07
0.09
0.03
0.01
03.0 3.5 4.0 5.0 5.5
MAIN SWITCH
SYNCHRONOUS SWITCH
Switch On-Resistance
vs Temperature
TEMPERATURE (°C)
–50
0
RDS(ON) (Ω)
0.01
0.03
0.04
0.05
70
0.09
3612 G22
0.02
10
–10 110
50
–30 90
30 130
0.06
0.07
0.08 MAIN SWITCH
SYNCHRONOUS SWITCH
Typical perForMance characTerisTics
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
LTC3612
8
3612fa
Frequency vs Input Voltage
Switch Leakage vs Temperature,
Main Switch
Switch Leakage vs Temperature,
Synchronous Switch
Frequency vs Resistor on
RT/SYNC Pin Frequency vs Temperature
Dynamic Supply Current vs Input
Voltage without AVP Mode
RESISTOR ON RT/SYNC PIN (kΩ)
0
0
FREQUENCY (kHz)
500
1500
2000
2500
800
4500
3612 G23
1000
400
200 1000 1200
600 1400
3000
3500
4000
TEMPERATURE (°C)
–50
–1.2
FREQUENCY VARIATION (%)
–1.0
–0.6
–0.4
–0.2
0.8
0.2
–10 30 50 130
3612 G24
–0.8
0.4
0.6
0
–30 10 70 90 100
INPUT VOLTAGE (V)
2.25
–2.5
FREQUENCY VARIATION (%)
–2.0
–1.0
–0.5
0
1.0
3612 G25
–1.5
0.5
3.75
3.25 5.25
2.75 4.25 4.75
TEMPERATURE (°C)
–50
SWITCH LEAKAGE (nA)
2000
2500
3000
110
3612 G26
1500
1000
0–10 30 70
–30 130
10 50 90
500
4000
3500
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
TEMPERATURE (°C)
–50
SWITCH LEAKAGE (nA)
2000
2500
3000
110
3612 G27
1500
1000
0–10 30 70
–30 130
10 50 90
500
4000
3500
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
INPUT VOLTAGE (V)
0.1
DYNAMIC SUPPLY CURRENT (mA)
1
10
100
2.25 3.25 3.75 4.25 4.75
0.01
2.75 5.25
3612 G28
FORCED CONTINUOUS MODE
PULSE-SKIPPING MODE
Burst Mode OPERATION
Typical perForMance characTerisTics
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
LTC3612
9
3612fa
VOUT Short to GND,
Forced Continuous Mode
Dynamic Supply Current vs
Temperature without AVP Mode
TEMPERATURE (°C)
0.1
DYNAMIC SUPPLY CURRENT (mA)
1
10
100
–50 30 70 110 130
0.01
–10 10 50 90–30
3612 G29
FORCED CONTINUOUS MODE
PULSE-SKIPPING MODE
Burst Mode OPERATION
VOUT
1V/DIV
IL
2A/DIV
50µs/DIV 3612 G30
VOUT = 2.5V
IOUT = 0A
VMODE = 1.5V
Start-Up from Shutdown with
Prebiased Output
(Forced Continuous Mode)
Output Voltage During Sinking
vs Input Voltage
VOUT
500mV/DIV
PGOOD
5V/DIV
IL
2A/DIV
20µs/DIV 3612 G31
PREBIASED VOUT = 2.2V
VOUT = 1.2V
IOUT = 0A
VMODE = 1.5V
INPUT VOLTAGE (V)
2.25
1.76
VOUT (V)
1.78
1.82
1.84
1.86
1.90
3612 G32
1.80
1.88
3.75
3.25 5.25
2.75 4.25 4.75
–1.5A, 2MHz, 120°C
–1.5A, 2MHz, 25°C
VOUT = 1.8V
1µH INDUCTOR
Output Voltage During Sinking
vs Input Voltage
INPUT VOLTAGE (V)
2.25
0.88
VOUT (V)
0.89
0.91
0.92
0.93
0.95
3612 G33
0.90
0.94
3.75
3.25 5.25
2.75 4.25 4.75
–1.5A, 1MHz, 120°C
–1.5A, 1MHz, 25°C
VOUT = 0.9V
1µH INDUCTOR
Typical perForMance characTerisTics
VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
LTC3612
10
3612fa
pin FuncTions
(QFN/FE)
DDR (Pin 1/Pin 8): DDR Mode Pin. Tying the DDR pin to
SVIN selects DDR mode and TRACK/SS can be used as
an external reference input. If DDR is tied to SGND, the
internal 0.6V reference will be used.
RT/SYNC (Pin 2/Pin 9): Oscillator Frequency. This pin
provides three ways of setting the constant switching
frequency:
1. Connecting a resistor from RT/SYNC to ground will set
the switching frequency based on the resistor value.
2. Driving the RT/SYNC pin with an external clock signal
will synchronize the LTC3612 to the applied frequency.
The slope compensation is automatically adapted to the
external clock frequency.
3. Tying the RT/SYNC pin to SVIN enables the internal
2.25MHz oscillator frequency.
SGND (Pin 3/Pin 10): Signal Ground. All small-signal and
compensation components should connect to this ground,
which in turn should connect to PGND at a single point.
NC (Pins 4, 7, 10/Pins 11, 13, 18): Can be connected to
ground or left open.
SW (Pins 5, 6, 11, 12/Pins 12, 14, 17, 19): Switch Node.
Connection to the inductor. This pin connects to the drains
of the internal synchronous power MOSFET switches.
PVIN (Pins 8, 9/Pins 15, 16): Power Input Supply. PVIN
connects to the source of the internal P-channel power
MOSFET. This pin is independent of SVIN and may be con-
nected to the same voltage or to a lower voltage supply.
PVIN_DRV (Pin 13/Pin 20): Internal Gate Driver Input Sup-
ply. This pin must be connected to PVIN.
SVIN (Pin 14/Pin 1): Signal Input Supply. This pin pow-
ers the internal control circuitry and is monitored by the
undervoltage lockout comparator.
RUN (Pin 15/Pin 2): Enable Pin. Forcing this pin to ground
shuts down the LTC3612. In shutdown, all functions are
disabled and the chip draws <1µA of supply current.
PGOOD (Pin 16/Pin 3): Power Good. This open-drain
output is pulled down to SGND on start-up and while the
FB voltage is outside the power good voltage window. If
the FB voltage increases and stays inside the power good
window for more than 105µs the PGOOD pin is released.
If the FB voltage leaves the power good window for more
than 105µs the PGOOD pin is pulled down.
In DDR mode (DDR = VIN), the power good window moves
in relation to the actual TRACK/SS pin voltage. During up/
down tracking the PGOOD pin is always pulled down.
In shutdown the PGOOD output will actively pull down
and may be used to discharge the output capacitors via
an external resistor.
MODE (Pin 17/Pin 4): Mode Selection. Tying the MODE
pin to SVIN or SGND enables pulse-skipping mode or Burst
Mode operation (with an internal Burst Mode clamp),
respectively. If this pin is held at slightly higher than half
of SVIN, forced continuous mode is selected. Connecting
this pin to an external voltage selects Burst Mode opera-
tion with the burst clamp set to the pin voltage. See the
Operation section for more details.
VFB (Pin 18/Pin 5): Voltage Feedback Input Pin. Senses
the feedback voltage from the external resistive divider
across the output.
ITH (Pin 19/Pin 6): Error Amplifier Compensation. The
current comparator’s threshold increases with this control
voltage. Tying this pin to SVIN enables internal compensa-
tion and AVP mode.
TRACK/SS (Pin 20/Pin 7): Track/External Soft-Start/Ex-
ternal Reference. Start-up behavior is programmable with
the TRACK/SS pin:
1. Tying this pin to SVIN selects the internal soft-start
circuit.
2. External soft-start timing can be programmed with a
capacitor to ground and a resistor to SVIN.
3. TRACK/SS can be used to force the LTC3612 to track
the start-up behavior of another supply.
The pin can also be used as external reference input. See the
Applications Information section for more information.
PGND (Pin 21/Pin 21): Power Ground. The exposed pad
connects to the source of the internal N-channel power
MOSFET. This pin should be connected close to the (–)
terminal of CIN and COUT and soldered to PCB ground for
rated thermal performance.
LTC3612
11
3612fa
FuncTional block DiagraM
–
+
–
+
–
+
–
+
–
+
–
+
MODE
+
SLEEP
MODE
BURST
COMPARATOR
ITH SENSE
COMPARATOR
ERROR
AMPLIFIER
FOLDBACK
AMPLIFIER
0.6V
0.3V
R
0.555V
TRACK/SS
0.645V
DDR
EXPOSED PAD
3612 BD
SOFT-START
BANDGAP
AND
BIAS
–
+
–
+
VFB
RUN
SGND RT/SYNC ITH
SVIN – 0.3V
PVIN PVIN_DRV
SVIN
PGOOD
LOGIC
SW
SW
SW
SW
PGND
REVERSE
COMPARATOR
IREV
OSCILLATOR
–
+
INTERNAL
COMPENSATION
CURRENT
SENSE
SLOPE
COMPENSATION
PMOS CURRENT
COMPARATOR
ITH
LIMIT
DRIVER
LTC3612
12
3612fa
Mode Selection
The MODE pin is used to select one of four different
operating modes:
operaTion
Main Control Loop
The LTC3612 is a monolithic, constant frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power switch. The peak inductor cur-
rent at which the current comparator trips is controlled by
the voltage on the ITH pin. The error amplifier adjusts the
voltage on the ITH pin by comparing the feedback signal
from a resistor divider on the VFB pin with an internal 0.6V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. Typical
voltage range for the ITH pin is from 0.1V to 1.05V with
0.45V corresponding to zero current.
When the top power switch shuts off, the synchronous
power switch (N-channel MOSFET) turns on until either
the bottom current limit is reached or the next clock cycle
begins. The bottom current limit is typically set at –4A for
forced continuous mode and 0A for Burst Mode operation
and pulse-skipping mode.
The operating frequency defaults to 2.25MHz when
RT/SYNC is connected to SVIN, or can be set by an external
resistor connected between the RT/SYNC pin and ground,
or by a clock signal applied to the RT/SYNC pin. The switch-
ing frequency can be set from 300kHz to 4MHz.
Overvoltage and undervoltage comparators pull the
PGOOD output low if the output voltage varies typically
more than ±7.5% from the set point.
PS PULSE-SKIPPING MODE ENABLE
FORCED CONTINUOUS MODE ENABLE
Burst Mode ENABLE—INTERNAL CLAMP
3612 OP01
Burst Mode ENABLE—EXTERNAL CLAMP,
CONTROLLED BY VOLTAGE APPLIED AT
MODE PIN
SVIN
SVIN – 0.3V
SVIN • 0.58
1.1V
0.8V
0.45V
0.3V
SGND
BM
BM
EXT
FC
Mode Selection Voltage
Burst Mode Operation—Internal Clamp
Connecting the MODE pin to SGND enables Burst Mode
operation with an internal clamp. In Burst Mode operation
the internal power switches operate intermittently at light
loads. This increases efficiency by minimizing switching
losses. During the intervals when the switches are idle,
the LTC3612 enters sleep state where many of the internal
circuits are disabled to save power. During Burst Mode
operation, the minimum peak inductor current is internally
clamped and the voltage on the ITH pin is monitored by
the burst comparator to determine when sleep mode is
enabled and disabled. When the average inductor current
is greater than the load current, the voltage on the ITH pin
drops. As the ITH voltage falls below the internal clamp,
the burst comparator trips and enables sleep mode. Dur-
ing sleep mode, the power MOSFETs are held off and the
load current is solely supplied by the output capacitor.
When the output voltage drops, the top power switch is
turned back on and the internal circuits are re-enabled.
This process repeats at a rate that is dependent on the
load current.
LTC3612
13
3612fa
operaTion
Burst Mode Operation—External Clamp
Connecting the MODE pin to a voltage in the range of 0.45V
to 0.8V enables Burst Mode operation with external clamp.
During this mode of operation the minimum voltage on the
ITH pin is externally set by the voltage on the MODE pin.
It is recommended to use Burst Mode operation with an
internal clamp for temperatures above 85°C ambient.
Pulse-Skipping Mode Operation
Pulse-skipping mode is similar to Burst Mode operation,
but the LTC3612 does not disable power to the internal
circuitry during sleep mode. This improves output voltage
ripple but uses more quiescent current, compromising
light load efficiency.
Tying the MODE pin to SVIN enables pulse-skipping mode.
As the load current decreases, the peak inductor current
will be determined by the voltage on the ITH pin until the
ITH voltage drops below the voltage level corresponding to
0A. At this point, the peak inductor current is determined
by the minimum on-time of the current comparator. If the
load demand is less than the average of the minimum on-
time inductor current, switching cycles will be skipped to
keep the output voltage in regulation.
Forced Continuous Mode
In forced continuous mode the inductor current is con-
stantly cycled which creates a minimum output voltage
ripple at all output current levels.
Connecting the MODE pin to a voltage in the range of
1.1V to SVIN • 0.58 will enable forced continuous mode
operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode or pulse-skipping operation, but
may be desirable in some applications where it is necessary
to keep switching harmonics out of the signal band.
Forced continuous mode must be used if the output is
required to sink current.
Dropout Operation
As the input supply voltage approaches the output voltage,
the duty cycle increases toward the maximum on-time.
Further reduction of the supply voltage forces the main
switch to remain on for more than one cycle, eventually
reaching 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
Low Supply Operation
The LTC3612 is designed to operate down to an input
supply voltage of 2.25V. An important consideration at low
input supply voltages is that the RDS(ON) of the P-channel
and N-channel power switches increases. The user should
calculate the power dissipation when the LTC3612 is used
at 100% duty cycle with low input voltages to ensure that
thermal limits are not exceeded. See the Typical Perfor-
mance Characteristics graphs.
Short-Circuit Protection
The peak inductor current at which the current comparator
shuts off the top power switch is controlled by the voltage
on the ITH pin.
If the output current increases, the error amplifier raises the
ITH pin voltage until the average inductor current matches
the new load current. In normal operation the LTC3612
clamps the maximum ITH pin voltage at approximately
1.05V which corresponds typically to 6A peak inductor
current.
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. The
LTC3612 uses two techniques to prevent current runaway
from occurring.
LTC3612
14
3612fa
applicaTions inForMaTion
If the output voltage drops below 50% of its nominal value,
the clamp voltage at ITH pin is lowered causing the maxi-
mum peak inductor current to decrease gradually with the
output voltage. When the output voltage reaches 0V the
clamp voltage at the ITH pin drops to 40% of the clamp
voltage during normal operation. The short-circuit peak
inductor current is determined by the minimum on-time
of the LTC3612, the input voltage and the inductor value.
This foldback behavior helps in limiting the peak inductor
current when the output is shorted to ground. It is disabled
during internal or external soft-start and tracking up/down
operation (see the Applications Information section).
A secondary limit is also imposed on the valley inductor
current. If the inductor current measured through the
bottom MOSFET increases beyond 6A typical, the top
power MOSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
operaTion
The basic LTC3612 application circuit is shown in Figure 1.
Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3612 is determined
by an external resistor that is connected between the
RT/SYNC pin and ground. The value of the resistor sets
RUN
TRACK/SS
RT/SYNC
PGOOD
ITH
SGND
PGND
VIN
2.25V TO 5.5V
PVIN_DRV
DDR
SVIN
LTC3612 SW
PVIN
CIN1
22µF
CC
470pF
CSS
22nF
L1
470nH
R1
392k
R2
196k
3612 F01
CIN2
22µF
MODE VFB
COUT1
47µF
COUT2
22µF
VOUT
1.8V
3A
RC
15k
RT
130k
RSS
2M
CC1
10pF
(OPT)
Figure 1. 1.8V, 3A Step-Down Regulator
the ramp current that is used to charge and discharge an
internal timing capacitor within the oscillator and can be
calculated by using the following equation:
RT=3.82 • 1011Hz
fOSC Hz
( )
Ω– 16kΩ
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3612 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 60ns; therefore, the minimum duty cycle is
equal to 100 • 60ns • fOSC(Hz)%.
Tying the RT/SYNC pin to SVIN sets the default internal
operating frequency to 2.25MHz ±20%.
LTC3612
15
3612fa
applicaTions inForMaTion
Frequency Synchronization
The LTC3612’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the RT/SYNC pin. During synchronization, the top
switch turn-on is locked to the falling edge of the external
frequency source. The synchronization frequency range
is 300kHz to 4MHz. During synchronization all operation
modes can be selected.
It is recommended that the regulator is powered down
(RUN pin to ground) before removing the clock signal
on the RT/SYNC pin in order to reduce inductor current
ripple.
AC coupling should be used if the external clock genera-
tor cannot provide a continuous clock signal throughout
start-up, operation and shutdown of the LTC3612. The
size of capacitor CSYNC depends on parasitic capacitance
on the RT/SYNC pin and is typically in the range of 10pF
to 22pF
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆IL increases with higher VIN and decreases
with higher inductance:
∆IL=VOUT
fSW •L
• 1– VOUT
VIN
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆IL = 0.3 • IOUT(MAX).
The largest ripple current occurs at the highest VIN. To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:
L=VOUT
fSW •∆IL(MAX)
• 1– VOUT
VIN
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low cur-
rent operation. In Burst Mode operation, lower inductance
values will cause the burst frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for
fixed inductor value, but it is very dependent on the induc-
tance selected. As the inductance increases, core losses de-
crease. Unfortunately, increased inductance requires more
turns of wire and therefore, copper losses will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” meaning that inductance
collapses abruptly when the peak design current is ex-
ceeded. This results in an abrupt increase in inductor
LTC3612
SVIN
VIN
RT/SYNC
LTC3612
SVIN
VIN
0.4V RT/SYNC
RT
RT
SGND
LTC3612
SVIN
fOSC
2.25MHz
fOSC
1/TP
fOSC t1/RT
VIN
RT/SYNC
SGND
TP
1.2V
0.3V
LTC3612
SVIN fOSC
1/TP
VIN
CSYNC
RT/SYNC
SGND
3612 F02
Figure 2. Setting the Switching Frequency
LTC3612
16
3612fa
applicaTions inForMaTion
ripple current and consequently output voltage ripple. Do
not allow a ferrite core to saturate!
Different core materials and shapes will change the size/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and do not radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 shows
some typical surface mount inductors that work well in
LTC3612 applications.
Input Capacitor (CIN) Selection
In continuous mode, the source current of the top P-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current must be used at VIN.
The maximum RMS capacitor current is given by:
IRMS =IOUT(MAX) •VOUT
VIN
•VIN
VOUT
– 1
This formula has a maximum at VIN = 2VOUT
, where IRMS =
IOUT/2. This simple worst-case condition is commonly used
for design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design.
Output Capacitor (COUT
) Selection
The selection of COUT is typically driven by the required
ESR to minimize voltage ripple and load step transients
(low ESR ceramic capacitors are discussed in the next
section). Typically, once the ESR requirement is satisfied,
the capacitance is adequate for filtering. The output ripple
∆VOUT is determined by:
∆VOUT ≤ ∆IL• ESR +1
8 • fSW • COUT
Table 1. Representative Surface Mount Inductors
INDUCTANCE
(µH)
DCR
(mΩ)
MAX
CURRENT (A)
DIMENSIONS
(mm)
HEIGHT
(mm)
Vishay IHLP-2525AH-01 Series
0.33 7 12 6.7 × 7 1.8
0.47 9 11 6.7 × 7 1.8
0.68 13 9 6.7 × 7 1.8
0.82 15 8 6.7 × 7 1.8
1.0 18 7 6.7 × 7 1.8
Vishay IHLP-1616BZ-01 Series
0.22 8 24 4.3 × 4.7 2
0.47 18 11.5 4.3 × 4.7 2
1.00 37 8.5 4.3 × 4.7 2
Sumida CDMC6D28 Series
0.3 3.2 15.4 6.7 × 7.25 3
0.47 4.2 13.6 6.7 × 7.25 3
0.68 5.4 11.3 6.7 × 7.25 3
1 8.8 8.8 6.7 × 7.25 3
NEC/Tokin MPLC0730L Series
0.47 4.5 16.6 6.9 × 7.7 3.0
0.75 7.5 12.2 6.9 × 7.7 3.0
1.0 9.0 10.6 6.9 × 7.7 3.0
Cooper HCP0703 Series
0.22 2.8 23 7 × 7.3 3.0
0.47 4.2 17 7 × 7.3 3.0
0.68 5.5 15 7 × 7.3 3.0
0.82 8.0 13 7 × 7.3 3.0
1.0 10.0 11 7 × 7.3 3.0
1.5 9.6 61 6.9 × 7.3 3.2
Würth Elektronik WE-HC744312 Series
0.25 2.5 18 7 × 7.7 3.8
0.47 3.4 16 7 × 7.7 3.8
0.72 7.5 12 7 × 7.7 3.8
1.0 9.5 11 7 × 7.7 3.8
1.5 10.5 9 7 × 7.7 3.8
Coilcraft DO1813H Series
0.33 4 10 8.9 × 6.1 5
0.56 10 7.7 8.9 × 6.1 5
Coilcraft v Series
0.27 0.1 14 7.5 × 6.7 3
0.35 0.1 11 7.5 × 6.7 3
0.4 0.1 8 7.5 × 6.7 3
LTC3612
17
3612fa
applicaTions inForMaTion
where fOSC = operating frequency, COUT = output capaci-
tance and ∆IL = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆IL
increases with input voltage.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
Tantalum capacitors have the highest capacitance density,
but can have higher ESR and must be surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can often
be used in extremely cost-sensitive applications provided
that consideration is given to ripple current ratings and
long term reliability.
Ceramic Input and Output Capacitors
Ceramic capacitors have the lowest ESR and can be cost
effective, but also have the lowest capacitance density,
high voltage and temperature coefficients, and exhibit
audible piezoelectric effects. In addition, the high-Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
They are attractive for switching regulator use because
of their very low ESR, but great care must be taken when
using only ceramic input and output capacitors.
Ceramic capacitors are prone to temperature effects
which require the designer to check loop stability over
the operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used.
When a ceramic capacitor is used at the input and the power
is being supplied through long wires, such as from a wall
adapter, a load step at the output can induce ringing at the
VIN pin. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, the ringing at the
input can be large enough to damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor
must instantaneously supply the current to support the
load until the feedback loop raises the switch current
enough to support the load. The time required for the
feedback loop to respond is dependent on the compensa-
tion components and the output capacitor size. Typically,
3 to 4 cycles are required to respond to a load step, but
only in the first cycle does the output drop linearly. The
output droop, VDROOP
, is usually about 2 to 4 times the
linear drop of the first cycle; however, this behavior can
vary depending on the compensation component values.
Thus, a good place to start is with the output capacitor
size of approximately:
COUT ≈3.5 • ∆IOUT
fSW • VDROOP
This is only an approximation; more capacitance may
be needed depending on the duty cycle and load step
requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
VOUT =0.6 • 1+R1
R2
V
The resistive divider allows pin VFB to sense a fraction of
the output voltage, as shown in Figure 1.
Burst Clamp Programming
If the voltage on the MODE pin is less than 0.8V, Burst
Mode operation is enabled.
If the voltage on the MODE pin is less than 0.3V, the internal
default burst clamp level is selected. The minimum voltage
on the ITH pin is typically 525mV (internal clamp).
If the voltage is between 0.45V and 0.8V, the voltage on
the MODE pin (VBURST) is equal to the minimum voltage
on the ITH pin (external clamp) and determines the burst
clamp level IBURST
(typically from 0A to 3.5A).
LTC3612
18
3612fa
When the ITH voltage falls below the internal (or external)
clamp voltage, the sleep state is enabled.
As the output load current drops, the peak inductor current
decreases to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than IBURST
, the burst clamp will force the peak
inductor current to remain equal to IBURST regardless of
further reductions in the load current.
Since the average inductor current is greater than the output
load current, the voltage on the ITH pin will decrease. When
the ITH voltage drops, sleep mode is enabled in which
both power switches are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power switches resume opera-
tion when the output voltage drops out of regulation. The
value for IBURST is determined by the desired amount of
output voltage ripple. As the value of IBURST increases, the
sleep period between pulses and the output voltage ripple
increase. Note that for very high VBURST voltage settings,
the power good comparator may trip, since the output
ripple may get bigger than the power good window.
Pulse-skipping mode, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting MODE to SVIN. This sets IBURST to 0A. In
this condition, the peak inductor current is limited by the
minimum on-time of the current comparator. The lowest
output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, VOUT shifts by an amount equal
to ∆ILOAD(ESR), where ESR is the effective series resistance
of COUT
. ∆ILOAD also begins to charge or discharge COUT
,
generating the feedback error signal that forces the regula-
tor to adapt to the current change and return VOUT to its
steady-state value. During this recovery time VOUT can
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. The availability of the
ITH pin allows the transient response to be optimized over
a wide range of output capacitance.
The ITH external components (RC and CC) shown in Fig-
ure 1 provide adequate compensation as a starting point
for most applications. The values can be modified slightly
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. The gain of the loop will be in-
creased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system. The external capaci-
tor, CC1, (Figure 1) is not needed for loop stability, but it
helps filter out any high frequency noise that may couple
onto that node. The general purpose buck regulator ap-
plication in the Typical Applications section uses a faster
compensation to improve load step response.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT
, causing a rapid drop in VOUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
AVP Mode
Fast load transient response, limited board space and low
cost are typical requirements of microprocessor power
supplies. A microprocessor has typical full load step with
very fast slew rate. The voltage at the microprocessor must
be held to about ±0.1V of nominal in spite of these load
current steps. Since the control loop cannot respond this
fast, the output capacitors must supply the load current
until the control loop can respond.
Normally, several capacitors in parallel are required to
meet microprocessor transient requirements. Capacitor
applicaTions inForMaTion
LTC3612
19
3612fa
ESR and ESL primarily determine the amount of droop or
overshoot in the output voltage.
Consider the LTC3612 without AVP with a bank of tantalum
output capacitors. If a load step with very fast slew rate
occurs, the voltage excursion will be seen in both direc-
tions, for full load to minimum load transient and for the
minimum load to full load transient.
If the ITH pin is tied to SVIN, the active voltage positioning
(AVP) mode and internal compensation are selected.
AVP mode intentionally compromises load regulation by
reducing the gain of the feedback circuit, resulting in an
output voltage that varies with load current. When the load
current suddenly increases, the output voltage starts from
a level slightly higher than nominal so the output voltage
can droop more and stay within the specified voltage
range. When the load current suddenly decreases the
output voltage starts at a level lower than nominal so the
applicaTions inForMaTion
Figure 4. Load Step Transient Forced Continuous Mode
with AVP Mode
output voltage can have more overshoot and stay within
the specified voltage range (see Figures 3 and 4).
The benefit is a lower peak-to-peak output voltage deviation
for a given load step without having to increase the output
filter capacitance. Alternatively, the output voltage filter ca-
pacitance can be reduced while maintaining the same peak
to peak transient response. Due to the reduced loop gain
in AVP mode, no external compensation is required.
DDR Mode
The LTC3612 can both source and sink current if the MODE
pin is configured to forced continuous mode.
Current sinking is typically limited to 1.5A, for 1MHz
frequency and a 1µH inductor, but can be lower at higher
frequencies and low output voltages. If higher ripple current
can be tolerated, smaller inductor values can increase the
sink current limit. See the Typical Performance Charac-
teristics curves for more information.
In addition, tying the DDR pin to SVIN, lower external
reference voltage and tracking output voltage between
channels are possible. See the Output Voltage Tracking
and External Reference Input sections.
Soft-Start
The RUN pin provides a means to shut down the LTC3612.
Tying the RUN pin to SGND places the LTC3612 in a low
quiescent current shutdown state (IQ < 1µA).
The LTC3612 is enabled by pulling the RUN pin high.
However, the applied voltage must not exceed SVIN. In
some applications, the RUN signal is generated within
another power domain and is driven high while the SVIN
and PVIN is still 0V. In this case, it’s required to limit the
current into the RUN pin by either adding a 1MΩ resistor
or a 100kΩ resistor, plus a Schottky diode, to SVIN. After
pulling the RUN pin high, the chip enters a soft start-up
state. This type of soft start-up behavior is set by the
TRACK/SS pin:
1. Tying TRACK/SS to SVIN selects the internal soft-start
circuit. This circuit ramps the output voltage to the final
value within 1ms.
2. If a longer soft-start period is desired, it can be set ex-
ternally with a resistor and capacitor on the TRACK/SS
Figure 3. Load Step Transient Forced Continuous Mode
(AVP Inactive)
VOUT
200mV/DIV
IL
1A/DIV
50µs/DIV 3612 F03
VIN = 3.3V
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
COMPENSATION FIGURE 1
VOUT
100mV/DIV
IL
1A/DIV
50µs/DIV 3612 F04
VIN = 3.3V
VOUT = 1.8V
ILOAD = 100mA TO 3A
VMODE = 1.5V
VITH = 3.3V
OUTPUT CAPACITOR VALUE FIGURE 1
LTC3612
20
3612fa
applicaTions inForMaTion
pin, as shown in Figure 1. The TRACK/SS pin reduces
the value of the internal reference at VFB until TRACK/SS
is pulled above 0.6V. The external soft-start duration
can be calculated by using the following formula:
tSS =RSS • CSS • ln SVIN
SVIN – 0.6V
3. The TRACK/SS pin can be used to track the output
voltage of another supply.
Each time the RUN pin is tied high and the LTC3612 is
turned on, the TRACK/SS pin is internally pulled down
for ten microseconds in order to discharge the external
capacitor. This discharging time is typically adequate
for capacitors up to about 33nF. If a larger capacitor is
required, connect the external soft-start resistor to the
RUN pin.
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be
in pulse-skipping mode. In addition, the PGOOD pin
is kept low and foldback of the switching frequency is
disabled.
Output Voltage Tracking Input
If the DDR pin is not tied to SVIN, once VTRACK/SS exceeds
0.6V, the run state is entered and the MODE selection, power
good and current foldback circuits are enabled.
In the run state, the TRACK/SS pin can be used for track-
ing down/up the output voltage of another supply. If the
VTRACK/SS drops below 0.6V, the LTC3612 enters the down
tracking state and VOUT is referenced to the TRACK/SS volt-
age. If the TRACK/SS pin drops below 0.2V, the switching
frequency is reduced to ensure that the minimum duty
cycle limit does not prevent the output from following
the TRACK/SS pin. The run state will resume if VTRACK/SS
again exceeds 0.6V and VOUT is referenced to the internal
precision reference (see Figure 7).
Through the TRACK/SS pin, the output voltage can be set
up for either coincident or ratiometric tracking, as shown
in Figure 5.
Figure 5. Two Different Modes of Output Voltage Tracking
TIME
(5b) Ratiometric Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
TIME 3612 F05
(5a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
To implement the coincident tracking behavior in Fig-
ure 5a, connect an extra resistive divider to the output
of the master channel and connect its midpoint to the
TRACK/SS pin for the slave channel. The ratio of this
divider should be selected to be the same as that of the
slave channel’s feedback divider (Figure 6a).
In this track-
ing mode, the master channel’s output must be set higher
than slave channel’s output. To implement the ratiometric
tracking behavior in Figure 5b, different resistor divider
values must be used as specified in Figure 6b.
For coincident start-up, the voltage value at the TRACK/SS
pin for the slave channel needs to reach the final reference
value after the internal soft-start time (around 1ms). The
master start-up time needs to be adjusted with an external
capacitor and resistor to ensure this.
LTC3612
21
3612fa
applicaTions inForMaTion
External Reference Input (DDR Mode)
If the DDR pin is tied to SVIN (DDR mode), the run state
is entered when VTRACK/SS exceeds 0.3V and tracking
down behavior is possible if the VTRACK/SS voltage is
below 0.6V.
This allows TRACK/SS to be used as an external reference
between 0.3V and 0.6V if desired. During the run state in
DDR mode, the power good window moves in relation
to the actual TRACK/SS pin voltage if the voltage value
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
0.6V, either the tracking circuit or the internal reference
can be used.
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see
Figure 8).
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
Figure 6a. Set-Up for Coincident Tracking
Figure 6b. Set-Up for Ratiometric Tracking
VFB2
R4
R2
R4
R2
R3
R2
R4 ≤ R3
VOUT2
VOUT1
LTC3612
TRACK/SS2
VFB1 VIN
LTC3612
LTC3612 CHANNEL 2
SLAVE
LTC3612 CHANNEL 1
MASTER
TRACK/SS1
3612 F06a
VFB2
R1
R2
R5
R6
R3 R1/R2 < R5/R6
R4
VOUT2
VOUT1
LTC3612
TRACK/SS2
VFB1
VIN
3612 F06b
LTC3612
LTC3612 CHANNEL 2
SLAVE
LTC3612 CHANNEL 1
MASTER
TRACK/SS1
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to VIN; thus, their effects
will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW
, and external inductor, RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
LTC3612
22
3612fa
applicaTions inForMaTion
Figure 7. DDR Pin Not Tied to SVIN
Figure 8. DDR Pin Tied to SVIN. Example DDR Application
SOFT-START
STATE
tSS > 1ms
SHUTDOWN
STATE
0.6V
0.6V
0.2V
0V
0V
0V
0V
VIN
VIN
VFB PIN
VOLTAGE
TRACK/SS
PIN VOLTAGE
RUN PIN
VOLTAGE
SVIN PIN
VOLTAGE
RUN STATE RUN STATE
TIME
3612 F07
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
UP
TRACKING
STATE
SOFT-START
STATE
tSS > 1ms
SHUTDOWN
STATE
0.3V
0.45V
0.45V
0.3V
0.2V
0V
0V
0V
0V
VIN
VIN
VFB PIN
VOLTAGE
EXTERNAL
VOLTAGE
REFERENCE 0.45V
TRACK/SS
PIN VOLTAGE
RUN PIN
VOLTAGE
SVIN PIN
VOLTAGE
RUN STATE RUN STATE
TIME
3612 F08
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
UP
TRACKING
STATE
LTC3612
23
3612fa
Thermal Considerations
In most applications, the LTC3612 does not dissipate much
heat due to its high efficiency.
However, in applications where the LTC3612 is running at
high ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3612 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
TRISE = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature. The junction temperature, TJ,
is given by:
TJ = TA + TRISE
where TA is the ambient temperature.
As an example, consider the case when the LTC3612 is in
dropout at an input voltage of 3.3V with a load current of
3A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P-channel switch is 0.075Ω.
Therefore, power dissipated by the part is:
PD = (IOUT)2 • RDS(ON) = 675mW
For the QFN package, the θJA is 43°C/W.
Therefore, the junction temperature of the regulator operat-
ing at 70°C ambient temperature is approximately:
TJ = 0.675W • 43°C/W + 70°C = 99°C
We can safely assume that the actual junction temperature
will not exceed the absolute maximum junction tempera-
ture of 125°C.
Note that for very low input voltage, the junction tempera-
ture will be higher due to increased switch resistance,
RDS(ON). It is not recommended to use full load current
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3612 the
Exposed Pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
Design Example
As a design example, consider using the LTC3612 in an
application with the following specifications:
VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 3A, IOUT(MIN)
= 100mA, f = 2.6MHz.
Efficiency is important at both high and low load current,
so Burst Mode operation will be utilized.
First, calculate the timing resistor:
RT=3.82 • 1011Hz
2.6MHz Ω– 16kΩ= 130kΩ
Next, calculate the inductor value for about 30% ripple
current at maximum VIN:
L=1.8V
2.6MHz • 1A
• 1– 1.8V
5.5V
=0.466µH
Using a standard value of 0.47µH inductor results in a
maximum ripple current of:
∆IL=1.8V
2.6MHz • 0.47µH
• 1– 1.8V
5.5V
=0.99A
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
68µF (or 47µF plus 22µF) ceramic capacitor is used with
a X5R or X7R dielectric.
applicaTions inForMaTion
LTC3612
24
3612fa
CIN should be sized for a maximum current rating of:
IRMS =3A • 1.8V
3.6V •3.6V
1.8V – 1
=1.5ARMS
Decoupling the PVIN with two 22µF capacitors, is adequate
for most applications.
If we set R2 = 196k, the value of R1 can now be determined
by solving the following equation.
R1 = 196k • 1.8V
0.6V −1
A value of 392k will be selected for R1.
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
TRACK/SS. If we set minimum tSS = 5ms and a resistor
of 2M, the following equation can be solved with the
maximum SVIN = 5.5V :
CSS =5ms
2M •In 5.5V
5.5V – 0.6V
=21.6nF
The standard value of 22nF guarantees the minimum
soft-start up time of 5ms.
Figure 1 shows the schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3612:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3612.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
applicaTions inForMaTion
LTC3612
25
3612fa
Typical applicaTions
General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz
RUN
TRACK/SS
RT/SYNC
PGOOD
ITH
PGOOD SGND
PGND
VIN
2.25V TO 5.5V
PVIN_DRV
DDR
SVIN
LTC3612
SW
PVIN
CF
1µF
RF
24Ω
L1
470nH
R1
392k
C3
22pF
R2
196k
3612 TA02a
MODE VFB
CO1
47µF
CO2
22µF
CC1
10pF
C1
22µF
C2
22µF
CC
220pF
CSS
10nF VOUT
1.8V
3A
R4
100k
R5B
1M
L1: VISHAY IHLP-2020BZ 0.47µH
R5A
1M
RC
43k
RSS
4.7M
Efficiency vs Output Current Load Step Response in Forced Continuous Mode
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
1 100 1000 10000
3612 TA02b
0
10
VIN = 2.5V
VIN = 3.3V
VIN = 4V
VIN = 5.5V
VOUT
100mV/DIV
IOUT
1A/DIV
20µs/DIV 3612 TA02c
VIN = 3.3V
VOUT = 1.8V
IOUT = 100mA TO 3A
VMODE = 1.5V
LTC3612
26
3612fa
Typical applicaTions
Master and Slave for Coincident Tracking Outputs Using a 1MHz External Clock
RUN
TRACK/SS
RT/SYNC
PGOOD
ITH
PGOOD SGND
PGND
VIN
2.25V TO 5.5V
PVIN_DRV
DDR
SVIN
LTC3612
SW
PVIN
CF1
1µF
RF1
24Ω
L1
1µH
CHANNEL 1
MASTER
CHANNEL 2
SLAVE
R1
715k
C3
22pF
R2
357k
R3
464k
R4
464k
3612 TA03a
MODE VFB
CO11
47µF
CO12
22µF
CC2
10pF
C1
22µF
C2
22µF
CC1
470pF
VOUT1
1.8V
3A
10nF
4.7M
4.7M
4.7M
R5
100k
1MHz
CLOCK
RC1
15k
RUN
TRACK/SS
RT/SYNC
PGOOD
ITH
PGOOD SGND
PGND
PVIN_DRV
DDR
SVIN
LTC3612
SW
PVIN
CF2
1µF
RF2
24Ω
L2
1µH
R5
301k
C7
22pF
R6
301k
MODE VFB
CO21
47µF
CO22
22µF
CC4
10pF
C6
22µF
C5
22µF
CC3
470pF
VOUT2
1.2V
3A
R7
100k
RC2
15k
Coincident Start-Up Coincident Tracking Up/Down
500mV/DIV
2ms/DIV 3612 TA03b
VOUT1
VOUT2
500mV/DIV
200ms/DIV 3612 TA03c
VOUT1
VOUT2
LTC3612
27
3612fa
package DescripTion
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
3.00 ± 0.10 1.50 REF
4.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ± 0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
s 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDC20) QFN 1106 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
1.50 REF
2.10 ± 0.05
3.50 ± 0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ± 0.10
2.65 ± 0.10
1.65 ± 0.05
2.65 ± 0.05
0.50 BSC
LTC3612
28
3612fa
package DescripTion
FE Package
20-Lead Plastic eTSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev G)
Exposed Pad Variation CB
FE20 (CB) eTSSOP REV G 0510
0.09 – 0.20
(.0035 – .0079)
0o – 8o
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 p0.05
0.65 BSC
4.50 p0.10
6.60 p0.10
1.05 p0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3612
29
3612fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 08/10 Updated Temperature Range in Order Information 2
Edited Electrical Characteristics table and updated Note 2 3, 4
Updated text in graphs G19, G31 7, 9
Updated Pin 16/Pin 3 and Pin 21/Pin 21 text 10
Updated Functional Block Diagram 11
Updated Burst Mode Operation—External Clamp section 13
Updated Internal and External Compensation section 18
Updated Soft-Start section 19
Updated Timing Resistor equation in Design Example section 23
Updated TA02a and TA02c in Typical Applications 25
Updated Related Parts 30
LTC3612
30
3612fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2009
LT 0810 REV A • PRINTED IN USA
relaTeD parTs
Typical applicaTion
DDR Termination with Ratiometric Tracking of VDD, 1MHz
Ratiometric Start-Up
PART NUMBER DESCRIPTION COMMENTS
LTC3614 5.5V, 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter with Tracking and DDR
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA,
ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3616 5.5V, 6A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter with Tracking and DDR
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA,
ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3601 15V, 1.5A (IOUT), Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA,
ISD < 1µA, MSOP-16E and 3mm × 3mm QFN-16 Packages
LTC3603 15V, 2.5A, Synchronous Step-Down DC/DC Converter 92% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA,
4mm × 4mm QFN-16 Package
LTC3605 15V, 5A (IOUT), Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,
4mm × 4mm QFN-24 Package
LTC3412A 5.5V, 3A (IOUT), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
ISD < 1µA, TSSOP-16E and 4mm × 4mm QFN-16 Packages
LTC3413 5.5V, 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous
Regulator for DDR/QDR Memory Termination
90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF /2, IQ = 280µA,
ISD < 1µA, TSSOP-16E Package
RUN
TRACK/SS
RT/SYNC
PGOODPGOOD
SGND
PGND
VIN
3.3V
VDD
1.8V
PVIN_DRV
DDR
SVIN
LTC3612
SW
PVIN
L1
1µH
R1
200k
C3
22pF
R2
200k
3612 TA04a
MODE VFB
C4
100µF
C5
47µF
CC1
10pF
C2
22µF
C1
22µF
CC
2.2nF
VTT
0.9V
±1.5A
R3
100k R8
365k
R5
1M L1: COILCRAFT DO3316T
R4
1M
RC
6k
R7
187k
R6
562k
ITH
500mV/DIV
500µs/DIV 3612 TA04b
VDD
VTT
