FemtoClockTM Crystal-to-LVDS Clock Generator ICS844011 PRELIMINARY DATA SHEET General Description Features The ICS844011 is a Fibre Channel Clock Generator and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS844011 uses an 18pF parallel resonant crystal over the range of 20.4MHz - 28.3MHz. For Fibre Channel applications, a 26.5625MHz crystal is used. The ICS844011 has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS844011 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * * One differential LVDS clock output pair * * * Output frequency range: 81.66MHz - 113.33MHz * RMS phase jitter @ 156.25MHz, (1.875MHz - 20MHz): 0.45ps (typical) * * Full 3.3V or 2.5V operating supply * 0C to 70C ambient operating temperature ICS Crystal interface designed for 18pF parallel resonant crystals (20.4MHz - 28.3MHz) VCO range: 490MHz - 680MHz RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.75ps (typical) Available in both standard (RoHs 5) and lead-free (RoHS 6) packages Common Configuration Table - Fibre Channel Inputs Crystal Frequency (MHz) M N Multiplication Value M/N Output Frequency (MHz) 26.5625 24 6 4 106.25 25 24 6 4 100 Pin Assignment Block Diagram OE Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO 490MHz - 680MHz Q nQ N = /6 (fixed) M = /24 (fixed) VDDA GND XTAL_OUT XTAL_IN 1 8 2 3 4 7 6 5 VDD Q nQ OE ICS844011 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. ICS844011AG REV. B AUGUST 28, 2009 1 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1 VDDA Power Analog power supply. 2 GND Power Power supply ground. 3, 4 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 OE Input 6, 7 nQ, Q Output Differential clock output. LVDS interface levels. 8 VDD Power Core supply pin. Pullup Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ output is in a high impedance state. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k ICS844011AG REV. B AUGUST 28, 2009 Test Conditions 2 Minimum Typical Maximum Units (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = 3.3V5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.07 3.3 VDD V IDD Power Supply Current 90 mA IDDA Analog Supply Current 7 mA Table 3B. Power Supply DC Characteristics, VDD = 2.5V5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD - 0.07 2.5 VDD V IDD Power Supply Current 85 mA IDDA Analog Supply Current 7 mA Table 3C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V5% or 2.5V5%, TA = 0C to 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V or 2.625V IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V ICS844011AG REV. B AUGUST 28, 2009 Test Conditions Minimum VDD = 3.3V Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 A 3 -150 Typical A (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Table 3D. LVDS DC Characteristics, VDD = 3.3V5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.25 V VOS VOS Magnitude Change 50 mV Table 3E. LVDS DC Characteristics, VDD = 2.5V5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 V VOS VOS Magnitude Change 50 mV Table 4. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 28.3 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Fundamental Frequency ICS844011AG REV. B AUGUST 28, 2009 Typical 20.4 4 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR AC Characteristics Table 5A. AC Characteristics, VDD = 3.3V5%, TA = 0C to 70C Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 81.66 Maximum Units 113.33 MHz 106.25MHz, Integration Range: 637kHz - 10MHz ps 100MHz, Integration Range: 637kHz - 10MHz 0.75 ps 20% to 80% 275 ps 50 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the phase noise plot. Table 5B. AC Characteristics, VDD = 2.5V5%, TA = 0C to 70C Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 81.66 Maximum Units 113.33 MHz 106.25MHz, Integration Range: 637kHz - 10MHz 0.45 ps 100MHz, Integration Range: 637kHz - 10MHz 0.93 ps 20% to 80% 295 ps 50 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the phase noise plot. ICS844011AG REV. B AUGUST 28, 2009 5 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information SCOPE SCOPE 3.3V5% POWER SUPPLY + Float GND - Qx VDD 2.5V5% POWER SUPPLY + Float GND - VDDA LVDS Qx VDD VDDA LVDS nQx nQx 2.5V LVDS Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit Phase Noise Plot Noise Power nQ Q t PW t odc = PERIOD t PW Phase Noise Mask x 100% t PERIOD f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Duty Cycle/Pulse Width/Period RMS Phase Jitter VDD VDD out 100 DC Input LVDS VOD/ VOD out out LVDS DC Input out VOS/ VOS Offset Voltage Setup Differential Output Voltage Setup nQ 80% 80% VOD Q 20% 20% tR tF Output Rise/Fall Time ICS844011AG REV. B AUGUST 28, 2009 6 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844011 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDAshould be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V or 2.5V VDD .01F 10 .01F 10F VDDA Figure 1. Power Supply Filtering Crystal Input Interface The ICS844011 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 2. Crystal Input Interface ICS844011AG REV. B AUGUST 28, 2009 7 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at VCC the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC R1 Ro Rs 0.1f 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface 3.3V, 2.5V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V or 2.5V VDD 50 LVDS Driver + R1 100 - 50 100 Differential Transmission Line Figure 4. Tyical LVDS Driver Termination ICS844011AG REV. B AUGUST 28, 2009 8 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS844011. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844011 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (90mA + 7mA) = 336.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.336W * 129.5C/W = 113.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS844011AG REV. B AUGUST 28, 2009 0 1 2.5 129.5C/W 125.5C/W 123.5C/W 9 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Reliability Information Table 7. JA vs. Air Flow Table for a 8-lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5C/W 125.5C/W 123.5C/W Transistor Count The transistor count for ICS844011 is: 2533 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS844011AG REV. B AUGUST 28, 2009 10 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Table 9. Ordering Information Part/Order Number 844011AG 844011AG 844011AGLF 844011AGLFT Marking 4011A 4011A 011AL 011AL Package 8-lead TSSOP 8-lead TSSOP Lead-Free, 8-lead TSSOP Lead-Free, 8-lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS844011AG REV. B AUGUST 28, 2009 11 (c)2009 Integrated Device Technology, Inc. ICS844011 Preliminary Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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