PRELIMINARY DATA SHEET
ICS844011AG REV. B AUGUST 28, 2009 1 ©2009 Integrated Device Technology, Inc.
FemtoClock™ Crystal-to-LVDS
Clock Generator
ICS844011
General Description
The ICS844011 is a Fibre Channel Clock Generator
and a member of the HiPerClocksTM family of high
performance devices from IDT. The ICS844011 uses
an 18pF parallel resonant crystal over the range of
20.4MHz - 28.3MHz. For Fibre Channel applications, a
26.5625MHz crystal is used. The ICS844011 has excellent <1ps
phase jitter performance, over the 637kHz - 10MHz integration
range. The ICS844011 is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
Features
•One differential LVDS clock output pair
•Crystal interface designed for 18pF parallel resonant crystals
(20.4MHz – 28.3MHz)
•Output frequency range: 81.66MHz – 113.33MHz
•VCO range: 490MHz – 680MHz
•RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
•RMS phase jitter @ 156.25MHz, (1.875MHz - 20MHz):
0.45ps (typical)
•Full 3.3V or 2.5V operating supply
•Available in both standard (RoHs 5) and lead-free (RoHS 6)
packages
•0°C to 70°C ambient operating temperature
Common Configuration Table – Fibre Channel
HiPerClockS™
ICS
Inputs
Output Frequency (MHz)Crystal Frequency (MHz) M N Multiplication Value M/N
26.5625 24 6 4 106.25
25 24 6 4 100
OSC Phase
Detector
VCO
490MHz - 680MHz
M = ÷24 (fixed)
N = ÷6 (fixed)
Q
nQ
OE
XTAL_IN
XTAL_OUT
Pullup 1
2
3
4
8
7
6
5
VDDA
GND
XTAL_OUT
XTAL_IN
VDD
Q
nQ
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
Block Diagram Pin Assignment
ICS844011
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS844011AG REV. B AUGUST 28, 2009 2 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1V
DDA Power Analog power supply.
2GNDPower Power supply ground.
3,
4
XTAL_OUT,
XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5 OE Input Pullup Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ
output is in a high impedance state. LVCMOS/LVTTL interface levels.
6, 7 nQ, Q Output Differential clock output. LVDS interface levels.
8V
DD Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
RPULLUP Input Pullup Resistor 51 kΩ
ICS844011AG REV. B AUGUST 28, 2009 3 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C
Table 3B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C
Table 3C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 129.5°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage VDD – 0.07 3.3 VDD V
IDD Power Supply Current 90 mA
IDDA Analog Supply Current 7 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 2.375 2.5 2.625 V
VDDA Analog Supply Voltage VDD – 0.07 2.5 VDD V
IDD Power Supply Current 85 mA
IDDA Analog Supply Current 7 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VDD = 3.3V 2 VDD + 0.3 V
VDD = 2.5V 1.7 VDD + 0.3 V
VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V
VDD = 2.5V -0.3 0.7 V
IIH Input High Current OE VDD = VIN = 3.465V or 2.625V 5 µA
IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V -150 µA
ICS844011AG REV. B AUGUST 28, 2009 4 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 3D. LVDS DC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C
Table 3E. LVDS DC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C
Table 4. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 350 mV
∆VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.25 V
∆VOS VOS Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 350 mV
∆VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.2 V
∆VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 20.4 28.3 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
Drive Level 1mW
ICS844011AG REV. B AUGUST 28, 2009 5 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
AC Characteristics
Table 5A. AC Characteristics, VDD = 3.3V±5%, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to the phase noise plot.
Table 5B. AC Characteristics, VDD = 2.5V±5%, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to the phase noise plot.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 81.66 113.33 MHz
tjit(Ø) RMS Phase Jitter (Random);
NOTE 1
106.25MHz, Integration Range:
637kHz – 10MHz ps
100MHz, Integration Range:
637kHz – 10MHz 0.75 ps
tR / tFOutput Rise/Fall Time 20% to 80% 275 ps
odc Output Duty Cycle 50 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 81.66 113.33 MHz
tjit(Ø) RMS Phase Jitter (Random);
NOTE 1
106.25MHz, Integration Range:
637kHz – 10MHz 0.45 ps
100MHz, Integration Range:
637kHz – 10MHz 0.93 ps
tR / tFOutput Rise/Fall Time 20% to 80% 295 ps
odc Output Duty Cycle 50 %
ICS844011AG REV. B AUGUST 28, 2009 6 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
Output Rise/Fall Time
2.5V LVDS Output Load AC Test Circuit
RMS Phase Jitter
Offset Voltage Setup
SCOPE
Qx
nQx
3.3V±5%
POWER SUPPLY
+–
Float GND LVDS
VDD
VDDA
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ
Q
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
20%
80% 80%
20%
tRtF
VOD
nQ
Q
SCOPE
Qx
nQx
2.5V±5%
POWER SUPPLY
+–
Float GND LVDS
VDD
VDDA
Phase Noise Mas
k
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
out
out
LVDS
DC Input
➤
➤
➤
VOS/∆ VOS
VDD
ICS844011AG REV. B AUGUST 28, 2009 7 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844011 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD and VDDAshould be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin. Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS844011 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 26.5625MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
VDD
VDDA
3.3V or 2.5V
10Ω
10µF.01µF
.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
33p
C2
27p
ICS844011AG REV. B AUGUST 28, 2009 8 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 4. Tyical LVDS Driver Termination
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50Ω0.1µf
R1
R2
V
CC
V
CC
LVDS Driver
R1
100Ω
–
+
50Ω
50Ω
3.3V or 2.5V
VDD
100Ω Differential Transmission Line
ICS844011AG REV. B AUGUST 28, 2009 9 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844011 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (90mA + 7mA) = 336.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.336W * 129.5°C/W = 113.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
ICS844011AG REV. B AUGUST 28, 2009 10 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Reliability Information
Table 7. θJA vs. Air Flow Table for a 8-lead TSSOP
Transistor Count
The transistor count for ICS844011 is: 2533
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.20
A1 0.5 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D2.90 3.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS844011AG REV. B AUGUST 28, 2009 11 ©2009 Integrated Device Technology, Inc.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 9. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
844011AG 4011A 8-lead TSSOP Tube 0°C to 70°C
844011AG 4011A 8-lead TSSOP 2500 Tape & Reel 0°C to 70°C
844011AGLF 011AL Lead-Free, 8-lead TSSOP Tube 0°C to 70°C
844011AGLFT 011AL Lead-Free, 8-lead TSSOP 2500 Tape & Reel 0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS844011 Preliminary Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
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