© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 11
1Publication Order Number:
MC1489/D
MC1489, MC1489A
Quad Line EIA-232D
Receivers
The MC1489 monolithic quad line receivers are designed to
interface data terminal equipment with data communications
equipment in conformance with the specifications of EIA Standard
No. EIA−232D.
Features
•Input Resistance − 3.0 k to 7.0 kW
•Input Signal Range − ± 30 V
•Input Threshold Hysteresis Built In
•Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
•Pb−Free Packages are Available
DTL Logic Output
Interconnecting
Cable
Interconnecting
Cable
DTL Logic Input
Line Receiver
MC1489
Figure 1. Simplified Application
Line Driver
MC1488
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
1
14
See general marking information in the device marking
section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
1
14
SOEIAJ−14
M SUFFIX
CASE 965
PIN CONNECTIONS
Input D
13
Response
Control B
Input A
Response
Control A
1
Ground
Input B
2
Output C
Response
Control C
Output D
VCC
14
Response
Control D
Output A
Input C
Output B
8
9
10
11
12
7
5
3
4
6
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Figure 2. Representative Schematic Diagram
(1/4 of Circuit Shown)
3.8 k
Input 1
RF
Response Control 2
1.7 k
5.0 k
10 k
7 GND
3 Output
14
VCC
9.0 k
MC1489 MC1489A
RF6.7 kW1.6 kW
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MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted)
Rating Symbol Value Unit
Power Supply Voltage VCC 10 Vdc
Input Voltage Range VIR ± 30 Vdc
Output Load Current IL20 mA
Power Dissipation (Package Limitation, SOIC−14 and Plastic Dual In−Line Package)
Derate above TA = + 25°C
PD
1/qJA
1000
6.7
mW
mW/°C
Operating Ambient Temperature Range TA0 to + 75 °C
Storage Temperature Range Tstg − 65 to + 175 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted)
Characteristics Symbol Min Typ Max Unit
Positive Input Current (VIH = + 25 Vdc)
(VIH = + 3.0 Vdc)
IIH 3.6
0.43
−
−
8.3
−
mA
Negative Input Current (VIH = − 25 Vdc)
(VIH = − 3.0 Vdc)
IIL − 3.6
− 0.43
−
−
− 8.3
−
mA
Input Turn−On Threshold Voltage
(TA = + 25°C, VOL p 0.45 V) MC1489
MC1489A
VIH
1.0
1.75
−
1.95
1.5
2.25
Vdc
Input Turn−Off Threshold Voltage
(TA = + 25°C, VOH q 2.5 V, IL = − 0.5 mA) MC1489
MC1489A
VIL
0.75
0.75
−
0.8
1.25
1.25
Vdc
Output Voltage High (VIH = 0.75 V, IL = − 0.5 mA)
(Input Open Circuit, IL = − 0.5 mA)
VOH 2.5
2.5
4.0
4.0
5.0
5.0
Vdc
Output Voltage Low (VIL = 3.0 V, IL = 10 mA) VOL −0.2 0.45 Vdc
Output Short−Circuit Current IOS − − 3.0 − 4.0 mA
Power Supply Current (All Gates “on,” Iout = 0 mA, VIH = + 5.0 Vdc) ICC −16 26 mA
Power Consumption (VIH = + 5.0 Vdc) PC−80 130 mW
SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc ±1%, TA = + 25°C, See Figure 3.)
Propagation Delay Time (RL = 3.9 kW)tPLH −25 85 ns
Rise Time (RL = 3.9 kW)tTLH −120 175 ns
Propagation Delay Time (RL = 390 kW)tPHL −25 50 ns
Fall Time (RL = 390 kW)tTHL −10 20 ns
MC1489, MC1489A
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Vin
VR
All diodes
1N3064
or equivalent
Eo
R
tTLH and tTHL
measured
10% - 90%
Figure 3. Switching Response
C
1/4
MC1489A
RL
5.0 Vdc
50% 50%
3.0 V
Ein
tTHL
CL = 15 pF = total parasitic capacitance which includes
probe and wiring capacitances
1.5 V 1.5 V
tTLH
tPLH Response Node
VO
Ein
CL
C, capacitor is for noise filtering.
R, resistor is for threshold shifting.
EO
Figure 4. Response Control Node
TEST CIRCUITS
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TYPICAL CHARACTERISTICS
(VCC = 5.0 Vdc, TA = +25°C, unless otherwise noted)
Vin, INPUT VOLTAGE (V)
10
0
-10
-8.0
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
8.0
10
-25 -20 -15 -10 -5.0 5.0 15 2520
I , INPUT CURRENT (mA)
L
Figure 5. Input Current
II
VI
RT
1
RT
5.0 k
Vth
5.0 V
RT
13 k
Vth
5.0 V
6.0
5.0
4.0
3.0
2.0
1.0
0
3.02.01.00-2.0 -1.0-3.0
VI, INPUT VOLTAGE (V)
VILH
V , OUTPUT VOLTAGE (Vdc)
O
VIHL
EO
Vth
RT
VI
RT
11 k
Vth
-5.0 V
Figure 6. MC1489 Input Threshold
Voltage Adjustment
RT
1
VI, INPUT VOLTAGE (V)
3.0
4.0
5.0
6.0
1.0 2.00 4.0-2.0 -1.0-3.0
2.0
1.0
0
3.0
V , OUTPUT VOLTAGE (Vdc)
O
RT
5.0 k
Vth
5.0 V
RT
11 k
Vth
-5.0 V
Figure 7. MC1489A Input Threshold
Voltage Adjustment
EO
Vth
RT
Vin
VIHL
VILH
MC1489 VIH
MC1489 VIL
T, TEMPERATURE (°C)
+12
0
+600-60
0
0.2
0.4
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2.2
2.4
V , INPUT THRESHOLD VOLTAGE (Vdc)
IH
MC1489A VIL
MC1489A VIH
Figure 8. Input Threshold Voltage
versus Temperature
VIH MC1489A
VIH MC1489
VIL MC1489
VIL MC1489A
VCC, POWER SUPPLY VOLTAGE (V)
4.0 5.0 6.0
0
3.0
2.0
1.0
INPUT THRESHOLD VOLTAGE (Vdc)
Figure 9. Input Threshold versus
Power Supply Voltage
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APPLICATIONS INFORMATION
General Information
The Electronic Industries Association (EIA) has released
the EIA−232D specification detailing the requirements for
the interface between data processing equipment and data
communications equipment. This standard specifies not
only the number and type of interface leads, but also the
voltage levels to be used. The MC1488 quad driver and its
companion circuit, the MC1489 quad receiver, provide a
complete interface system between DTL or TTL logic levels
and the EIA−232D defined levels. The EIA−232D
requirements as applied to receivers are discussed herein.
The required input impedance is defined as between
3000 W and 7000 W for input voltages between 3.0 and 25 V
in magnitude; and any voltage on the receiver input in an
open circuit condition must be less than 2.0 V in magnitude.
The MC1489 circuits meet these requirements with a
maximum open circuit voltage of one VBE.
The receiver shall detect a voltage between − 3.0 and
−25 V as a Logic “1” and inputs between 3.0 and 25 V as a
Logic “0.” On some interchange leads, an open circuit of
power “OFF” condition (300 W or more to ground) shall be
decoded as an “OFF” condition or Logic “1.” For this
reason, the input hysteresis thresholds of the MC1489
circuits are all above ground. Thus an open or grounded
input will cause the same output as a negative or Logic “1”
input.
Device Characteristics
The MC1489 interface receivers have internal feedback
from the second stage to the input stage providing input
hysteresis for noise rejection. The MC1489 input has typical
turn−on voltage of 1.25 V and turn−off of 1.0 V for a typical
hysteresis of 250 mV. The MC1489A has typical turn−on of
1.95 V and turn−off of 0.8 V for typically 1.15 V of
hysteresis.
Each receiver section has an external response control
node in addition to the input and output pins, thereby
allowing the designer to vary the input threshold voltage
levels. A resistor can be connected between this node and an
external power supply. Figures 4, 6 and 7 illustrate the input
threshold voltage shift possible through this technique.
This response node can also be used for the filtering of
high frequency, high energy noise pulses. Figures 10 and 11
show typical noise pulse rejection for external capacitors of
various sizes.
These two operations on the response node can be
combined or used individually for many combinations of
interfacing applications. The MC1489 circuits are
particularly useful for interfacing between MOS circuits and
DTL/TTL logic systems. In this application, the input
threshold voltages are adjusted (with the appropriate supply
and resistor values) to fall in the center of the MOS voltage
logic levels (see Figure 12).
The response node may also be used as the receiver input
as long as the designer realizes that he may not drive this
node with a low impedance source to a voltage greater than
one diode above ground or less than one diode below
ground. This feature is demonstrated in Figure 13 where two
receivers are slaved to the same line that must still meet the
EIA−232D impedance requirement.
PW, INPUT PULSE WIDTH (ns)
500 pF
MC1489
6
5
4
3
2
1
10,000100010010
300 pF
100 pF
10 pF
E , AMPLITUDE (V)
in
Figure 10. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
MC1489A
PW, INPUT PULSE WIDTH (ns)
12 pF 500 pF
100 pF 300 pF
6
5
4
3
2
1
10,000100010010
E , AMPLITUDE (V)
in
Figure 11. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
MC1489, MC1489A
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7
Figure 12. Typical Translator Application − MOS to DTL or TTL
Response-Control Pin 1/2 MC1489
Response-Control Pin
Input
VCC
8.0 k
VCC
Input
Output
Output
+5.0 Vdc
+5.0 Vdc
DTL or TTL
R
+5.0 Vdc
-VDD
MC1489
-VGG
MOS
Logic
Figure 13. Typical Paralleling of Two MC1489, A Receivers to Meet EIA−232D
8.0 k
MC1489, MC1489A
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8
ORDERING INFORMATION
Device Package Operating Temperature Range Shipping†
MC1489D SOIC−14
TA = 0 to +75°C
55 Units/Rail
MC1489DG SOIC−14
(Pb−Free)
MC1489DR2 SOIC−14
2500 Tape & Reel
MC1489DR2G SOIC−14
(Pb−Free)
MC1489AD SOIC−14
55 Units/Rail
MC1489ADG SOIC−14
(Pb−Free)
MC1489ADR2 SOIC−14
2500 Tape & Reel
MC1489ADR2G SOIC−14
(Pb−Free)
MC1489P PDIP−14
25 Units/Rail
MC1489PG PDIP−14
(Pb−Free)
MC1489AP PDIP−14
MC1489APG PDIP−14
(Pb−Free)
MC1489M SOEIAJ−14
50 Units/Rail
MC1489MG SOEIAJ−14
(Pb−Free)
MC1489MEL SOEIAJ−14
2000 Tape & Reel
MC1489MELG SOEIAJ−14
(Pb−Free)
MC1489AM SOEIAJ−14
50 Units/Rail
MC1489AMG SOEIAJ−14
(Pb−Free)
MC1489AMEL SOEIAJ−14
2000 Tape & Reel
MC1489AMELG SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC1489, MC1489A
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9
MARKING DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
1
14
MC1489AP
AWLYYWWG
1
14
MC1489P
AWLYYWWG
MC1489A
ALYWG
SOEIAJ−14
M SUFFIX
CASE 965
MC1489
ALYWG
MC1489ADG
AWLYWW
1
14
MC1489DG
AWLYWW
1
14
MC1489, MC1489A
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10
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC1489, MC1489A
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11
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J
0.290 0.310 7.37 7.87
MC1489, MC1489A
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12
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.004 0.008
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC3423/D
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