CY7C1345B PRELIMINARY 128K x 36 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description * Supports 117-MHz microprocessor cache systems with zero wait states * 128K by 36 common I/O * Fast clock-to-output times -- 7.5 ns (117-MHz version) * Two-bit wrap-around counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous output enable * 3.3V I/Os * JEDEC-standard pinout * 100-pin TQFP packaging * ZZ "sleep" mode Logic Block Diagram GW The CY7C1345B allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[16:0] The CY7C1345B is a 3.3V, 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. Q 17 15 ADDRESS CE REGISTER D 15 17 128K X 36 MEMORY ARRAY DDQ[31:24],DP3Q BYTEWRITE REGISTERS BWE BWS3 BWS 2 DDQ[23:16],DP2Q BYTEWRITE REGISTERS BWS 1 D DQ[15:8],DP1 Q BYTEWRITE REGISTERS D DQ[7:0],DP0 Q BYTEWRITE REGISTERS BWS 0 CE1 CE2 CE3 36 36 D ENABLE Q CE REGISTER CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[31:0] DP[3:0] Selection Guide 7C1345B-117 7C1345B-100 7C1345B-90 7C1345B-50 Maximum Access Time (ns) 7.5 8.0 8.5 11.0 Maximum Operating Current (mA) 350 325 300 250 Maximum Standby Current (mA) 2.0 2.0 2.0 2.0 Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 April 5, 2000 PRELIMINARY CY7C1345B 2 3 VDDQ VSSQ DQ18 A8 A9 81 82 ADSP ADV 83 84 BWE OE ADSC 85 86 CLK VSS GW 87 88 89 CE3 BWS0 VDD 90 91 92 93 BWS2 BWS3 CE2 BWS1 94 95 96 97 A7 CE1 98 80 79 DP1 78 DQ15 DQ14 4 77 VDDQ 5 6 76 75 VSSQ DQ13 DQ19 7 74 DQ12 DQ20 DQ21 8 9 73 72 DQ11 VSSQ 10 71 VDDQ DQ22 11 12 70 69 DQ23 13 68 VSSQ 14 VDD NC 15 16 VSS 17 64 VDD ZZ DQ24 DQ25 18 19 63 62 DQ7 DQ6 VDDQ 20 61 VDDQ VSSQ DQ26 21 22 60 59 VSSQ DQ27 23 58 DQ28 DQ29 24 57 56 VSSQ 100-Pin TQFP CY7C1345B 67 66 65 25 26 DQ10 VSSQ DQ9 DQ8 VSS NC DQ5 DQ4 DQ3 DQ2 38 39 40 41 42 45 46 47 48 49 50 DNU DNU VSS VDD DNU DNU A10 A11 A12 A13 A14 A15 A16 44 37 A0 43 36 DP0 A1 51 35 30 34 DP3 A2 VDDQ DQ1 DQ0 A3 53 52 33 28 29 A4 VSSQ 54 32 55 27 2 BYTE1 VDDQ VDDQ DQ30 DQ31 31 BYTE3 1 MODE A5 BYTE2 DP2 DQ16 DQ17 99 100 A6 Pin Configurations BYTE0 PRELIMINARY CY7C1345B Pin Configurations (continued) 119-Ball BGA 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A CE3 NC C NC A A VDD A A NC D DQc DQPc VSS NC VSS DQPb DQb E F DQc VDDQ DQc DQc VSS VSS CE1 OE VSS VSS DQb DQb DQb VDDQ G H J DQc DQc DQc DQc BWc VSS ADV GW BWb VSS DQb DQb DQb DQb VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M N VDDQ DQd DQd DQd VSS VSS BWE A1 VSS VSS DQa DQa VDDQ DQa P DQd DQPd VSS A0 VSS DQPa DQa R NC A MODE VDD VSS A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ the specified address location. Byte writes are allowed. During byte writes, BW0 controls DQ[7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are three-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ [31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Functional Description Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BW[3:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BW0 controls DQ [7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ [31:24]. All I/Os are three-stated during a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSC Burst Sequences This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[3:0]) indicate a write access. ADSC is ignored if ADSP is active LOW. The CY7C1338 provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Single Read Accesses The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The information presented to DQ[31:0] will be written into 3 PRELIMINARY CY7C1345B Sleep Mode Table 1. Counter Implementation for the Intel(R) Pentium(R)/80486 Processor's Sequence First Address Second Address Third Address Fourth Address AX + 1, Ax AX + 1, Ax AX + 1, Ax AX + 1, Ax 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE 2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. Table 2. Counter Implementation for a Linear Sequence First Address Second Address Third Address Fourth Address AX + 1, Ax AX + 1, Ax AX + 1, Ax AX + 1, Ax 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 4 PRELIMINARY CY7C1345B Cycle Description Table[1, 2, 3] Cycle Description ADD Used CE1 CE3 CE2 ZZ ADSP ADSP ADV WE OE CLK DQ Deselected Cycle, Power-down None H X X L X L X X X L-H High-Z Deselected Cycle, Power-down None L X L L L X X X X L-H High-Z Deselected Cycle, Power-down None L H X L L X X X X L-H High-Z Deselected Cycle, Power-down None L X L L H L X X X L-H High-Z Deselected Cycle, Power-down None X X X L H L X X X L-H High-Z Snooze Mode, Power-down None X X X H X X X X X X High-Z External L L H L L X X X L L-H Read Cycle, Begin Burst Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 1. X= "Don't Care," 1 = Logic HIGH, 0 = Logic LOW. 2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a "Don't Care" for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active. 5 PRELIMINARY CY7C1345B Write Cycle Descriptions[1, 2, 3, 4] Function GW BWE BW3 BW2 BW1 BW0 Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0, DP0 1 0 1 1 1 0 Write Byte 1, DP1 1 0 1 1 0 1 Write Bytes 1, 0, DP 0, DP1 1 0 1 1 0 0 Write Byte 2, DP2 1 0 1 0 1 1 Write Bytes 2, 0, DP 2, DP0 1 0 1 0 1 0 Write Bytes 2, 1, DP 2, DP1 1 0 1 0 0 1 Write Bytes 2, 1, 0, DP2, DP1, DP0 1 0 1 0 0 0 Write Byte 3, DP3 1 0 0 1 1 1 Write Bytes 3, 0, DP 3, DP0 1 0 0 1 1 0 Write Bytes 3, 1, DP 3, DP0 1 0 0 1 0 1 Write Bytes 3, 1, 0, DP3, DP1, DP0 1 0 0 1 0 0 Write Bytes 3, 2, DP 3, DP2 1 0 0 0 1 1 Write Bytes 3, 2, 0, DP3, DP2, DP0 1 0 0 0 1 0 Write Bytes 3, 2, 1, DP3, DP2, DP1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit ICCZZ Snooze mode standby current ZZ > VDD - 0.2V 3 mA tZZS Device operation to ZZ ZZ > VDD - 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns DC Input Voltage[5] ................................ -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................-65C to +150C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied .............................................-55C to +125C Operating Range Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Ambient Range Temperature[6] DC Voltage Applied to Outputs in High Z State[5] ....................................-0.5V to VDD + 0.5V Com'l Notes: 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 6. TA is the case temperature. 6 0C to +70C VDD VDDQ 3.135V to 3.6V 2.375V to VDD PRELIMINARY CY7C1345B Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min. VDDQ = 3.3V, V DD = Min., IOH = -4.0 mA 2.4 VDDQ = 2.5V, V DD = Min., IOH = -2.0 mA 1.7 Max. Unit V V VDDQ = 3.3V, V DD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, V DD = Min., IOL = 2.0 mA 0.7 V VIH Input HIGH Voltage 1.7 VDD + 0.3V V VIL Input LOW Voltage[5] -0.3 0.8 V IX Input Load Current (except ZZ and MODE) GND VI VDDQ -1 1 A Input Current of MODE Input = VSS -30 5 A 30 A 5 A -300 mA 8.5-ns cycle, 117 MHz 350 mA 10-ns cycle, 100 MHz 325 mA 11-ns cycle, 90 MHz 300 mA 20-ns cycle, 50 MHz 250 mA 35 mA 30 mA 25 mA 20 mA Input = VDDQ Input Current of ZZ Output Leakage Current IOS Output Short Circuit Current IDD VDD Operating Supply Current ISB1 Automatic CE Power-Down Current--TTL Inputs [7] A -5 Input = VSS Input = VDDQ IOZ A GND VI VDD, Output Disabled VDD = Max., VOUT = GND VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC -5 Max. VDD, Device Deselected, 8.5-ns cycle, 117 MHz VIN VIH or VIN VIL 10-ns cycle, 100 MHz f = fMAX = 1/tCYC, inputs switching 11-ns cycle, 90 MHz 20-ns cycle, 50 MHz ISB2 Automatic CE Power-Down Current--CMOS Inputs All speeds Max. VDD, Device Deselected, VIN 0.3V or VIN > VDDQ - 0.3V, f = 0, inputs static 10 mA ISB3 Automatic CE Power-Down Current--CMOS Inputs Max. VDD, Device Deselected, 8.5-ns cycle, 117 MHz VIN VDDQ- 0.3V or VIN 0.3V, 10-ns cycle, 100 MHz f = fMAX, inputs switching 11-ns cycle, 90 MHz 10 mA 10 mA 10 mA 10 mA 18 mA 20-ns cycle, 50 MHz ISB4 Automatic CE Power-Down Current--TTL Inputs Max. VDD, Device Deselected, VIN VDD -0.3V or VIN 0.3V, f = 0, inputs static Note: 7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 7 PRELIMINARY CY7C1345B Capacitance[8] Parameter Description CIN Input Capacitance CI/O I/O Capacitance Test Conditions Max. Unit 4.0 pF 4.0 pF TA = 25C, f = 1 MHz, VDD = 5.0V AC Test Loads and Waveforms R1=317 OUTPUT 3.3V Z0 =50 RL =50 ALL INPUT PULSES OUTPUT 3.0V INCLUDING JIG AND SCOPE (a) R2=351 GND 5 pF VL =1.5V 10% 90% 10% 90% Rise Time: 1 V/ns Fall Time: 1 V/ns (b) Switching Characteristics Over the Operating Range[9] -117 Parameter Description Min. Max. -100 Min. Max. -90 Min. -50 Max. Min. Max. Unit tCYC Clock Cycle Time tCH Clock HIGH 3.0 tCL Clock LOW 3.0 tAS Address Set-Up Before CLK Rise 2.0 tAH Address Hold After CLK Rise 0.5 tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2.0 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tWEH BWS[1:0], GW,BWE Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns 8.5 10 11 20 ns 4.0 4.5 4.5 ns 4.0 4.5 4.5 ns 2.0 2.0 2.0 ns 0.5 0.5 0.5 ns 7.5 8.0 8.5 11.0 ns tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns [10, 11] tCHZ Clock to High-Z tCLZ Clock to Low-Z[10, 11] tEOHZ OE HIGH to Output High-Z[10, 12] tEOLZ OE LOW to Output Low-Z tEOV OE LOW to Output Valid 3.5 0 3.5 0 3.5 [10, 12] 0 3.5 0 3.5 3.5 0 3.5 0 3.5 3.5 0 3.5 0 3.5 ns ns ns ns 3.5 ns Notes: 8. Tested initially and after any design or process changes that may affect these parameters. 9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. 10. tCHZ, t CLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 11. At any given voltage and temperature, t CHZ (max.) is less than tCLZ (min.). 12. This parameter is sampled and not 100% tested. 8 PRELIMINARY CY7C1345B Timing Diagrams Write Cycle Timing[13, 14] S ingle W rite B urst W rite Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data- High-Z In 1a 1a 2a 2c 2b = UNDEFINED 2d 3a = DON'T CARE Notes: 13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table). 14. WDx stands for Write Data to Address X. 9 High-Z PRELIMINARY CY7C1345B Timing Diagrams (continued) Read Cycle Timing[13, 15] Burst Read Single Read tCYC Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE Data Out tCEH tEOV tCDV tOEHZ tDOH 2a 1a 1a 2c 2c 2b 2d 3a tCLZ tCHZ = DON'T CARE = UNDEFINED Note: 15. RDx stands for Read Data from Address X. 10 PRELIMINARY CY7C1345B Timing Diagrams (continued) Read/Write Timing tCYC tCH tCL CLK tAH tAS ADD A B D C tADH tADS ADSP tADH tADS ADSC tADVH tADVS ADV tCEH tCES CE1 tCEH tCES CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tEOHZ tCLZ Data Q(A) In/Out Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table). CE is the combination of CE 2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON'T CARE 11 = UNDEFINED PRELIMINARY CY7C1345B Timing Diagrams (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD RD1 tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWES tWEH WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 1a In 4a Out 2a In 3a In 4a D(C) In tCDV tDOH Back to Back Reads tCHZ Back to Back Writes = UNDEFINED = DON'T CARE 12 PRELIMINARY Timing Diagrams (continued) OE Switching Waveforms OE tEOV tEOHZ I/Os three-state tEOLZ 13 CY7C1345B PRELIMINARY CY7C1345B Timing Diagrams (continued) ZZ Mode Timing [16, 17] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ ICC tZZS ICC(active) ICCZZ tZZREC I/Os Three-state Notes: 16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device. 17. I/Os are in three-state when exiting ZZ sleep mode. 14 PRELIMINARY CY7C1345B Ordering Information Speed (MHz) Ordering Code Package Name Package Type 117 CY7C1345B-117AC A101 100-Lead Thin Quad Flat Pack 100 CY7C1345B-100AC A101 100-Lead Thin Quad Flat Pack 90 CY7C1345B-90AC A101 100-Lead Thin Quad Flat Pack 50 CY7C1345B-50AC A101 100-Lead Thin Quad Flat Pack Operating Range Commercial Document #: 38-00953-*A Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A (c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.