CY7C1345B
PRELIMINARY
3
Functional Description
Single Write Accesses Init iated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
count er/con trol logic and deli ver ed t o the RAM cor e. The wri te
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active ( see W rite
Cycle Descr iptions table for appropr iate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 control s DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasser ted and the I/Os must be three-stated pri or to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines ar e three-stated once a write cycle i s detected, re-
gardless of the state of OE .
Single Wri te Accesses Initiated by ADSC
This writ e acc ess is i nitiat ed when the f oll owing c ondit ions ar e
satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BW E, and BW[3:0])
indi cate a write access. ADSC is ignored if ADS P is active LOW.
The addr ess es presen ted are loa ded int o th e address regist er
and the burst counter/cont rol logic and delivered to the RAM
core. The informatio n presented to DQ[31:0] will be written into
the speci fied address locat ion. Byte writ es are allowed. During
b y te wri tes, BW0 c ontrols DQ[7:0], BW1 c ontrols DQ[15:8], BW 2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three- stat ed when a wri te is detect ed, e v en a byt e write . Si nce
this is a c ommon I/O de vi ce, the asynchronous O E input si gnal
must be dea sserted an d the I/ Os must be three -stat ed prior to
the pr esentation of da ta to DQ[31:0]. As a safet y precauti on, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Read Acces ses
A singl e read access is initiated when the following conditions
ar e satisfied at clock rise: (1) CE1, CE 2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the wri te input s must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control lo gic and presented to the m em ory core. If the
OE input is asserted LO W , the request ed data will be av ailabl e
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Burst Se quences
The CY7C1338 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LO W on MODE wi ll se lect a line ar bu rst se quenc e. A HI GH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence .
Pin Configurations (conti nued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC DQPc
DQc
DQd
DQc
DQd
AA AAADSP VDDQ
CE2A
DQc
VDDQ
DQc
VDDQ
VDDQ
VDDQ
DQd
DQd
NC
NC VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
NCNCNCNC NCNC NC
VDDQ
VDDQ
VDDQ
AAAA
CE3
AA
A
AA
AA0
A1
DQa
DQc
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQb
VDD
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS DQPa
MODE
DQPd
DQPb
BWb
BWc
NC VDD NC
BWa
NC
BWE
BWd
ZZ
119-Ball BGA
A