Description
The A8510 is a multi-output white LED driver for LCD
backlighting. It integrates a current-mode boost converter with
internal power switch and 8 current sinks. The boost converter
can drive up to 96 LEDs with 12 LEDs at 40 mA per string.
The LED sinks can also be paralleled together to achieve even
higher LED currents, up to 320 mA. The A8510 can operate
from a single power supply, from 5 to 40 V.
If required, the A8510 can drive an external P-FET to
disconnect the input supply from the system in the event of a
fault. The A8510 provides protection against output short and
overvoltage, open or shorted diode, open or shorted LED pin,
and overtemperature. A dual level cycle-by-cycle current limit
function provides soft start and protects the internal current
switch against high current overloads.
The A8510 has a synchronization pin that allows PWM
switching frequencies to be synchronized in the range of
580 kHz to 2.3 MHz.
The device package is a 26-contact, 4 mm × 4 mm, 0.75 mm
nominal overall height QFN, with exposed pad for enhanced
thermal dissipation. It is lead (Pb) free, with 100% matte tin
leadframe plating.
A8510-DS, Rev. 2
Features and Benefits
• Integrated 2 MHz capable boost converter with 60 V DMOS
switch with OVP protection
• Sync function to synchronize boost converter switching
frequencies up to 2.3 MHz
• LED current up to 40 mA per LED channel into 8 channels
• Drives up to 12 series LEDs in 8 parallel strings
(Vf = 3.5 V, If = 40 mA), VIN = 8 V, switching frequency
of 1 MHz
• Single EN/PWM pin interface for PWM dimming and
enable functions
• APWM pin for fine-tuning color adjustment and/or
maximizing contrast ratio
• Integrated driver for optional external PMOS input
disconnect switch
• Typical LED accuracy of 0.7% and 0.8% for
LED-to-LED matching
• Internal bias supply for single-supply operation
from 5 to 40 V
• Extensive protection features
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
Typical Application Diagram
A8510
Package: 26-pin QFN (suffix EC)
Applications
• Industrial LCD displays
• Backlighting LCD displays
• Infotainment displays
Figure 1. Typical Application Circuit showing VIN to GND
short protection using P-MOSFET sensing
Approximate scale 1:1
VGATE SW SW
Q1
L1 D1
CVDD
OVP
VOUT
ROVP COUT
RSC
RADJ
VSENSE
VIN
VDD
EN/PWM
APWM
ISET
FSET/SYNC
AGND PGND PGND
COMP
CPRZ
CZ
LED8
LED1
LED2
LED3
LED4
LED5
LED6
LED7
FAULT
PAD
A8510
120
VC
22 H
169 k
0.056
590
100 k
RISET
8.25 kRFSET
25.5 k
4.7 F
50 V
CIN
4.7 F/ 50 V
0.1 F
0.47 F
120 pF
VIN 2 A /
60 V
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Unit
LEDx Pin –0.3 to 55 V
OVP Pin –0.3 to 60 V
VIN, VSENSE, VGATE Pins VSENSE and VGATE should not exceed VIN by
more than 0.4 V. –0.3 to 40 V
SW Pin Continuous –0.6 to 62 V
t < 50 ns –1.0 V
¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
Pin –0.3 to 40 V
ISET, FSET/SYNC, APWM, and
COMP Pins –0.3 to 5.5 V
All other pins –0.3 to 7 V
Operating Ambient Temperature TARange G –40 to 105 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to Absolute-Maximum-rated conditions for extended periods may affect device reliability.
Selection Guide
Part Number Packing
A8510GECTR-T 7000 pieces per 13-in. reel
Thermal Characteristics may require derating at maximum conditions
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RJA On 2-layer, 3 in. × 3 in. PCB 48.5 ºC/W
*Additional thermal information available on the Allegro website
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
VDD
Regulator
UVLO
Internal
Soft Start
Enable
PWM
Thermal
Shutdown
Open/Short
LED Detect
ISET
Fault
LED
Driver
1.235 V
Ref
Driver
Circuit
Internal VCC
Internal VCC
VREF
Internal VCC
VREF
VREF
ISS
ISS
IADJ
GOFF
100 k
AGND
Current
Sense
Input Current
Sense Amplifier
PMOS
Driver
Diode
Open
Sense
OVP
Sense
Oscillator
SW
VIN
FSET/SYNC
COMP
VSENSE
VGATE
EN/PWM
APWM
PGND PGND AGND
ISET
OVP
LED2
LED1
LED4
LED5
LED6
LED7
LED8
LED3
FAULT
AGND
PGND
+
–
+
–
+
–
+
–
+
–
SW
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pin-out Diagram
Terminal List Table
Number Name Function
1 VIN Input power to the A8510 as well as the positive input used for the current sense resistor.
2¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
This pin is used to indicate a fault condition, it is an open drain type configuration that will be pulled
low when a fault occurs; connect a 100 k resistor between this pin and the required logic level
voltage.
3, 9 NC No connect.
4 COMP Output of the error amplifier and compensation node; connect a series RZCZ network from this pin to
GND for control loop compensation.
5 APWM Analog trimming option or dimming; applying a digital PWM signal to this pin adjusts the internal ISET
current.
6 EN/PWM PWM dimming pin used to control the LED intensity by using pulse width modulation, with the typical
PWM dimming frequency is in the range of 200 Hz to 1 kHz; also used to enable the A8510.
7 FSET/SYNC
Frequency/synchronization pin; connect a resistor RFSET from this pin to GND to set the switching
frequency. This pin can also be used to synchronize two or more converters in the system; the
maximum synchronization frequency is 2.3 MHz.
8 ISET Connect the RISET resistor between this pin and GND to set the LED 100% current level.
10 to
18
LED8 to
LED1 Connect the cathode of each LED string to these pins.
19 VDD Output of internal LDO; connect a 0.1 F decoupling capacitor between this pin and GND.
20, 21 PGND Power ground for internal NMOS device.
22 OVP This pin is used to sense an overvoltage condition; connect the ROVP resistor from VOUT to this pin to
adjust the Overvoltage Protection (OVP) function.
23, 24 SW The drain of the internal NMOS switch of the boost converter.
25 VGATE Gate driver pin for external P-MOSFET disconnect switch.
26 VSENSE Connect this pin to the negative sense side of the current sense resistor RSC; the threshold voltage
is measured as VIN – VSENSE.
–PAD
Exposed pad of the package providing enhanced thermal dissipation; this pad must be connected to
the ground plane(s) of the PCB with at least 8 thermal vias, directly in the pad.
PAD
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
26
25
24
23
22
VSENSE
VGATE
SW
SW
OVP
ISET
NC
AGND
LED8
LED7
LED6
LED5
PGND
PGND
VDD
LED1
LED2
LED3
LED4
VIN
FAULT
NC
COMP
APWM
EN/PWM
FSET/SYNC
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and
characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
Input Voltage Specifications
Operating Input Voltage Range3VIN 5 – 40 V
UVLO Start Threshold VUVLOrise VIN rising – 4.35 V
UVLO Stop Threshold VUVLOfall VIN falling – 3.90 V
UVLO Hysteresis4VUVLOhys – 450 – mV
Input Currents
Input Quiescent Current IQEN/PWM = VIH ; SW = 2 MHz, no load 5.5 mA
Input Sleep Supply Current IQSLEEP VIN = 16 V, EN/PWM = SYNC = 0 V 2 10.0 A
Input Logic Levels (EN/PWM, APWM)
Input Logic Level-Low VIL VIN throughout operating input voltage range – – 400 mV
Input Logic Level-High VIH VIN throughout operating input voltage range 1.5 – – V
EN/PWM Pin Pin Pull-Down Resistor REN EN/PWM = 5 V – 100 – k
APWM Pin Pull-Down Resistor RAPWM APWM = VIH – 100 – k
APWM
APWM Frequency fAPWM 20 1000 kHz
Error Amplifier
Open Loop Voltage Gain AVOL 48 dB
Transconductance gmICOMP = ±10 A990 A/V
Source Current IEA(SRC) VCOMP = 1.5 V –350 A
Sink Current IEA(SINK) VCOMP = 1.5 V 350 A
COMP Pin Pull-Down Resistor RCOMP 2000 
Overvoltage Protection
Overvoltage Threshold VOVP(th) OVP connected to VOUT 7.7 8.1 8.5 V
OVP Sense Current IOVPH 188 199 210 A
OVP Leakage Current IOVPLKG ROVP = 40.2 k, VIN = 16 V, EN/PWM = VIL 0.1 1 A
Secondary Overvoltage Protection VOVP(sec) 55 V
Boost Switch
Switch On-Resistance RSW ISW = 0.750 A, VIN = 16 V 300 m
Switch Leakage Current ISWLKG VSW = 16 V, EN/PWM = VIL 0.1 1 A
Switch Current Limit ISW(LIM) 3.0 3.5 4.2 A
Secondary Switch Current Limit4ISW(LIM2)
Higher than ISW(LIM)(max) for all conditions,
device latches when detected 7.0 A
Soft Start Boost Current Limit ISWSS(LIM) Initial soft start current for boost switch 700 mA
Minimum Switch On-Time tSWONTIME 85 ns
Minimum Switch Off-Time tSWOFFTIME 47 ns
Continued on the next page…
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Oscillator Frequency
Oscillator Frequency fSW
RFSET = 10 k1.8 2 2.2 MHz
RFSET = 20 k1MHz
RFSET = 35.6 k580 kHz
FSET/SYNC Pin Voltage VFSET RFSET = 10 k1.00 V
FSET Frequency Range fFSET 580 2500 kHz
Synchronization
Synchronized PWM Frequency fSWSYNC 580 2300 kHz
Synchronization Input
Minimum Off-Time tPWSYNCOFF 150 ns
Synchronization Input
Minimum On-Time tPWSYNCON 150 ns
SYNC Input Logic Voltage VSYNC(H) FSET/SYNC pin, high level 0.4 V
VSYNC(L) FSET/SYNC pin, low level 2.0 V
LED Current Sinks
LEDx Accuracy ErrLED ISET = 120 A3%
LEDx Matching LEDx ISET = 120 A3%
LEDx Regulation Voltage VLED VLED1 through VLED8 all equal, ISET = 120 A680 mV
ISET to ILEDx Current Gain AISET ISET = 120 A 317 327 337 A/A
ISET Pin Voltage VISET 1.003 V
Allowable ISET Current ISET 40 120 A
VLED Short Detect VLEDSC
While LED sinks are in regulation, sensed
from LEDx pin to GND 4.6 V
Soft Start LEDx Current ILEDSS
Current through each enabled LEDx pin
during soft start, ISET = 120 A1.06 mA
Maximum PWM Dimming
Until Off-Time3tPWML
Measured while EN/PWM = low, during
dimming control and internal references
are powered-on (exceeding tPWML results in
shutdown)
32750 fSW
cycles
Minimum EN/PWM On-Time tPWMH First cycle when powering-up device 0.75 2 s
EN/PWM High to LED-On Delay tdPWM(on)
Time between EN/PWM enable and LEDx
current reaching 90% of maximum 0.5 1 s
EN/PWM Low to LED-Off Delay tdPWM(off)
Time between EN/PWM enable going low
and LEDx current reaching 10% of maximum 500 ns
VGATE Pin
VGATE Pin Sink Current IGSINK VGS = VIN 104 A
VGATE Pin Fault Shutdown tGFAULT 3s
VGATE Pin Voltage VGS
Gate to source voltage measured when gate
is on –6.7 V
ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design
and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
Continued on the next page…
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VSENSE Pin
VSENSE Pin Sink Current IADJ 18.8 20.3 21.8 A
VSENSE Trip Point VSENSEtrip
Measured between VIN and VSENSE,
RADJ = 0 180 mV
¯
F
¯
¯
A
¯
¯
U ¯¯
L
¯
¯
T
¯
Pin
¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
Pin Pull-Down Voltage VFAULT IFAULT = 1 mA (400 )0.5 V
¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
Pin Leakage Current IFAULTLKG VFAULT = 5 V 1A
Thermal Protection (TSD)
Thermal Shutdown Threshold4TSD Temperature rising 165 ºC
Thermal Shutdown Hysteresis4TSDHYS 20 ºC
1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as
going into the node or pin (sinking).
2Typical specifications are at TA = 25ºC.
3Minimum VIN = 5 V is only required at startup. After startup is completed, the IC is able to function down to VIN = 4 V.
4Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design
and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Characteristic Performance
-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100
7.7
7.6
7.8
7.9
8.0
8.1
8.2
8.3
8.4
VOVP(th) (V)
190
192
194
196
198
200
202
204
206
208
210
IOVPH (μA)
3.60
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.70
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
f
SW
(MHz)
Switching Frequency
OVP Pin Sense Current OVP Pin Overvoltage Threshold
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
V
UVLOrise
(V)V
UVLOfall
(V)
0
1
2
3
4
5
IQSLEEP (μA)
VIN Input Sleep Mode Current
versus Ambient Temperature
VIN UVLO Rising Threshold Voltage
VIN UVLO Falling Threshold Voltage
versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
-50-40-30-20-10 1020304050607080901001100-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100-50-40-30-20-10 1020304050607080901001100
-50-40-30-20-10 1020304050607080901001100-50-40-30-20-10 1020304050607080901001100
20.0
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
IADJ (μA)
VSENSE Pin Sink Current
-6.9
-6.8
-6.7
-6.6
-6.5
-6.4
-6.3
V
GS
(V)
Input Disconnect Switch
Voltage
Gate to Source
330
329
328
327
326
325
324
323
322
321
320
A
ISET
Temperature (°C) Temperature (°C)
Temperature (°C) Temperature (°C)
ISET to LED Current Gain
versus Ambient Temperature versus Ambient Temperature
versus Ambient Temperature
LEDx Current
versus Ambient Temperature
ISET = 120 μA
LED Current, I
LEDx
(mA)
40.0
39.8
39.6
39.4
39.2
39.0
38.8
38.6
38.4
38.2
38.0
10.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
ΔLEDx (%)
LED to LED Matching Accuracy
Temperature (°C) Temperature (°C)
versus Ambient Temperature
LED Set Point Accuracy
versus Ambient Temperature
LEDx Accuracy, Err
LED
(%)
92
90
88
86
84
92
80
Efficiency, η (%)
Input Voltage, VIN (V)
Efficiency for 10 Series LEDs per Channel
ILED = 40 mA, LED Vf ≈ 3.2 V
7 9 11 13 15 17 19 21
fSW
800 kHz
1 MHz
95
90
85
75
70
Efficiency, η (%)
Input Voltage, VIN (V)
Efficiency for 12 Series LEDs per Channel
ILED = 40 mA, LED Vf ≈ 3.2 V
7 9 11 13 15 17 19 21
fSW
800 kHz
1 MHz
f
S
W
800
kHz
1
MH
z
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The A8510 incorporates a current-mode boost controller with
internal DMOS switch, and eight LED current sinks. It can be
used to drive eight LED strings of up to 12 white LEDs in series,
with current up to 40 mA per string. For optimal efficiency,
the output of the boost stage is adaptively adjusted to the mini-
mum voltage required to power all of the LED strings. This is
expressed by the following equation:
VOUT = max ( VLED1 ,..., VLED8 ) + VREG (1)
where
VLEDx is the voltage drop across LED strings 1 through 8, and
VREG is the regulation voltage of the LED current sinks (typi-
cally 0.68 V at the maximum LED current).
Enabling the IC
The IC turns on when a logic high signal is applied on the
EN/PWM pin with a minimum duration of tPWMH for the first
clock cycle, and the input voltage present on the VIN pin is
greater than the 4.35 V necessary to clear the UVLO (VUVLOrise )
threshold. The power-up sequence is shown in figure 2. Before
the LEDs are enabled, the A8510 driver goes through a system
check to determine if there are any possible fault conditions that
might prevent the system from functioning correctly. Also, if the
FSET/SYNC pin is pulled low, the IC will not power-up. More
information on the FSET/SYNC pin can be found below, in the
Synchronization section of this document.
Powering up: LED pin short-to-GND check
The VIN pin has a UVLO function that prevents the A8510 from
powering-up until the UVLO threshold is reached. After the VIN
pin goes above UVLO, and a high signal is present on the EN/
PWM pin, the IC proceeds to power-up. As shown in figure 3, at
this point the A8510 enables the disconnect switch and checks if
any LED pins are shorted to GND and/or are not used. The LED
detect phase starts when the VGATE voltage of the disconnect
switch is equal to VIN – 4.5 V.
After the voltage threshold on the LEDx pins exceeds 120 mV, a
timer of 3000 to 4000 clock cycles is used to determine the status
of the pins. Thus, the LED detection duration varies with the
switching frequency, as shown in the following table:
Switching Frequency
(kHz)
Detection Time
(ms)
2000 1.5 to 2
1000 3 to 4
800 3.75 to 5
600 5 to 6.7
The LED pin detection voltage thresholds are as follows:
LED Pin Voltage LED Pin Status Action
<70 mV Short-to-GND Power-up is halted
150 mV Not used LED removed from operation
>325 mV LED pin in use None
Functional Description
Figure 2. Power-up diagram at fSW = 2 MHz; shows VDD (ch1, 2 V/div.),
FSET/SYNC (ch2, 1 V/div.), ISET (ch3, 1 V/div.), and EN/PWM (ch4, 2 V/
div.) pins, t = 200 s/div.
Figure 3. Power-up diagram; shows the relationship of an LEDx pin with
respect to the gate voltage of the disconnect switch (if used) during the
LED detect phase, as well as the duration of the LED detect phase for a
switching frequency of 800 kHz; shows VGATE (ch1, 5 V/div.), LEDx (ch2,
500 mV/div.), ISET (ch3, 1 V/div.), and EN/PWM (ch4, 5 V/div.) pins,
t = 1 ms/div.
t
VDD
EN/PWM
FSET/SYNC
ISET
C1
C3
C4
C2
t
VGATE
VGATE = VIN – 4.5 V
LED detection period
EN/PWM
LEDx
ISET
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
All unused pins should be connected with a 4.75 k resistor to
GND, as shown in figure 5. The unused pin, with the pull-down
resistor, will be taken out of regulation at this point and will not
contribute to the boost regulation loop.
If an LEDx pin is shorted to ground the A8510 will not proceed
with soft start until the short is removed from the LEDx pin. This
prevents the A8510 from powering-up and putting an uncon-
trolled amount of current through the LEDs. The various detect
scenarios are presented in figures 4A and 4B.
4A. Example with LED8 pin not being used; fSW is 2 MHz, the detect voltage
is about 150 mV; shows LED1-7 (ch1, 500 mV/div.), LED8 (ch2, 500 mV/div.),
ISET (ch3, 1 V/div.), and EN/PWM (ch4, 5 V/div.) pins, t = 500 s/div.
4B. Example with one LED shorted to GND. The IC will not proceed with power-
up until the shorted LED pin is released, at which point the LED is checked to
see if it is being used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.),
ISET (ch3, 1 V/div.), and EN/PWM (ch4, 5 V/div.) pins, t = 1 ms/div.
.
Figure 5. Channel select setup: (left) channel LED8 not used,
(right) using all channels.
GND
4.75 k
A8510
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
A8510
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
GND
t
Pin shorted
Short removed
EN/PWM
LED2
LED1
ISET
C1
C3
C4
C2
t
LED detection period
EN/PWM
LED8
LED1-7
ISET
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
fSW (MHz)
Resistance for RSET (kΩ)
10.0 30.020.012.5 32.522.517.515.0 25.0 35.0
Soft start function
During soft start the LEDx pins are set to sink (ILEDSS) and the
boost switch current is reduced to the ISWSS(LIM) level to limit
the inrush current generated by charging the output capacitors.
When the converter senses that there is enough voltage on the
LEDx pins, the converter proceeds to increase the LED current
to the preset regulation current and the boost switch current limit
is switched to the ISW(LIM) level to allow the A8510 to deliver the
necessary output power to the LEDs. This is shown in figure 7.
Frequency selection
The switching frequency on the boost regulator is set by the
resistor connected to the FSET/SYNC pin, and the switching
frequency can be can be anywhere from 580 kHz to 2.3 MHz.
Figure 6 shows the typical switching frequencies for given resis-
tor values.
If during operation a fault occurs that will increase the switch-
ing frequency, the FSET/SYNC pin is clamped to a maximum
switching frequency of no more than 3.5 MHz.
Synchronization
The A8510 can also be synchronized using an external clock on
the FSET/SYNC pin. Figure 8 shows the correspondence of a
SYNC signal and the SW pin, and figure 9 shows the result when
a SYNC signal is detected: the LED current does not show any
variation while the frequency synchronization occurs. At power-
up if the FSET/SYNC pin is held low, the IC will not power-up.
Only when the FSET/SYNC pin is tri-stated to allow for the pin
to rise, to about 1 V, or when a sync clock is detected, will the
A8510 try to power-up.
Figure 7. Startup diagram showing the input current, output voltage, and
output current, fSW = 800 kHz; shows IOUT (ch1, 500 mA/div.), IIN (ch2, 1 A/
div.), VOUT (ch3, 20 V/div.), and EN/PWM (ch4, 5 V/div.), t = 1 ms/div.
Figure 6. Typical Switching Frequency versus value of RFSET resistor.
Figure 9. Transition of the SW waveform when the SYNC pulse is
detected. The A8510 switching at 800 kHz, applied SYNC pulse at
1.5 MHz; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 500 mA/div.), FSET/
SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), t = 2 s/div.
t
Inrush current caused by
enabling the disconnect
switch (when used)
Operation during
ISWSS(lim)
Normal operation
ISW(lim)
EN/PWM
IIN
IOUT
VOUT
C1
C3
C4
C2
t
SW node
FSET/SYNC
ILED
VOUT
C1
C3
C4
C2
Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch
node; shows VOUT (ch1, 20 V/div.), ILED (ch2, 200 mA/div.), FSET/SYNC
(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), t = 2 s/div.
t
SW node
800 kHz operation 1.5 MHz operation
FSET/SYNC
IOUT
VOUT
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The basic requirement of the SYNC signal is 150 ns minimum
on-time and 150 ns minimum off time, as indicated by the speci-
fications for tPWSYNCON and tPWSYNCOFF
. Figure 10 shows the
timing for a synchronization clock into the A8510 at 800 kHz.
Thus any pulse with a duty cycle of 12% to 88% at 800 kHz can
be used to synchronize the IC.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
SYNC Pulse Frequency
(kHz)
Duty Cycle Range
(%)
2200 33 to 66
2000 30 to 70
1000 15 to 85
800 12 to 88
600 9 to 91
If during operation a SYNC clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor RFSET. Dur-
ing this period the IC will stop switching for a maximum period
of about 7 s to allow the sync detection circuitry to switch over
to the externally preset switching frequency.
If the clock is held low for more than 7 s, the A8510 will shut
down. In this shutdown mode the IC will stop switching, the
input disconnect switch is open, and the LEDs will stop sinking
current. To shutdown the IC into low power mode, the IC must be
disabled by keeping the EN/PWM pin low for a period of 32750
clock cycles. If the FSET/SYNC pin is released at any time after
7 s, the A8510 will proceed to soft start.
LED current setting and LED dimming
The maximum LED current can be up to 40 mA per channel, and
is set through the ISET pin. To set the ILED current, connect a
resistor, RISET, between this pin and GND, according to the fol-
lowing formula:
RISET = (1.003 × 327) / ILED (2)
where ILED is in mA and RISET is in . This sets the maximum
current through the LEDs, referred to as the 100% current. Stan-
dard RISET values, at gain equals 327, are as follows:
Standard Resistor Value
Closest to RISET
(kΩ)
LED current per LED, ILED
(mA)
8.25 40
10.5 30
13.0 25
16.2 20
PWM dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the EN/PWM pin. When the EN/PWM
pin is pulled high, the A8510 turns on and all enabled LEDs sink
100% current. When EN/PWM is pulled low, the boost converter
and LED sinks are turned off. The compensation (COMP) pin is
floated, and critical internal circuits are kept active. The typical
PWM dimming frequencies fall between 200 Hz and 1 kHz. Fig-
ures 12A to 12D provide examples of PWM switching behavior.
Another important feature of the A8510 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows greater accuracy at low PWM dimming duty cycles, as
shown in figure 11.
150 ns
T = 1.25 s
950 ns
t
PWSYNCON
t
PWSYNCOFF
150 ns
Figure 10. SYNC pulse on and off time requirements, for an
800-kHz clock.
Figure 11. Percentage Error of the LED current versus PWM duty cycle
(at 200 Hz PWM frequency), for 500 ns delay.
10
8
6
4
2
0
ErrLED (%)
PWM Duty Cycle, D (%)
0.1 1 10 100
Worst-case
Typical
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 12A. Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 200 Hz at 50% duty
cycle; shows VOUT (ch1, 10 V/div.), ILED (ch2, 50 mA/div.), COMP (ch3,
2 V/div.), EN/PWM (ch4, 5 V/div.), t = 1 ms/div.
Figure 12B. Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 200 Hz at 1% duty
cycle ; shows VOUT (ch1, 10 V/div.), ILED (ch2, 50 mA/div.), COMP (ch3,
2 V/div.), EN/PWM (ch4, 5 V/div.), t = 2 ms/div.
Figure 12C. Delay from rising edge of PWM signal to LED current; shows
EN/PWM (ch1, 2 V/div.), and ILED (ch2, 20 mA/div.), t = 200 ns/div.
Figure 12D. Delay from falling edge of PWM signal to LED current turn off;
shows EN/PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), t = 200 ns/div.
t
ILED
EN/PWM
COMP
VOUT
C1
C3
C4
C2
t
ILED
EN/PWM
C1
C2
t
ILED
EN/PWM
C1
C2
t
ILED
EN/PWM
COMP
VOUT
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
APWM pin
The APWM pin is used in conjunction with the ISET pin. This is
a digital signal pin that internally adjusts the ISET current. The
typical input signal frequency is between 20 kHz and 1 MHz. The
duty cycle of this signal is inversely proportional to the percent-
age of current that is delivered to the LEDs (figure 14). As an
example, a system that delivers a full LED current of 40 mA per
LED would deliver 20 mA of current per LED when an APWM
signal is applied with a duty cycle of 50%. When this pin is not
used it should be tied to GND.
To use this pin for a trim function, the user should set the maxi-
mum output current to a value higher than the required current by
at least 5%. The LED ISET current is then trimmed down to the
Figure 13. Simplified block diagram of the APWM ISET block.
Figure 16. Diagram showing the transition of LED current from 40 mA
to 20 mA, when a 50% duty cycle signal is applied to the APWM pin;
EN/PWM = 1; shows EN/PWM (ch1, 5 V/div.), APWM (ch2, 5 V/div.), and
ILED (ch3, 20 mA/div.), t = 1 ms/div.
Figure 17. Diagram showing the transition of LED current from 20 mA
to 40 mA, when a 50% duty cycle signal is removed from the APWM pin.
EN/PWM = 1; shows EN/PWM (ch1, 5 V/div.), APWM (ch2, 5 V/div.), and
ILED (ch3, 20 mA/div.), t = 1 ms/div.
Figure 14. LED current versus PWM duty cycle; 200 kHz APWM frequency. Figure 15. Percentage Error of the LED current versus APWM signals.
APWM
APWM ISET
Current
Adjust
ISET
Current
Mirror
LED
Driver
ISET
RISET
EN/PWM
A8510
40
30
20
10
0
ILED (mA)
PWM Duty Cycle, D (%)
0406020 80 100
5 V 200 kHz
1.5 V 200 kHz
1.5 V 50 kHz
5 V 50 kHz
25
20
15
10
5
0
PWM Duty Cycle, D (%)
0406020 80 100
ErrLED (%)
t
ILED
APWM
EN/PWM
C1
C3
C2
t
ILED
APWM
EN/PWM
C1
C3
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
appropriate value. In cases where the user-supplied APWM has
significant duty cycle limitations, it might be preferable to set the
maximum ISET current to be 25% to 50% higher, thus allowing
the APWM signal to have duty cycles that are between 50% and
75%.
Although the APWM dimming function has a wide frequency
range, if this function is used strictly as an analog dimming
function it is recommended to use frequency ranges between
50 and 500 kHz for best accuracy. The frequency range must be
considered only if the user is not using this function as a closed
loop trim function. There is a few millisecond propagation delay
between the APWM signal and ILED current. This effect is shown
in figures 16 through 18.
Analog dimming
The A8510 can also be dimmed by using an external DAC or
another voltage source applied either directly to the ground side
of the RISET resistor or through an external resistor to the ISET
pin (see figure 19).
• For a single resistor (upper panel of figure 19), the ISET current
is controlled by the following formula:
ISET =
VISET – VDAC
RISET – VDAC
(3)
Where VISET is the ISET pin voltage and VDAC is the DAC out-
put voltage.
When the DAC voltage is equal to VISET
, the internal reference,
there is no current through RISET . When the DAC voltage starts
to decrease, the ISET current starts to increase, thus increasing
the LED current. When the DAC voltage is 0 V, the LED current
will be at its maximum.
• For a dual-resistor configuration (lower panel of figure 19), the
ISET current is controlled by the following formula:
ISET =–
VISET
R
ISET
VDAC – VISET
R
1
(4)
The advantage of this circuit is that the DAC voltage can be
higher or lower, thus adjusting the LED current to a higher or
lower value of the preset LED current set by the RISET resistor:
VDAC = 1.003 V; the output is strictly controlled by RISET
VDAC > 1.003 V; the LED current is reduced
VDAC < 1.003 V; the LED current is increased
Figure 18. Transition of output current level when a 50% duty cycle signal
is applied to the APWM pin, in conjunction with a 50% duty cycle PWM
dimming being applied to the EN/PWM pin; shows EN/PWM (ch1, 5 V/
div.), APWM (ch2, 5 V/div.), and ILED (ch3, 20 mA/div.), t = 1 ms/div.
t
IOUT
APWM
EN/PWM
C1
C3
C2
Figure 19. Simplified diagrams of voltage control of ILED: typical
applications using a DAC to control ILED using a single resistor (upper),
and dual resistors (lower).
GND
DAC
VDAC
GND
A8510
ISET
GND
DAC
VDAC
GND
A8510
ISET
R
ISET
R1
R
ISET
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
LED short detect
All of the LEDx pins are capable of handling the maximum VOUT
that the converter can deliver, thus providing protection from the
LED pin to VOUT in the event of a connector short.
Any LEDx pin that has a voltage exceeding VLEDSC will be
removed from operation (see figure 20). This is to prevent the IC
from dissipating too much power by having a large voltage pres-
ent on the LEDx pin.
While the IC is being PWM-dimmed, the IC rechecks the dis-
abled LEDx pin every time the PWM signal goes high, to prevent
false tripping of an LEDx short event. This also allows some self-
correction if an intermittent LEDx pin short-to-VOUT is present.
Overvoltage protection
The A8510 has overvoltage protection (OVP) and open Schottky
diode (D1) protection. The OVP protection has a default level of
8 V and can be increased up to 55 V by connecting ROVP between
the OVP pin and VOUT
. When the current into the OVP pin
exceeds 199 A typical, the OVP comparator goes low and the
boost stops switching.
The following equation can be used to determine the resistance
for setting the OVP level:
ROVP = ( VOUTovp – VOVP(th)
) / IOVPH (4)
where:
VOUTovp is the target overvoltage level,
ROVP is the value of the external resistor, in ,
VOVP(th) is the pin OVP trip point found in the Electrical Charac-
teristics table, and
IOVPH is the current into the OVP pin.
There are several possibilities for why an OVP condition would
be encountered during operation, the two most common being: an
open LED string, and a disconnected output. Examples of these
are provided in figures 21 and 22.
Figure 21 illustrates when the output of the A8510 is discon-
nected from load during normal operation. The output voltage
instantly increases up to OVP voltage level and then the boost
stops switching to prevent damage to the IC. If the output is
drained off, eventually the boost might start switching for a short
duration until the OVP threshold is hit again.
Figure 20. Example of the disabling of an LED string when the LED pin
voltage is increased above 4.6 V; shows VLED (ch1, 5 V/div.), EN/PWM
(ch2, 5 V/div.), and ILED (ch3, 50 mA/div.), t = 20 s/div.
t
ILED
VLED
EN/PWM
C1
C3
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 21. OVP protection in an output disconnect from load event; shows
VOUT (ch1, 10 V/div.), SW node (ch2, 20 V/div.), EN/PWM (ch3, 5 V/div.),
and ILED (ch4, 50 mA/div.), t = 2 ms/div.
Figure 23. OVP protection in an open Schottky diode D1 event, while the
IC is in normal operation; shows SW node (ch1, 50 V/div.), IOUT (ch2, 500
mA/div.), ¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
(ch3, 5 V/div.), and EN/PWM (ch4, 5 V/div.), t = 2 s/div.
Figure 22. OVP protection in an open LED string event; shows VOUT
(ch1, 10 V/div.), SW node (ch2, 20 V/div.), EN/PWM (ch3, 5 V/div.), and
ILED (ch4, 200 mA/div.), t = 1 ms/div.
Figure 24. OVP protection when the IC is enabled during an open diode
condition; shows EN/PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), VOUT
(ch3, 10 V/div.), and ILED (ch4, 200 mA/div.), t = 500 s/div.
t
VOUT
EN/PWM
SW node
Output disconnect
event detected
ILED
C1
C3
C4
C2
t
VOUT
EN/PWM
SW node
Open diode
condition detected
ILED
C1
C3
C4
C2
t
VOUT
EN/PWM
SW node
ILED
C1
C3
C4
C2
LED string open
condition detected
Figure 22 displays a typical OVP event caused by an open LED
string. After the OVP condition is detected, the boost stops
switching, and the open LED string is removed from operation.
Afterwards VOUT is allowed to fall, and eventually the boost will
resume switching and the A8510 will resume normal operation.
A8510 also has built-in secondary overvoltage protection to pro-
tect the internal switch in the event of an open diode condition.
Open Schottky diode (D1) detection is implemented by detecting
overvoltage on the SW pins of the device. If voltage on the SW
pins exceeds the device safe operating voltage rating, the A8510
disables and remains latched. To clear this fault, the IC must be
shut down either by using the PWM signal or by going below the
UVLO threshold on the VIN pin. Figure 23 illustrates this. As
soon as the switch node voltage (SW) exceeds VOVP(sec), the IC
shuts down. Due to small delays in the detection circuit, as well
as there being no load present, the switch node voltage will rise
above the trip point voltage.
Figure 24 illustrates when the A8510 is being enabled during an
open diode condition. The IC goes through all of its initial LED
detection and then tries to enable the boost, at which point the
open diode is detected.
t
EN/PWM
SW node
Open diode
condition detected
IOUT
C1
C3
C4
C2
FAULT
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
19
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Boost switch overcurrent protection
The boost switch is protected with cycle-by-cycle current
limiting set at a minimum of 3.0 A. There is also a secondary cur-
rent limit that is sensed on the boost switch. When detected this
current limit immediately shuts down the A8510. The level of this
current limit is set above the cycle-by-cycle current limit to pro-
tect the switch from destructive currents when the boost inductor
is shorted. Various boost switch overcurrent conditions are shown
in figures 25 through 27.
Input overcurrent protection and disconnect switch
The primary function of the input disconnect switch is to protect
the system and the device from catastrophic input currents during
a fault condition. The external circuit implementing the discon-
nect is shown in figure 28. If the input disconnect switch is not
used, the VSENSE pin must be tied to VIN and the VGATE pin
must be left open.
Figure 25. Normal operation of the switch node (SW); inductor current
(IL) and output voltage (VOUT) for 12 series LEDs in each of 8 strings
configuration; shows IL (ch1, 500 mA/div.), SW node (ch2, 20 V/div.), VOUT
(ch3, 20 V/div.), and EN/PWM (ch4, 5 V/div.), t = 1 s/div.
Figure 26. Cycle-by-cycle current limiting; inductor current (IL), note
reduction in output voltage as compared to normal operation with the
same configuration (figure 25); shows IL (ch1, 1 A/div.), SW node (ch2, 20
V/div.), VOUT (ch3, 10 V/div.), and EN/PWM (ch4, 5 V/div.), t = 2 s/div.
Figure 27. Secondary boost switch current limit; when this limit is hit, the
A8510 immediately shuts down; shows EN/PWM (ch1, 5 V/div.), ¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
(ch2, 5 V/div.), SW node (ch3, 50 V/div.), and IL (ch4, 2 A/div.), t = 200 ns/div.
t
VOUT
EN/PWM
SW node
I
L
C1
C2
C3
C3
t
VOUT
EN/PWM
SW node
IL
C1
C3
C4
C2
t
IL
EN/PWM
SW node
C1
C3
C4
C2
FAULT
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
20
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
When selecting the external PMOS, check for the following
parameters:
• Drain-source breakdown voltage V(BR)DSS > –40 V
• Gate threshold voltage (make sure it is fully conducting at
VGS = -4 V, and cut-off at –1 V)
• RDS(on): Make sure the on-resistance is rated at VGS = -4.5 V or
similar, not at -10 V; derate it for higher temperature
If the input current level goes above the preset current limit
threshold, the A8510 will shut down in less than 3 s regardless
of user input (figure 29). This is a latched condition. The Fault
flag is also set to indicate a fault. This feature is meant to prevent
catastrophic failure in the system due to a short of the inductor or
output voltage to GND.
Figure 28. Typical circuit showing the implementation of the input
disconnect feature.
VGATE
RADJ
RSC
VSENSE
VIN
A8510
VIN Q1 To L1
Figure 29. Diagram showing input disconnect current limit wave forms
during fault condition; shows ¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
(ch1, 5 V/div.), VGATE (ch2,
10 V/div.), IIN (ch3, 2 A/div.), and EN/PWM (ch4, 5 V/div.), t = 5 s/div.
t
VGATE
EN/PWM
IIN
C1
C3
C4
C2
FAULT
A8510 shuts down
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
21
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Setting the current sense resistor
The typical threshold for the current sense circuit is 180 mV,
when RADJ is 0 . This voltage can be trimmed by the RADJ
resistor. The typical trip point should be set at about 3 A, which
coincides with the cycle-by-cycle current limit minimum thresh-
old. A sample calculation is done below:
Given: 2.85 A of input current, and the calculated maximum
value of the sense resistor, RSC = 0.063 .
The RSC chosen is 0.056 , a standard value.
Also:
RADJ = (VSENSETRIP – VADJ ) / IADJ (5)
The typical trip point voltage is calculated as:
VADJ = 2.85 A × 0.056 = 0.160 V
RADJ = (0.180 – 0.160 V) / (20.3 A) = 1.0 k
Input UVLO
When VIN and VSENSE rise above the UVLO enable hysteresis
(VUVLOrise + VUVLOhys
), the A8510 is enabled. A8510 is disabled
when VIN falls below the VUVLOfall threshold for more than 50 s.
This lag is to avoid shutting down because of momentary glitches
in the input power supply.
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect the capacitor CVDD with a value of 0.1 F or greater to
this pin.
Shutdown
If the EN/PWM pin is pulled low for more than tPWML , the
device enters shutdown mode and clears all internal fault regis-
ters. As an example, at a 2-MHz clock frequency, the maximum
PWM low period, while avoiding shutdown, is 16 ms. In shut
down, the IC disables all current sources and waits until the
EN/PWM pin goes high to re-enable the IC and proceed with
power-up.
Fault protection during operation
The A8510 constantly monitors the state of the system to deter-
mine if any fault conditions occur during normal operation. The
response to a triggered fault condition is summarized in the Fault
Mode table, on the next page.
The possible fault conditions that the device can detect are: Open
LED pin, LED pin shorted to GND, shorted inductor, VOUT short
to GND, SW pin shorted to GND, ISET pin shorted to GND, and
input disconnect switch source shorted to GND.
Note the following:
• Some of the protection features might not be active during
startup, to prevent false triggering of fault conditions.
• Some of these faults will not be protected if the input
disconnect switch is not being used. An example of this is
VOUT short to ground.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
22
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Fault Mode Table
Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
switch
Sink
driver
Primary switch
overcurrent protection
(cycle-by-cycle
current limit)
Auto-restart Always No This fault condition is triggered by the cycle-by-
cycle current limit, ISW(LIM).
Off for
a single
cycle
On On
Secondary switch
current limit Latched Always Yes
When the current through the boost switch exceeds
secondary current SW limit (ISW(LIM2)) the device
immediately shuts down the disconnect switch,
LED drivers, and boost. The Fault flag is set. To re-
enable the device, the EN/PWM pin must be pulled
low for 32750 clock cycles.
Off Off Off
Input disconnect
current limit Latched Always Yes
The device is immediately shut off if the voltage
across the input sense resistor is above the
VSENSEtrip threshold. The Fault flag is set. To re-
enable the part the EN/PWM pin must be pulled low
for 32750 clock cycles.
Off Off Off
Secondary OVP Latched Always Yes
Secondary overvoltage protection is used for open
diode detection. When diode D1 opens, the SW pin
voltage will increase until VOVP(SEC) is reached. This
fault latches the IC. The input disconnect switch is
disabled as well as the LED drivers, and the Fault
flag is set. To re-enable the part the EN/PWM pin
must be pulled low for 32750 clock cycles.
Off Off Off
LEDx pin short
protection Auto-restart Startup No
This fault prevents the device from starting-up if
any of the LEDx pins are shorted. The device stops
soft-start from starting while any of the LED pins
are determined to be shorted. Once the short is
removed, soft-start is allowed to start.
Off On Off
LEDx pin open Auto-restart Normal
Operation No
When an LEDx pin is open the device will determine
which LEDx pin is open by increasing the output
voltage until OVP is reached. Any LED string not
in regulation will be turned off. The device will then
go back to normal operation by reducing the output
voltage to the appropriate voltage level.
On On
Off for
open
pins.
On
for all
others.
ISET short protection Auto-restart Always No
This fault occurs when the ISET current goes above
150% of the maximum current. The boost will stop
switching and the IC will disable the LED sinks until
the fault is removed. When the fault is removed the
IC will try to regulate to the preset LED current.
Off On Off
Continued on the next page…
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
23
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FSET/SYNC short
protection Auto-restart Always Yes
Fault occurs when the FSET/SYNC current goes
above 150% of maximum current. The boost will
stop switching, the disconnect switch will turn off
and the IC will disable the LEDx sinks until the fault
is removed. When the fault is removed the IC will try
to restart with soft-start.
Off Off Off
Overvoltage
protection Auto-restart Always No
Fault occurs when OVP pin exceeds VOVP(th)
threshold. The A8510 will immediately stop
switching to try to reduce the output voltage. If the
output voltage decreases then the A8510 will restart
switching to regulate the output voltage.
Stop
during
OVP
event.
On On
LED short protection Auto-restart Always No
Fault occurs when the LEDx pin voltage exceeds
5.1 V. When the LED short protection is detected
the LED string above the threshold will be removed
from operation.
On On
Off for
shorted
pins.
On
for all
others.
Overtemperature
protection Auto-restart Always No Fault occurs when the die temperature exceeds the
overtemperature threshold, typically 165°C. Off Off Off
VIN UVLO Auto-restart Always No Fault occurs when VIN drops below VUVLO
, typically
3.90 V. This fault resets all latched faults. Off Off Off
Fault Mode Table (continued)
Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
Switch
Sink
driver
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Fault Tolerant LED Driver
A8510
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Allegro MicroSystems, Inc.
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Applications Information
Design Example for Boost Configuration
This section provides a method for selecting component values
when designing an application using the A8510. An example
schematic is provided in figure 30.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VBAT: 10 to 14 V
• Quantity of LED channels, #CHANNELS : 8
• Quantity of series LEDs per channel, #SERIESLEDS : 12
• LED current per channel, ILED
: 40 mA
• Vf at 40 mA: 3.2 V
• fSW
: 800 kHz
• TA(max): 65°C
• PWM dimming frequency: 200 Hz, 1% Duty cycle
Procedure: The procedure consists of selecting the appropriate
configuration and then the individual component values, in an
ordered sequence. It should be noted that in many calculations
the minimum and/or maximum specification values are used to
guarantee proper system operation.
Step 1 Connect LEDs to pins LED1 through LED8.
Step 2 Determining the LED current setting resistor RISET:
RISET = 1.003 × 327 / ILED (6)
= 327.981 / 40 mA = 8.20 k
Choose a 8.25 k resistor.
Step 3 Determining the OVP resistor. The OVP resistor is
connected between the OVP pin and the output voltage of the
converter.
Step 3a The first step is determining the maximum voltage
based on the LED requirements. Then this value and the regula-
tion voltage (VLED) should be added together, as well as another
750 mV to take noise and output ripple into consideration. The
regulation voltage, VLED , of the A8510 is 680 mV.
VOUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (7)
= 12 × 3.2 V+ 0.680 V + 2 V
= 41.08 V
Then the OVP resistor is:
ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (8)
= (41.08 V – 8.1 V) / 199 A = 165.73 k
where both I
OVPH and VOVP(th) are taken from the Electrical
Characteristics table.
Chose a value of resistor that is higher value than the calculated
ROVP . In this case a value of 169 k was selected. Below is the
actual value of the minimum OVP trip level with the selected
resistor:
VOUT(OVP) = 169 k × 199 A + 8.1 V = 41.7 V
Step 3b At this point a quick check must be done to see if the
conversion ratio is acceptable for the selected frequency.
Dmaxofboost = 1 – tSWOFFTIME × fSW (9)
= 1 – 1.5 × 47 ns × 800 kHz = 94.36%
where minimum off time (tSWOFFTIME) is found in the Electrical
Characteristics table.
The Theoretical Maximum VOUT is then calculated as:
VOUTthe(max) Vd
=–
1 – Dmaxofboost
VIN(min)
0.4 177 V
==–
1 – 0.9436
10 V
(10)
where Vd is the diode forward voltage.
The Theoretical Maximum VOUT value must be greater than the
value VOUT(OVP) . If this is not the case, the switching frequency
of the boost converter must be reduced to meet the maximum
duty cycle requirements.
Step 4 Selecting the inductor. The inductor must be chosen such
that it can handle the necessary input current. In most applica-
tions, due to stringent EMI requirements, the system must operate
in continuous conduction mode throughout the whole input volt-
age range.
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Fault Tolerant LED Driver
A8510
25
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Step 4a Determining the duty cycle, calculated as follows:
D(max) Vd
=+
VIN(min)
VOUT(OVP)
76.3%
==
41.7 V + 0.4 V
1 –
1 –
10 V
(11)
The voltage drop of the diode can be approximated to be about
0.4 V.
Step 4b Determining the maximum and minimum input current
to the system. The minimum input current will dictate the induc-
tor value. The maximum current rating will dictate the current
rating of the inductor. First, the maximum input current, given:
IOUT
=
#CHANNELS ILED
0.320 A
==
8 0.040 A
(12)
then:
IIN(max) =
VIN(min)
VOUT(OVP) IOUT
H
1.483 A
==
41.7 V
10 V 0.9
0.320 A
(13)
where is efficiency.
Next, calculate minimum input current, as follows:
IIN(min) =
VIN(max)
VOUT(OVP) IOUT
H
1.059 A
==
41.7 V
14 V 0.9
0.320 A
(14)
A good approximation of efficiency, , can be taken from the
efficiency curves located in the diode datasheet. A value of 90%
is a good starting approximation.
Step 4c Determining the inductor value. To ensure that the
inductor operates in continuous conduction mode, the value of
the inductor must be set such that the ½ inductor ripple current is
not greater than the average minimum input current. A first past
assumes Iripple to be 30% of the maximum inductor current:
IL = IIN(max) × 0.3 (15)
= 1.48 A × 0.3 = 0.444 A
Then:
L=
VIN(min) D(max)
fSW
IL
21.4 H
0.444 A
==
0.76
10 V
800 kHz
(16)
Step 4d Double-check to make sure the ½ current ripple is less
than IIN(min):
IIN(min) > 1/2 IL (17)
1.059 A > 0.222 A
A good inductor value to use would be 22 H, Lused
.
Step 4e This step is used to verify that there is sufficient slope
compensation for the inductor chosen. The slope compensation
value is determined by the following formula:
2 10
6
Slope Compensation ==
fSW
4.5
1.8 A /s
(18)
Next insert the inductor value used in the design:
=
VIN(min) D(max)
fSW
Lused
ILused
22 H0.434
A
==
0.763
10 V
800 kHz
(19)
Calculate the minimum required slope:
=
(1 – D(max))
(1 – 0.763)
fSW
Required
Slope (min) ILused
0.434 A
1
1
1
10
–6
110
–6
==
1.46 A/s
800 kHz
(20)
If the minimum required slope is larger than the calculated slope
compensation, the inductor value must be increased.
Note: that the slope compensation value is in A/s, and 1×10
–6 is
a constant multiplier.
Step 4f Determining the inductor current rating. The inductor
current rating must be greater than the IIN(max) value plus the
ripple current IL, or about 1.7 A, calculated as follows:
IL(min) = IIN(max) + 1/2 ILused (21)
= 1.483 A + 0.217 A = 1.70 A
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
26
Allegro MicroSystems, Inc.
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Worcester, Massachusetts 01615-0036 U.S.A.
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Step 5 Determining the resistor value for a particular switching
frequency. Use the RFSET values shown in figure 6. For example,
a 25.5 k resistor will result in an 800 kHz switching frequency.
Step 6 Choosing the proper switching diode. The switching
diode must be chosen for three characteristics when it is used in
LED lighting circuitry. The most obvious two are: current rating
of the diode and reverse voltage rating.
The reverse voltage rating should be such that during operation
condition, the voltage rating of the device is larger than the maxi-
mum output voltage. In this case it is VOUT(OVP).
The peak current through the diode is calculated as:
Idp = IIN(max) + 1/2 ILused (22)
= 1.483 A + 0.217 A = 1.70 A
The third major component in deciding the switching diode is the
reverse current, IR , characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time the boost converter is not switching. This
results in a slow bleeding off of the output voltage, due to leakage
currents. IR can be a large contributor, especially at high tempera-
tures. On the diode that was selected in this design, the current
varies between 1 and 100 A.
Step 7 Choosing the output capacitors. The output capacitors
must be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The big-
gest factors that contribute to the size of the output capacitor are
PWM dimming frequency and PWM duty cycle. Another major
contributor is leakage current ( ILK
). This current is the combina-
tion of the OVP leakage current as well as the reverse current of
the switching diode. In this design the PWM dimming frequency
is 200 Hz and the minimum duty cycle is 1%. Typically the volt-
age variation on the output (VCOUT) during PWM dimming must
be less than 250 mV, so that no audible hum can be heard. The
capacitance can be calculated as follows:
COUT =
fPWM(dimming)
1 – D(min)
1 – 0.01
200 Hz
ILK
200 A 3.96 F
==
0.250 V
VCOUT
(23)
A capacitor larger than 3.96 F should be selected due to degra-
dation of capacitance at high voltages on the capacitor. A ceramic
4.7 F 50 V capacitor is a good choice to fulfill this requirement.
Corresponding capacitors include:
Vendor Value Part number
Murata 4.7 F 50 V GRM32ER71H475KA88L
Murata 2.2 F 50 V GRM31CR71H225KA88L
The rms current through the capacitor is given by:
ICOUTrms =
1 – D(max)
D(max) + ILused
IOUT
0.320 A 0.583 A
12
==
IIN(max)
1 – 0.763
0.763
+0.434 A
1.48 A
12
(24)
The output capacitor must have a current rating of at least
583 mA. The capacitors selected in this design have a combined
rms current rating of 3 A.
Step 8 Selecting input capacitor. The input capacitor must be
selected such that it provides a good filtering of the input voltage
waveform. A good rule of thumb is to set the input voltage ripple
VIN to be 1% of the minimum input voltage. The minimum
input capacitor requirements are as follows:
CIN =
fSW
0.434 A
ILused
0.68 F
8
==
VIN
800 kHz 0.1 V
8
(25)
The rms current through the capacitor is given by:
IINrms =
(1 – D(max))
IOUT × ILused
0.11 A
12
==
IIN(max)
(1 – 0.763)
0.320 A × 0.434 A
1.48 A
12
(26)
A good ceramic input capacitor with ratings of 2.2 F 50V or
4.7 F 50 V will suffice for this application.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
27
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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Figure 30. The schematic diagram showing calculated values from the design example above
Corresponding capacitors include:
Vendor Value Part number
Murata 4.7 F 50 V GRM32ER71H475KA88L
Murata 2.2 F 50 V GRM31CR71H225KA88L
Step 9 Choosing the input disconnect switch components. Set
the input disconnect current limit to 3 A by choosing a corre-
sponding sense resistor. The calculated maximum value of the
sense resistor is:
RSC(max) = VSENSEtrip/ 3.0 A (27)
= 0.180 V / 3.0 A= 0.060
The RSC chosen is 0.056 , a standard value.
The trip point voltage must be:
VADJ = 3.0 A × 0.056 = 0.168 V
RADJ = (VSENSEtrip – VADJ ) / IADJ (28)
= (0.180 V – 0.168 V) / 20.3 A = 591
A value of 590 was chosen for this design.
VGATE SW SW
Q1
L1 D1
CVDD
OVP
VOUT
ROVP COUT
RSC
RADJ
VSENSE
VIN
VDD
EN/PWM
APWM
ISET
FSET/SYNC
AGND PGND PGND
COMP
CPRZ
CZ
LED8
LED1
12 LEDs
each string
LED2
LED3
LED4
LED5
LED6
LED7
FAULT
PAD
A8510
120
VC
22 H
169 k
0.056
590
100 k
RISET
8.25 kRFSET
25.5 k
4.7 F
50 V
CIN
4.7 F/ 50 V
0.1 F
0.47 F
120 pF
VIN 2 A /
60 V
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
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Allegro MicroSystems, Inc.
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Design Example for SEPIC Configuration
This section provides a method for selecting component values
when designing an application using the A8510 in SEPIC (Sin-
gle-Ended Primary-Inductor Converter) circuit. SEPIC topology
has the advantage that it can generate a positive output voltage
either higher or lower than the input voltage. The resulting design
is diagrammed in figure 31.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VBAT: 6 to 14 V ( VIN(min): 5 V and VIN(max): 16 V )
• Quantity of LED channels, #CHANNELS : 8
• Quantity of series LEDs per channel, #SERIESLEDS : 4
• LED current per channel, ILED
: 40 mA
• LED Vf at 60 mA: 3.3 V
• fSW
: 800 kHz
• TA(max): 65°C
• PWM dimming frequency: 200 Hz, 1% duty cycle
Procedure: The procedure consists of selecting the appropriate
configuration and then the individual component values, in an
ordered sequence.
Step 1 Connecting LEDs to LEDx pins. If only some of the LED
channels are needed, the unused LEDx pins should be pulled to
ground using a 1.5 k resistor.
Step 2 Determining the LED current setting resistor RISET:
RISET = (VISET × AISET) / ILED (29)
= (1.003 (V) × 327) / 0.40 (A) = 8.20 k
Choose an 8.25 k 1% resistor.
Step 3 Determining the OVP resistor. The OVP resistor is
connected between the OVP pin and the output voltage of the
converter.
Step 3a The first step is determining the maximum voltage
based on the LED requirements. The regulation voltage, VLED ,
of the A8510 is 720 mV. A constant term, 2 V, is added to give
margin to the design due to noise and output voltage ripple.
VOUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (V) (30)
= 4 × 3.3 (V) + 0.680 (V) + 2 (V) = 15.9 V
Then the OVP resistor is:
ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (31)
= (15.9 (V) – 8.1 (V)) / 0.199 (mA) = 39.196 k
where both I
OVPH and VOVP(th) are taken from the Electrical
Characteristics table.
In this case a value of 39.2 k was selected. Below is the actual
value of the minimum OVP trip level with the selected resistor:
VOUT(OVP) = 39.2 (k) × 0.199 (mA) + 8.1 (V) = 15.9 V
Step 3b At this point a quick check must be done to determine if
the conversion ratio is acceptable for the selected frequency.
Dmax = 1 – tSWOFFTIME × fSW (32)
= 1 – 1.5 × 47 (ns) × 800 (kHz) = 94.4%
where the minimum off-time (tSWOFFTIME) is found in the Electri-
cal Characteristics table.
The Theoretical Maximum VOUT is then calculated as:
VOUT(max) =Vd
–
1 – Dmax
Dmax
VIN(min)
0.4 (V) 77.9 V
==–
1 – 0.94
0.94
5 (V)
(33)
where Vd is the diode forward voltage.
The Theoretical Maximum VOUT value must be greater than
the value VOUT(OVP) . If this is not the case, it may be necessary
to reduce the frequency to allow the boost to convert the volt-
age ratios.
Step 4 Selecting the inductor. The inductor must be chosen such
that it can handle the necessary input current. In most applica-
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
29
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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tions, due to stringent EMI requirements, the system must operate
in continuous conduction mode throughout the whole input volt-
age range.
Step 4a Determining the duty cycle, calculated as follows:
D(max) Vd
=+
Vd
+
VOUT(OVP)
+
VIN(min)
VOUT(OVP)
76.5%
==
5 (V) + 15.9 (V) + 0.4 (V)
+ 0.4 (V)
15.9 (V)
(34)
Step 4b Determining the maximum and minimum input current
to the system. The minimum input current will dictate the induc-
tor value. The maximum current rating will dictate the current
rating of the inductor. First, the maximum input current, given:
IOUT
=
#CHANNELS ILED
0.320 A
==
8 40 (mA)
(35)
then:
IIN(max) =
VIN(min)
VOUT(OVP) IOUT
H
1.131 A
==
15.9 (V)
5 (V) 0.90
0.32 (A)
(36)
where is efficiency.
Next, calculate minimum input current, as follows:
IIN(min) =
VIN(max)
VOUT(OVP) IOUT
H
0.353 A
==
15.9 (V)
16 (V) 0.90
0.32 (A)
(37)
Step 4c Determining the inductor value. To ensure that the
inductor operates in continuous conduction mode, the value of
the inductor must be set such that the ½ inductor ripple current
is not greater than the average minimum input current. As a first
pass assume Iripple to be 30% of the maximum inductor current:
IL = IIN(max) × Iripple (38)
= 1.131 × 0.30 = 0.339 A
then:
L=
VIN(min) D(max)
fSW
IL
14.1 H
0.339 (A)
==
0.765
5 (V)
800 (kHz)
(39)
Step 4d Double-check to make sure the ½ current ripple is less
than IIN(min):
IIN(min) > 1/2 IL (40)
0.353 A > 0.170 A
A good inductor value to use would be 15 H.
Step 4e Next insert the inductor value used in the design to
determine the actual inductor ripple current:
=
VIN(min) D(max)
fSW
Lused
ILused
15 (H) 0.319 A
==
0.765
5 (V)
800 (kHz)
(41)
Step 4f Determining the inductor current rating. The inductor
current rating must be greater than the IIN(max) value plus half of
the ripple current IL, calculated as follows:
L(min) = IIN(max) + 1/2 ILused (42)
= 1.131 (A) + 0.160 (A) = 1.291 A
Step 5 Determining the resistor value for a particular switching
frequency. Use the RFSET values shown in figure 6. For example,
a 25.5 k resistor will result in an 800 kHz switching frequency.
Step 6 Choosing the proper switching diode. The switching
diode must be chosen for three characteristics when it is used in
LED lighting circuitry. The most obvious two are: current rating
of the diode and reverse voltage rating.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
30
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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The reverse breakdown voltage rating for the output diode in a
SEPIC circuit should be:
VBD > VOUT(OVP)(max) + VIN(max) (43)
> 15.9 (V) + 16 (V) = 31.9 V
because the maximum output voltage in this case is VOUT(OVP).
The peak current through the diode is calculated as:
Idp = IIN(max) + 1/2 ILused (44)
= 1.131 (A) + 0.160 (A) = 1.291 A
The third major component in deciding the switching diode is the
reverse current, IR , characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time the boost converter is not switching. This
results in a slow bleeding off of the output voltage, due to leakage
currents. IR can be a large contributor, especially at high tempera-
tures. On the diode that was selected in this design, the current
varies between 1 and 100 A. It is often advantageous to pick a
diode with a much higher breakdown voltage, just to reduce the
reverse current. Therefore for this example, pick a diode rated for
a VBD of 60 V, instead of just 40 V.
Step 7 Choosing the output capacitors. The output capacitors
must be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The biggest
factors that contribute to the size of the output capacitor are:
PWM dimming frequency and PWM duty cycle. Another major
contributor is leakage current, ILK
. This current is the combina-
tion of the OVP leakage current as well as the reverse current of
the switching diode. In this design the PWM dimming frequency
is 200 Hz and the minimum duty cycle is 1%. Typically, the volt-
age variation on the output, VCOUT , during PWM dimming must
be less than 250 mV, so that no audible hum can be heard. The
capacitance can be calculated as follows:
COUT =
fPWM(dimming)
1 – D(min)
1 – 0.01
200 (Hz)
ILK
200 (A) 3.96 F
==
0.250 (V)
VCOUT
(45)
A capacitor larger than 3.96 F should be selected due to degra-
dation of capacitance at high voltages on the capacitor. Select a
4.7 F capacitor for this application.
The rms current through the capacitor is given by:
ICOUTrms =
1 – D(max)
D(max)
IOUT
0.320 (A) 0.577 A
==
1 – 0.765
0.765
(46)
The output capacitor must have a ripple current rating of at least
600 mA. The capacitor selected for this design is a 4.7 F 50 V
capacitor with a 1.5 A current rating.
Step 8 Selecting input capacitor. The input capacitor must be
selected such that it provides a good filtering of the input voltage
waveform. A estimation rule is to set the input voltage ripple,
VIN
, to be 1% of the minimum input voltage. The minimum
input capacitor requirements are as follows:
CIN =
fSW
0.319 (A)
ILused
1.00 F
8
==
VIN
800 (kHz) 0.05 (V)
8
(47)
The rms current through the capacitor is given by:
CINrms =
ILused
0.092 A
12
==
0.319 (A)
12
(48)
A good ceramic input capacitor with a rating of 2.2 F 25 V will
suffice for this application.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
31
Allegro MicroSystems, Inc.
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VGATE SW SW
Q1
L1 D1
CVDD
OVP
VOUT
COUT
RSC
RADJ
R1
VSENSE
VIN
VDD
EN/PWM
APWM
ISET
FSET/SYNC
AGND PGND PGND
COMP
CP
RZ
CZ
LED8
LED1
LED2
LED3
LED4
LED5
LED6
LED7
FAULT
PAD
A8510
VC
RISET RFSET
CIN
6 to 14 V 0.056
590
100 k
120
8.25 k
25.5 k
39.2 k
120 pF
2.2 F
25 V
0.1 F
0.47 F
4.7 F
50 V
3.3 F / 25 V 2 A / 60 V
VIN CSW
ROVP
L2
15 H
15 H
Figure 31. Typical application showing SEPIC configuration, with accurate input current sense, and VSENSE
to GND protection.
Step 9 Selecting coupling capacitor CSW. The minimum capaci-
tance of CSW is related to the maximum voltage ripple allowed
across it:
CSW =
fSW
0.32 (A) 0.765
IOUT DMAX
0.627 F
==
VSW
800 (kHz)0.1 (V)
(49)
The rms current requirement of the coupling capacitor is given
by:
ICSWrms =
1 – D(max)
D(max)
IIN(max)
1.131 (A) 0.627 A
==
1 – 0.765
0.765
(50)
The voltage rating of the coupling capacitor must be greater than
VIN(max), or 16 V in this case. A ceramic capacitor rated for
2.2 F 25 V will suffice for this application.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
32
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EC, 26-Pin QFN with Exposed Thermal Pad
0.95
C
SEATING
PLANE
C0.08
27X
26
26
2
1
1
2
26
2
1
A
D
C
ATerminal #1 mark area
Coplanarity includes exposed thermal pad and terminals
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only
(reference JEDEC MO-220WGGE)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
D
Reference land pattern layout (reference IPC7351
QFN40P400X400X80-29M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1.23
1.10
1.23
1.10
2.45
2.45
4.00
0.20
0.40
4.00
4.00 ±0.15
4.00 ±0.15
0.75 ±0.05
0.20 ±0.05
0.40 BSC
0.40 +0.15
–0.10 B
PCB Layout Reference View
Top View
Bottom View
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8510
33
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2010-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Rev. 2 December 15, 2011 Update to application examples, add VSYNC