QP27C256 & QP27C256L June 18, 2009 QP27C256 - 256 Kilobit (32K x 8) CMOS EPROM General Description The QP27C256 is a 32Kx8 (256-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The QP27C256 meets the same specification requirements and utilizes the same programming methodology as the AMD 27C256 that it replaces. Products are available in windowed and non-windowed (OTP) ceramic hermetic packages. Data is typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable ( OE ) and Chip Enable ( CE ) pins, eliminating bus contention in a multiple bus system. Typical power consumption is only 80 mW in active mode, and 100 W in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device is programmed identically to the AMD27C256 device that it replaces, using the same programming algorithm (100 us pulses). The QP27C256 features: - Same programming algorithm as the AMD27C256, allowing it to be programmed using the same equipment, data and algorithm. When programming this device select AMD as the manufacturer and 27C256 as the device type. - Speed options as fast as 55ns - JEDEC Pinout - Single +5V power supply - CMOS and TTL input/output compatibility - Two line control functions - Programming time typically 4 seconds. The device/family is constructed using an advanced UV CMOS wafer fabrication process. Block Diagram 2945 Oakmead Village Ct, Santa Clara, CA 95051 * Phone: (408) 737-0992 * Fax: (408) 736--8708 * Internet: www.qpsemi.com QP27C256 & QP27C256L Pin Name A0 - A14 CE ( E ) DQ0 - DQ7 Function Address Inputs Chip Enable Input OE ( G ) Data Input/Output Output Enable Input PGM ( P ) Program Enable Input VCC VPP Vss NC VCC Supply Voltage Program Voltage Input Ground No Connection Connection Diagrams CERDIP / CERPACK LCC Device Type Functional Description Device Erasure In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp with a wavelength of 2537A and an intensity of 12,000 W/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000A, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 2 of 13 QP27C256 & QP27C256L Upon delivery, or after each erasure, the device has all of its bits in the "ONE", or HIGH state. "ZEROs" are loaded into the device through the programming procedure. The device enters the programming mode when 12.75V 0.25V is applied to the VPP pin, and both OE is at VIH & CE are at VIL. For programming, the data to be programmed is applied 8 bits in parallel to the data pins. The programming algorithm uses a 100 s programming pulse and gives each address only as many pulses as needed to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done with VCC = 6.25 V to assure that each bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Program Inhibit Programming different data to multiple devices in parallel is easily accomplished. Except for devices may be common. A TTL low-level program pulse applied to one device's and OE HIGH will program that particular device. A high-level CE CE CE , all like inputs of the input with VPP = 12.75 V 0.25 V input inhibits the other devices from being programmed. Program Verify Verification should be performed on the programmed bits to determine that they were correctly programmed. Verify should be performed with OE at VIL, CE at VIH and VPP between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and device identification through identifier codes on DQ0-DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. Read Mode To obtain data at the device outputs, Chip Enable ( CE ) and Output Enable ( power to the device and is typically used to select the device. OE OE ) must be driven low. CE controls the enables the device to output data, independent of device selection. Addresses must be stable for at least tACC-tOE. Standby Mode The device enters the CMOS standby mode when The device enters the TTL-standby mode when CE CE is at VCC 0.3 V. Maximum VCC current is reduced to 100 A. is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE input. Output OR Connection To accommodate multiple memory connections, a two-line control function provides: CE * Low memory power dissipation * Assurance that output bus contention will not occur. should be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. As a minimum, a 0.1F ceramic capacitor (high frequency, low inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7F bulk electrolytic capacitor should be used QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 3 of 13 QP27C256 & QP27C256L between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. MODE Select Table Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code Device Code CE OE A0 A9 VPP Outputs VIL X VIH VCC0.3V VIL VIH VIH VIL VIL VIL VIH X X VIH VIL VIH VIL VIL X X X X X X X VIL VIH X X X X X X X VH VH X X X X VPP VPP VPP X X Notes \1 \1 \1 \1 \1 \1 \1 \1 \2 \3 \4 \1 \2 \3 \4 DOUT High Z High Z High Z DIN DOUT High Z 01h 10h Notes: \1 X = Either VIH or VIL \2 VH = 12.0V 0.5V \3 A1-A8 & A10-A14 = VIL \4 Device Manufacture Code and Device ID match original AMD device for programming compatibility Absolute Maximum Ratings Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability Condition Units Notes Power Supply (VCC) -0.6 to +7.0 Volts DC Voltage with Respect to VSS All pins except A9, VPP, VCC -0.6 to VCC+0.6 Volts A9 and VPP -0.6 to 13.5 Volts Storage Temperature Range -65 to +150 C Lead Temperature (soldering, 10 seconds) +300 C Junction Temperature (TJ) +150 C Maximum Operating Temperature Commercial Devices 0 to 70 C Industrial Devices -40 to 85 C Military Temperature Range -55 to 125 C Data Retention 10 Years, minimum Device must not be removed from or inserted into a socket when VCC or VPP is applied. Recommended Operating Conditions Condition Supply Voltage Range (VCC) Input or Output Voltage Range Minimum High-Level Input Voltage (VIH) Maximum Low-Level Input Voltage (VIL) Case Operating Range (Tc) Commercial Devices Industrial Devices Military Temperature Range QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Units 4.5 to 5.5 0.0 to VCC 2.0 0.8 Volts DC Volts DC Volts DC Volts DC 0 to 70 C -40 to 85 C -55 to 125 C \5 \9 \6 \9 \7 \7 \7 \8 \7 \8 \7 \8 Notes \5 \6 \7 \8 \7 \8 \7 \8 Page 4 of 13 QP27C256 & QP27C256L \5 - Minimum DC Input Voltage on input or I/O pins -0.5V. During voltage transitions, the input may overshoot VSS to - 2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC+0.5V. During transitions, input and I/O pins may overshoot to VCC +2.0V for periods up to 20ns. \6 - Minimum DC Input Voltage on A9 is -0.5V. During voltage transitions, A9 and VPP may overshoot VSS to -2.0V for periods of up to 20ns. A9 and VPP must not exceed +13.5V at any time. \7 - Do not exceed 125C TC or TJ for plastic package devices. \8 - Maximum PD, Maximum TJ Are Not to Be Exceeded. \9 - During transitions, the inputs may undershoot to -2.0 V dc for periods less than 20 ns. \10 - VPP may be connected directly to VCC except during programming. \11 - Qualification Only. \12 - If not tested, shall be guaranteed to the limits specified. TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Input Load Current Symbol ILI Output Leakage Current ILO Operating Current, TTL ICC TTL Conditions -55C TA+125C Unless Otherwise Specified Min Max Unit VIN = 5.5V or 0.0V -10.0 +10.0 A VOIT = 5.5V or 0.0V -10.0 +10.0 A 35ns 85 mA VPP = VCC 45ns 60 mA O0-O7 = 0 mA 55ns 60 mA f = 1/tACCmax 70ns 60 mA QP27C256 90ns 60 mA QP27C256L 90ns 50 mA QP27C256 120ns 60 mA QP27C256L 120ns 50 mA QP27C256 150ns 60 mA QP27C256L 150ns 50 mA QP27C256 170ns 60 mA QP27C256L 170ns 50 mA QP27C256 200ns 60 mA QP27C256L 200ns 50 mA QP27C256 250ns 60 mA QP27C256L 250ns 50 mA QP27C256 300ns 60 mA QP27C256L 300ns 50 mA All other inputs at either VCC or GND OE = CE QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 = VIL Page 5 of 13 QP27C256 & QP27C256L TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Operating Current, CMOS Symbol ICC CMOS Conditions -55C TA+125C Unless Otherwise Specified Max Unit 35ns 60 mA VPP = VCC 45ns 60 mA O0-O7 = 0 mA 55ns 60 mA f = 1/tACCmax 70ns 60 mA QP27C256 90ns 60 mA QP27C256L 90ns 25 mA QP27C256 120ns 60 mA QP27C256L 120ns 25 mA QP27C256 150ns 60 mA QP27C256L 150ns 25 mA QP27C256 170ns 60 mA QP27C256L 170ns 25 mA QP27C256 200ns 60 mA QP27C256L 200ns 25 mA QP27C256 250ns 60 mA QP27C256L 250ns 25 mA QP27C256 300ns 60 mA QP27C256L 300ns 25 mA OE = CE QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 = VIL Min Page 6 of 13 QP27C256 & QP27C256L TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Standby Current, TTL Symbol Conditions -55C TA+125C Unless Otherwise Specified ISB TTL CE Max Unit 35ns 25 mA 45ns 25 mA f = 0 MHz 55ns O0-O7 = 0 mA 70ns QP27C256 90ns 25 25 25 mA mA mA QP27C256L 90ns 5 mA QP27C256 120ns 25 mA QP27C256L 120ns 5 mA QP27C256 150ns 25 mA QP27C256L 150ns 3 mA QP27C256 170ns 25 mA QP27C256L 170ns 3 mA QP27C256 200ns 25 mA QP27C256L 200ns 3 mA QP27C256 250ns 25 mA QP27C256L 250ns 3 mA QP27C256 300ns 25 mA QP27C256L 300ns 3 mA = VIH VCC= 5.5V QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Min Page 7 of 13 QP27C256 & QP27C256L TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Standby Current, CMOS Symbol ISB CMOS Conditions -55C TA+125C Unless Otherwise Specified Max Unit 35ns 25 mA 45ns 25 mA f = 0 MHz 55ns O0-O7 = 0 mA 70ns QP27C256 90ns 25 25 25 mA mA mA QP27C256L 90ns 300 uA QP27C256 120ns 25 mA QP27C256L 120ns 300 uA QP27C256 150ns 25 mA QP27C256L 150ns 300 uA QP27C256 170ns 25 mA QP27C256L 170ns 300 uA QP27C256 200ns 25 mA QP27C256L 200ns 300 uA QP27C256 250ns 25 mA QP27C256L 250ns 300 uA QP27C256 300ns 25 mA QP27C256L 300ns 300 uA 10 A CE = VIH VCC= 5.5V Min VPP Read Current IPP VPP = VCC = 5.5V Input Low Voltage TTL VIL VPP = VCC -0.1 0.8 V Input Low Voltage CMOS VIL VPP = VCC -0.2 0.2 V Input High Voltage TTL VIH VPP = VCC 2.0 VCC+1.0 V Input High Voltage CMOS VIH VPP = VCC VCC-0.2 VCC+0.2 V Output Low Voltage VOL IOL= 2.1mA 0.45 V Output High Voltage VOH VIL=0.8V,VIH=2.0V 2.4 V IOL= -400A,VCC=4.5V Output Short Circuit Current VPP Read Voltage \10 IOS VOUT = 0.0V -100 mA VCC V Duration not to exceed 1 second, one output at a time VPP QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 VCC - 0.7 Page 8 of 13 QP27C256 & QP27C256L TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Address to Output Delay CE to Output Delay Symbol tACC tCE Conditions -55C TA+125C Unless Otherwise Specified Min Max Unit CE = VIL 35ns 35 ns OE = VIL 45ns 45 ns 55ns 55 ns 70ns 70 ns 90ns 90 ns 120ns 120 ns 150ns 150 ns 170ns 170 ns 200ns 200 ns 250ns 250 ns 300ns 300 ns 35ns 40 ns 45ns 45 ns 55ns 55 ns 70ns 70 ns 90ns 90 ns 120ns 120 ns 150ns 150 ns 170ns 170 ns 200ns 200 ns 250ns 250 ns 300ns 300 ns OE = VIL QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 9 of 13 QP27C256 & QP27C256L TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test OE OE Symbol tOE to Output Delay tDF high to Output Float Output hold from Addresses, OE or tOH Conditions -55C TA+125C Unless Otherwise Specified CE OE CE = VIL = VIL = OE =VIL Min Max Unit 35ns 20 ns 45ns 15 ns 55ns 25 ns 70ns 25 ns 90ns 30 ns 120ns 35 ns 150ns 40 ns 170ns 40 ns 200ns 60 ns 250ns 60 ns 300ns 60 ns 35ns 15 ns 45ns 15 ns 55ns 20 ns 70ns 25 ns 90ns 30 ns 120ns 35 ns 150ns 40 ns 170ns 40 ns 200ns 55 ns 250ns 60 ns 300ns 60 ns 0 ns CE Whichever Occurred First Input Capacitance Output Capacitance \12 CIN VIN=0V, f=1Mhz 12 pF COUT VIN=0V, f=1Mhz 14 pF QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 10 of 13 QP27C256 & QP27C256L Ordering Information Part Number 5962-8606301UA 5962-8606301XA 5962-8606301YA 5962-8606301YC 5962-8606301ZA 5962-8606302UA 5962-8606302XA 5962-8606302YA 5962-8606302YC 5962-8606302ZA 5962-8606303UA 5962-8606303XA 5962-8606303YA 5962-8606303YC 5962-8606303ZA 5962-8606304UA 5962-8606304XA 5962-8606304YA 5962-8606304YC 5962-8606304ZA 5962-8606305UA 5962-8606305XA 5962-8606305YA 5962-8606305YC 5962-8606305ZA 5962-8606306UA 5962-8606306XA 5962-8606306YA 5962-8606306YC 5962-8606306ZA 5962-8606307UA 5962-8606307XA 5962-8606307YA 5962-8606307YC 5962-8606307ZA 5962-8606308UA 5962-8606308XA 5962-8606308YA 5962-8606308YC 5962-8606308ZA 5962-8606309UA 5962-8606309XA 5962-8606309YA 5962-8606309YC 5962-8606310UA 5962-8606310XA 5962-8606310YA 5962-8606310YC Package (Mil-Std-1835) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) JLCC-N32 GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) CQCC1-N32 (LCC) QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Generic QP27C256L-200/UA QP27C256L-200/XA QP27C256L-200/YA QP27C256L-200/YC QP27C256L-200/ZA QP27C256L-250/UA QP27C256L-250/XA QP27C256L-250/YA QP27C256L-250/YC QP27C256L-250/ZA QP27C256L-300/UA QP27C256L-300/XA QP27C256L-300/YA QP27C256L-300/YC QP27C256L-300/ZA QP27C256L-170/UA QP27C256L-170/XA QP27C256L-170/YA QP27C256L-170/YC QP27C256L-170/ZA QP27C256L-150/UA QP27C256L-150/XA QP27C256L-150/YA QP27C256L-150/YC QP27C256L-150/ZA QP27C256L-120/UA QP27C256L-120/XA QP27C256L-120/YA QP27C256L-120/YC QP27C256L-120/ZA QP27C256L-90/UA QP27C256L-90/XA QP27C256L-90/YA QP27C256L-90/YC QP27C256L-90/ZA QP27C256-70/UA QP27C256-70/XA QP27C256-70/YA QP27C256-70/YC QP27C256-70/ZA QP27C256-55/UA QP27C256-55/XA QP27C256-55/YA QP27C256-55/YC QP27C256-45/UA QP27C256-45/XA QP27C256-45/YA QP27C256-45/YC Page 11 of 13 QP27C256 & QP27C256L Part Number 5962-8606311QXA 5962-8606311QYA 5962-8606311UA 5962-8606311XA 5962-8606311YA 5962-8606312QXA 5962-8606312QYA 5962-8606312UA 5962-8606312XA 5962-8606312YA 5962-8606313QXA 5962-8606313QYA 5962-8606313UA 5962-8606313XA 5962-8606313YA 5962-8606314QXA 5962-8606314QYA 5962-8606314UA 5962-8606314XA 5962-8606314YA 5962-8606315QXA 5962-8606315QYA 5962-8606315UA 5962-8606315XA 5962-8606315YA 5962-8606316QXA 5962-8606316QYA 5962-8606316UA 5962-8606316XA 5962-8606316YA 5962-8606317QXA 5962-8606317QYA 5962-8606317UA 5962-8606317XA 5962-8606317YA 5962-8606318QXA 5962-8606318QYA 5962-8606318UA 5962-8606318XA 5962-8606318YA 5962-8606319QXA 5962-8606319QYA 5962-8606319UA 5962-8606319XA 5962-8606319YA 5962-8606320QUA 5962-8606320QXA 5962-8606320QYA 5962-8606321QUA Package (Mil-Std-1835) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP3-T28 CDIP4-T28 (DIP) QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Generic QP27C256-200/XA QP27C256-200/YA QP27C256-200/UA QP27C256-200/XA QP27C256-200/YA QP27C256-250/XA QP27C256-250/YA QP27C256-250/UA QP27C256-250/XA QP27C256-250/YA QP27C256-300/XA QP27C256-300/YA QP27C256-300/UA QP27C256-300/XA QP27C256-300/YA QP27C256-170/XA QP27C256-170/YA QP27C256-170/UA QP27C256-170/XA QP27C256-170/YA QP27C256-150/XA QP27C256-150/YA QP27C256-150/UA QP27C256-150/XA QP27C256-150/YA QP27C256-120/XA QP27C256-120/YA QP27C256-120/UA QP27C256-120/XA QP27C256-120/YA QP27C256-90/XA QP27C256-90/YA QP27C256-90/UA QP27C256-90/XA QP27C256-90/YA QP27C256-70/XA QP27C256-70/YA QP27C256-70/UA QP27C256-70/XA QP27C256-70/YA QP27C256-55/XA QP27C256-55/YA QP27C256-55/UA QP27C256-55/XA QP27C256-55/YA QP27C256-45/UA QP27C256-45/XA QP27C256-45/YA QP27C256-35/UA Page 12 of 13 QP27C256 & QP27C256L Part Number 5962-8606321QXA 5962-8606321QYA Package (Mil-Std-1835) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) Generic QP27C256-35/XA QP27C256-35/YA QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product family. Notes: Package outline information and specifications are defined by Mil-Std-1835 package dimension requirements. "-MIL" products manufactured by QP Semiconductor are compliant to the assembly, burn-in, test and quality conformance requirements of Test Methods 5004 & 5005 of Mil-Std-883 for Class B devices. This datasheet defines the electrical test requirements for the device(s). The listed drawings, Mil-PRF-38535, Mil-Std-883 and Mil-Std-1835 are available online at http://www.dscc.dla.mil/ Additional information is available at our website http://www.qpsemi.com QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 13 of 13