PECL3 Series 10K ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25C 3-Bit 10K ECL | Delay per er or tet Delay (ns) Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P 1) PartNumber | Step (ns) | (ng) 000 000 | 001 | 010 | O11 100 | 101. | 110 | M1 PECL3-0.5 0.5 + .25 + .30 3+0.5 0.0 0.5 1.0 15 2.0 2.5 3.0 3.5 PECL3-0.75 0.75 + .3 + 50 3+0.5 0.0 0.75 1.50 2.25 3.00 3.75 4.50 5.25 PECL3-1 1024.4 + 50 3+05 0.0 1.0 2.0 3.0 40 5.0 6.0 7.0 PECL3-1.2 12+.4 + .60 3+05 0.0 1.2 2.4 3.6 48 6.0 7.2 8.4 PECL3-1.25 1,254.5 +.70 3+0.5 0.0 1.25 2.50 3.75 5.00 6.25 7.50 8.75 PECL3-1.3 1.34.5 +.70 3+0.5 0.0 13 2.6 3.9 5.2 6.5 78 9.1 PECL3-1.5 15+ .5 +.70 3+05 0.0 15 3.0 45 6.0 75 9.0 10.5 PECL3-1.75 1.75 + .6 + 80 340.5 0.0 1.75 3.50 5.25 7.00 8.75 10.50 12.25 PECL3-2 2.0+.7 + 80 3+0.5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 PECL3-2.5 2.5+.7 +90 3+05 0.0 2.5 5.0 75 10.0 12.5 15.0 17.5 PECL3-3 3.0+.7 +10 340.5 0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 PECL3-5 5.0+1.0 +45 3+0.5 0.0 $.0 10.0 15.0 20.0 25.0 30.0 35.0 PECL3-10 10.0 + 1.5 +3.0 3+0.5 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 3PECLH Series 10KH ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25C 3-Bit 10KH ECL | Delay per Ere D elay(n s) Referenced to 000 - Delay (ns) per Program Setting (P3*P2*P1) PartNumber =| Step (ns) | (ng) 000 000 | 001 | 010 | on 100 | 101 110 | an 3PECLH-0.5 0.5 + .25 + .30 15405 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3PECLHO.75 0.75 + 3 + .50 15+0.5 0.0 0.75 1.50 2.25 3.00 3.75 4.50 5.25 3PECLH-1 10+ .4 +.50 15+0.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 3PECLH-1.2 12+.4 + .60 15+0.5 0.0 1.2 2.4 3.6 48 6.0 7.2 8.4 3PECLH1.25 1.25 + .5 +.70 1540.5 0.0 1.25 2.50 3.75 5.00 6.25 7.50 8.75 3PECLH-1.3 134.5 +.70 15+0.5 0.0 13 2.6 3.9 5.2 6.5 78 9.1 3PECLH-1.5 15+ .5 +.70 15+0.5 0.0 15 3.0 45 6.0 75 9.0 10.5 3PECLH1.75 1.75 + 6 + .80 15+0.5 0.0 1.75 3.50 5.25 7.00 8.75 10.50 12.25 3PECLH-2 20+ .7 + .80 1.5+0.5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 3PECLH-2.5 2.54.7 + .90 15+0.5 0.0 2.5 5.0 75 10.0 12.5 15.0 17.5 3PECLH-3 3.04.7 +10 15+0.5 0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 3PECLH-5 5.0410 15 15+0.5 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 3PECLH-10 10.0+ 1.5 +3.0 15+0.5 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 CUMULATIVE TOLERANCES: Error Tolerance is for Programmed Delays Referenced to Initial Delay, Setting "000." For example the setting "111" delay of PECL3-2 is 14.0 + 0.8 ns ref. to "000," and 17.04 1.3 ns referenced to the input. ECL 3-Bit 16-Pin Schematic Veco OUT P2 P3 ENABLE input, Pin 2, is active low. Output will be disabled ( low) when E "is high. [16] [15] [10] [o| ie : . . . Output |, | 3-Bit Programmable INPUT LOADING: Input, Pin 6, internally connected to eight ECL gate inputs Buffer Delay Line terminated by Thevenin equivalent of 100 Ohms to -2V. tt La Vec 6} [7 IN Pi mi[~ [- [=| Dimensions in Inches (mm) (20.57) (i046) MAX. [ MAX. GENERAL: For Operating Specifications and Test Conditions, see tf Tables IV, V and Vil on page 5 of this catalog. Delays specified for the (e60) (782 Leading Edge. TYP. MAR Operating Temp. Range .............-.cscsssessccseetceees -30C to +85C 120 o10 Temperature Coefficient ........2.......:ccesceseseee < 300ppm/C typical (3.05) (0.25) |" Minimum Input Pulse Width .............ccccceceee 35% of max. Delay y MIN. TYP. Supply Current, bog .sssccsssessesssseessesssenseees 75 mA typ., 85 mA max. L300 020 050.100 (7.62) 0.51 1.27) (2.54) owe Ce Ve. Specifications subject to change without notice. For other values & Custom Designs, contact factory. PECL3 4/98 Rhombus 15801 Chemical Lane, Huntington Beach, CA 92649-1595 @ Industries Inc. 27 Tel: (714) 898-0960 Fax: (714) 896-0971