THC63LVD827 - THine Electronics, Inc.

THC63LVD827_Rev.1.00_E

THC63LVD827

LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER

General Description

The THC63LVD827 transmitter is designed to support

pixel data transmission between Host and Flat Panel

Display and Dual Link transmission between Host and

Flat Panel Display up to 1080p/1920x1440 resolutions.

The THC63LVD827 converts 27 bits (RGB 8 bits +

Hsync, Vsync, DE) of CMOS/TTL data into LVDS

(Low Voltage Differential Signaling) data stream. The

transmitter can be programmed for rising edge or falling

edge clocks through a dedicated pin.

For dual LVDS out, LVDS clock frequency of

87MHz, 51bits of RGB data are transmitted at an effec-

tive rate of 609Mbps per LVDS channel.

For single LVDS out, LVDS clock frequency of

174MHz, 27bits of RGB data are transmitted at an

effective rate of 1218Mbps per LVDS channel.

21bits (RGB 6 bits + Hsync, Vsync, DE) m ode is also

selectable for 6bit color transmission with lower power .

Features

•Low power 1.8V CMOS design

•7mm x 7mm/72pin/0.65mm pitch/TFBGA package

applicable to non-HDI PC B.

•Wide dot clock range, 10-174MHz, suited for

TV Signal: up to 1080p(74.25MHz dual)

PC Signal: up to 1920x1440(86MHz dual)

•Supports 1.8V single power supply

•1.8V/2.5V/3.3V TTL/CMOS inputs are supported

by setting IOVCC=1.8V/2.5V/3.3V

•LVDS swing reducible by RS-pin to reduce both

EMI and power consumption

•PLL requires No external components

•Flexible Input/Output mod e

1. Single in / Dual LVDS out

2. Single in / Single LVDS out

3. Double edge Single in / Dual LVDS out

•2 LVDS data mapping to simplify PCB lay out

•Power down mode

•Input clock triggering edge selectable by R/F pin

•6bit / 8bit modes selectable by 6B /8B pi n

Block Diagram

PARALLEL TO SERIAL

PLL

TA1 +/-

TB1 +/-

TC1 +/-

TD1 +/-

TCLK1 +/-

/PDWN

10 to 174MHz

R1[7:0]

LVDS Outputs

24

TTL/CMOS Input s

TCLK2 +/-

1st Link

G1[7:0]

B1[7:0]

HSYNC

28

Data Formatter

28

R/F

1) DEMUX

2) MUX

VSYNC

DE

MAP

3

RS

MODE

PRBS

PARALLEL TO SERIAL

TA2 +/-

TB2 +/-

TC2 +/-

TD2 +/-

LVDS Outputs

2nd Link

O/E

DDRN

6B/8B

TRANSMITTER CLOCK IN

(Single in /Dual out : 20 to 174MHz)

10 to 174MHz

THC63LVD827_Rev.1.00_E

Pin Out (top view)

THC63LVD827_Rev.1.00_E

Pin Description

Pin Name Pin # Type Description

TA1+, TA1- A1,B1

LVDS OUT The 1st Link .

The 1st pixel output data when Dual out.

Output data when Single out.

TB1+, TB1- A2,B2

TC1+, TC1- A3,B3

TD1+, TD1- A5,B5

TCLK1+, TCLK1- A4,B4 LVDS OUT LVDS Clock Out for 1st Link.

TA2+, TA2- A6,B6

LVDS OUT The 2nd Link.

The 2nd pixel ou tp ut data when Dual ou t.

TB2+, TB2- A7,B7

TC2+, TC2- A8,B8

TD2+, TD2- C9,C8

TCLK2+, TCLK2- A9,B9 LVDS OUT LVDS Clock Out for 2nd Link.

R17 ~ R10 G1,G2,F1,F2

E1,E2,D1,D2

IN Pixel Data Inputs.G17 ~ G10 J4,H4,J3,H3

J2,H2,J1,H1

B17 ~ B10 J8,H8,J7,H7

J6,H6,J5,H5

DE G9 IN Data Enable Input.

VSYNC H9 IN Vsync Input.

HSYNC J9 IN Hsync Input.

CLKIN F9 IN Clock Input.

R/F G8 IN Input Clock Triggering Edge Select.

H: Rising edge, L: Falling edge

RS F8 IN

LVDS swing mode select.

MAP E8 IN

LVDS mapping table select. See Fig9 and Fig10.

MODE E7 IN

Pixel data mode. See Fig7 and Fig8.

O/E D9 IN Output enable.

H: Output enable,

L: Output disable (all outputs are Hi-Z).

/PDWN D8 IN H: Normal operation,

L: Power down (all output s are Hi-Z and all cir cuit s are

stand-by mode with minimum current (ITCCS)).

PRBS aC1 IN Must be tied to GND.

RS LVD S Swing (VOD, see Fig4 and Fig5)

H350mV

L200mV

MAP Mapping Mode

H Mapping MODE1

L Mapping MODE2

MODE Modes

H Single out (Single-in/Single-out)

L Dual out (Single-in/Dual-out)

THC63LVD827_Rev.1.00_E

a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of 223-1.

The generated PRBS is fed into input data latches, encoded and serialized into LVDS OUT.

This function is normally to be used for analyzing the signal integr ity of the transmission channel

including PCB traces, connectors, and cables.

Reserved1 C3 IN Must be tied to GND.

6B/8B F7 IN 6bit / 8bit mode select.

H: 6bit mode (21bit mode),

L: 8bit mode (27bit mode).

DDRN E9 IN DDR function is active when MODE = L (Dual-out mode).

H: DDR (Double Edge input) function disable (Fig4).

L: DDR (Double Edge input) function enable (Fig5).

N/C C2 Must be Open.

VCC G3,G5 Power Power Supply Pins for digital circuitry.

IOVCC G 7 Power Power Supply Pin for IO inputs circuitry.

LVDSVCC C5,D3 Power Power Supply Pins for LVDS Outputs.

PLLVCC C7 Power Power Supply Pin for PLL circuitry.

GND F3,G4,G6,C4,

E3,C6,D7 Ground Ground Pins.

Pin Name Pin # Type Description

Pin Description (Continued)

THC63LVD827_Rev.1.00_E

Absolute Maximum Ratings

Recommended Operating Conditions

Supply Voltage (IOVCC) -0.3V ~ +4.0V

Supply Voltage (VCC, PLLVCC, LVDSVCC) -0.3V ~ +2.1V

CMOS/TTL Input Voltage -0.3V ~ (IOVCC+ 0.3V)

LVDS Transmitter Output Voltage -0.3V ~ (LVDSVCC + 0.3V)

Output Current -50mA ~ 50mA

Junction Temperature +125

Storage Temperature Range -55 ~ +125

Reflow Peak Temperature / Time +260 / 10sec.

Maximum Power Dissipation @+25 1.3W

Parameter Min Typ Max Units

Supply Voltage (IOVCC) 1.62 1.8 / 2.5 / 3.3 3.6 V

Supply Voltage (PLLVCC / LVDSVCC / VCC) 1.62 1.8 1.98 V

Operating Ambient Temperature (Ta) -40 85

Clock

Frequency

MODE=L

Dual-out

Single Edge Input

(DDRN=H)

Input 20 174 MHz

LVDS Output 10 87 MHz

Double Edge Input

(DDRN=L)

Input 10 174 MHz

LVDS Output 10 174 MHz

MODE=H

Single-out

Input 10 174 MHz

LVDS Output 10 174 MHz

°C

°C°C

°C

THC63LVD827_Rev.1.00_E

Electrical Characteristics

CMOS/TTL (Pin type “IN”) DC Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

LVDS Transmitter (Pin type “LVDS OUT”) DC Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

VIH18 High Level Data Input Voltage IOVCC=1.62V~1.98V 0.65 IOVCC IOVCC+0.3 V

VIL18 Low Level Data Input Voltage -0.3 0.35 IOVCC V

VIH25 High Level Data Input Voltage IOVCC=2.3V~2.7V 1.7 IOVCC+0.3 V

VIL25 Low Level Data Input Voltage -0.3 0.7 V

VIH33 High Level Data Input Voltage IOVCC=3.0V~3.6V 2.0 IOVCC+0.3 V

VIL33 Low Level Data Input Voltage -0.3 0.8 V

IINC Input Current VIN=GND~IOVCC -10 10 μA

Symbol Parameter Conditions Min. Typ. Max. Units

VOD Differential Output Voltage RL=100Ω

Normal swing

RS= H 250 350 450 mV

Reduced swing

RS= L 140 200 300 mV

ΔVOD Change in VOD between

complementary output states RL=100Ω

35 mV

VOC Common Mode Voltage 1.125 1.25 1.375 V

ΔVOC Change in VOC between

complementary output states 35 mV

IOS Output Short Circuit Current VOUT=GND, RL=100Ω100 mA

IOZ Output TRI-State current /PDWN=L,

VOUT=GND~LVDSVCC -20 20 μA

THC63LVD827_Rev.1.00_E

Electrical Characteristics (Continued)

Supply Current Over recommended operating supply and temperature ranges unless otherwise specified.

(a) All Typ. values are at Vcc=1.8V, Ta=25 . The 256 Grayscale Test Pattern inputs test for a typical display pattern.

(b) All Max. values are at Vcc=1.98V, Ta=85 . Worst Case Test Pattern produces maximum switching frequency for

all the LVDS outputs (Fig .1).

Symbol Parameter Conditions Typ.(a) Max.(b) Units

ITCCW

Transmitter

Supply

Current

RL=100Ω

CL=5pF

RS = H

(RS = L)

MODE=H

Single-out

CLKIN=37MHz 24

(18) 33

(26) mA

CLKIN=65MHz 29

(23) 43

(37) mA

CLKIN=72MHz 30

(24) 46

(40) mA

MODE=L

Dual-out

DDRN=H

DDR Input Off

CLKIN=89MHz 48

(36) 65

(53) mA

CLKIN=119MHz 53

(41) 75

(63) mA

CLKIN=139MHz 56

(44) 82

(70) mA

CLKIN=154MHz 58

(46) 88

(76) mA

MODE=L

Dual-out

DDRN=L

DDR Input On

CLKIN=44.5MHz 47

(35) 64

(52) mA

CLKIN=59.5MHz 51

(39) 74

(62) mA

CLKIN=69MHz 54

(42) 80

(68) mA

CLKIN=77MHz 56

(44) 85

(73) mA

ITCCS

Transmitter

Power Down

Supply

Current

/PDWN = L, All Inputs = Fixed L or H 1 50 uA

°C

Fig1. Test Pattern

Txy+

x= A, B, C, D

y=1,2

TCLK1+

(LVDS Output Full Toggle Pattern)

THC63LVD827_Rev.1.00_E

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(a) Refer to Fig3-1 for details.

Symbol Parameter Min. Typ. Max. Units

tTCIP CLK IN Period(Fig4,5) 5.75 100 ns

tTCH CLK IN High T ime(Fig4,5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns

tTCL CLK IN Low Time(Fig4,5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns

tTS TTL Data Setup to CLK IN(Fig4,5) 0.8 ns

tTH TTL Data Hold from CKL IN(Fig4,5) 0.8 ns

tTCD CLK IN to TCLK+/-

Delay (Fig4,5)

MODE=L,DDR=H 9tTCIP+3.1 9tTCIP+8.0 ns

Others 5tTCIP+3.1 5tTCIP+8.0 ns

tTCOP CLK OUT Period(F ig 6) 5.75 100 ns

tLVT LVDS Transition Time(Fig2) 0.6 1.5 ns

tTOP1 Output Data

Position0 (Fig 6)

tTCOP =

5.75ns~15ns

-0.15 0.0 +0.15 ns

tTOP0 Output Data

Position1 (Fig 6) ns

tTOP6 Output Data

Position2 (Fig 6) ns

tTOP5 Output Data

Position3 (Fig 6) ns

tTOP4 Output Data

Position4 (Fig 6) ns

tTOP3 Output Data

Position5 (Fig 6) ns

tTOP2 Output Data

Position6 (Fig 6) ns

tTPLL Phase Lock Time(Fig3) 10.0 ms

tDEINT DE input period (Fig3-1)

Dual out mode only (MODE=L) 4tTCIP tTCIP*(2n)(a) ns

tDEH DE High time (Fig3-1)

Dual-out mode only (MODE=L) 2tTCIP tTCIP*(2m)(a) ns

tDEL DE Low time(Fig3-1)

Dual-out mode only (MODE=L) 2tTCIP ns

tTCOP

7

--------------- 0.15–tTCOP

7

--------------- tTCOP

7

--------------- 0.15+

2tTCOP

7

--------------- 0.15–2tTCOP

7

--------------- 2tTCOP

7

--------------- 0.15+

3tTCOP

7

--------------- 0.15–3tTCOP

7

--------------- 3tTCOP

7

--------------- 0.15+

4tTCOP

7

--------------- 0.15–4tTCOP

7

--------------- 4tTCOP

7

--------------- 0.15+

5tTCOP

7

--------------- 0.15–5tTCOP

7

--------------- 5 tTCOP

7

--------------- 0.15+

6tTCOP

7

--------------- 0.15–6tTCOP

7

--------------- 6tTCOP

7

--------------- 0.15+

THC63LVD827_Rev.1.00_E

AC Timing Diagrams

VIH

tTPLL

CLKIN

/PDWN

TCLKx+/-

Vdiff=0V

Fig3. PLL Lock Time

x=1,2

5pF 20%

80%

20%

80%

tLVT tLVT

Vdiff

100Ω

Vdiff=(TA+)-(TA-)

TA+

TA-

LVDS Output Load

Fig2. LVDS Output Load and Transition Time

CLKIN

DE

tDEINT

tDEH tDEL

Note: In dual-out mode (MODE=L),

the period between rising edges of DE (tDEINT), high time of DE (tDEH)

tTCIP

Fig3-1. Dual OUT mode DE input timing

should always satisfy following equations.

tDEINT = tTCIP * (2n)

m, n =integ e r

tDEH = tTCIP * (2m)

THC63LVD827_Rev.1.00_E

AC Timing Diagrams (Continued)

Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing for Single Edge Input Mode

tTCIP

tTS tTH

tTCH tTCL

CLKIN

t

TCD

VOC

GND

R1n, G1n, B1n

HSYNC

VSYNC

DE

n=0-7

Current Data

x=1,2

Current Data

Txy+/-

x=1,2

y= A, B, C, D

VOD

IOVCC

IOVCC/2 IOVCC/2 IOVCC/2

IOVCC/2 IOVCC/2

MODE=H or MODE=L,DDR=H

R/F=L

R/F=H

TCLKx+

TCLKx-

Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR)

MODE=L,DDRN=L

Current Data

Txy+/-

x=1,2

y= A, B, C, D

1st Pixel

Data 2nd Pixel

Data GND

VOD

IOVCC

VCC

tTS tTH tTS tTH

tTCIP

tTCH tTCL

CLKIN

t

TCD

VOC

IOVCC/2

IOGND

R1n, G1n, B1n

VSYNC

DE

n=0-7

RS pin VOD

H 350mV

L 200mV

HSYNC

I

IOVCC/2 IOVCC/2

IOVCC/2

R/F=L

R/F=H

x=1,2

TCLKx+

TCLKx-

THC63LVD827_Rev.1.00_E

AC Timing Diagrams (Continued)

Vdiff = 0V

Tyx+/- Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1

Vdiff = 0V

tTOP2

tTOP3

tTOP4

tTOP5

tTOP6

tTOP0

tTOP1

tTCOP

TCLKx+

x = 1,2

y = A,B,C,D Note:

Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-)

Fig6. LVDS Output Data Position

THC63LVD827_Rev.1.00_E

Single-In / Dual-Out Mode (MODE = L)

1st Pixel Data are mapped.

TCLK1+/-,TCLK2+/-

TA1+/-

TB1+/-

TC1+/-

TD1+/-

TA2+/-

TB2+/-

TC2+/-

TD2+/-

2nd Pixel Data are mapped.

Current CyclePrevious Cycle

1st Pixel

Data

2nd Pixel

Data

1st Pixel

Data

2nd Pixel

Data

Rn,Gn,Bn

HSYNC,VSYNC

n=10-17

DE

Fig7. Single-In / Dual-Out Mode (MODE=L)

THC63LVD827_Rev.1.00_E

Single-In / Single-Out Mode (MODE=H)

Pixel Data are mapped.

TCLK1+/-

TA1+/-

TB1+/-

TC1+/-

TD1+/-

TA2+/-

TB2+/-

TC2+/-

TD2+/-

Current CyclePrevious Cycle

Pixel Data

Rn,Gn,Bn

HSYNC,VSYNC,DE

n=10-17

TCLK2+/-

No output (HiZ)

Fig8. Single-In / Single-Out Mode (MODE=H)

THC63LVD827_Rev.1.00_E

LVDS Data Mapping for 8 bit mode (6B/8B=L)

R12

G12 R17 R16 R15 R14

R13

R13 R12

G13

B13 B12 G17 G16 G15

G14

G14 G13

TCLKn+/-

TAn+/-

B14

DE VSYNC HSYNC B17 B16

B15

B15 B14

R10

N/A B11 B10 G11 G10

R11

R11 R10

TBn+/-

TCn+/-

TDn+/-

Current CyclePrevious Cycle

n=1,2

(a) LVDS Data Mapping when MAP = H (Mapping Mode 1)

R10

G10 R15 R14 R13 R12

R11

R11 R10

G11

B11 B10 G15 G14 G13

G12

G12 G11

TCLKn+/-

TAn+/-

B12

DE VSYNC HSYNC B15 B14

B13

B13 B12

R16

N/A B17 B16 G17 G16

R17

R17 R16

TBn+/-

TCn+/-

TDn+/-

Current CyclePrevious Cycle

n=1,2

(b) LVDS Data Ma

pp

in

g

when MAP = L (Ma

pp

in

g

Mode 2)

Fig9. LVDS Data Mapping for 8 b it mode (6B/8B=L)

THC63LVD827_Rev.1.00_E

LVDS Data Mapping for 6 bit mode (6B/8B=H)

HiZ

R12

G12 R17 R16 R15 R14

R13

R13 R12

G13

B13 B12 G17 G16 G15

G14

G14 G13

TCLKn+/-

TAn+/-

B14

DE VSYNC HSYNC B17 B16

B15

B15 B14

TBn+/-

TCn+/-

TDn+/-

Current CyclePrevious Cycle

n=1,2

(a) LVDS Data Mapping when MAP = H (Mapping Mode 1)

R10

G10 R15 R14 R13 R12

R11

R11 R10

G11

B11 B10 G15 G14 G13

G12

G12 G11

TCLKn+/-

TAn+/-

B12

DE VSYNC HSYNC B15 B14

B13

B13 B12

TBn+/-

TCn+/-

TDn+/-

Current CyclePrevious Cycle

n=1,2

(b) LVDS Data Ma

pp

in

g

when MAP = L (Ma

pp

in

g

Mode 2)

HiZ

Fig10. LVDS Data Mapping for 6 bit mode (6B/8B=H)

Note: Input pins which are not used in 6 bit mode (R10-11,G10-11,B10-11 on Mapping Mode 1,

R16-17,G16-17 ,G16-17 on Mapping Mode 2) can be H, L, or Open.

THC63LVD827_Rev.1.00_E

Note

1)Cable Connection and Disconnection

Don't connect and disconnect the LVDS cable, when the power is suppl i e d to the system.

2)GND Connection

Connect the each GND of the PCB which THC63LVD827 and LVDS-Rx on it. It is better for EMI reduction to place

GND cable as close to LVDS cable as possible.

3)Multi Drop Connection

Multi drop connection is not recommended.

4)Asynchronous use

Asynchronous use such as following systems are not recommended.

THC63LVD827_Rev.1.00_E

Package

TFBGA

THC63LVD827_Rev.1.00_E

Notices and Requests

1.)The product specifications described in this material are subject to change without prior notice.

2.)The circuit diagrams described in this material are examples of the a pplication which may not

always apply to the customer's design. We are not responsible for possible errors and omissions in

this material. Please note if errors or omissions should be found in this material, we may not be able

to correct them immediately.

3.)This material contains our copyright, know-how or other proprietary. Copying or disclosing to

third parties the contents of this material without our prior permission is prohibited.

4.)Note that if infringement of any third party's industrial ownership should occur by using this

product, we will be exempted from the responsibility unless it directly relates to the production pro-

cess or functions of the product.

5.)This product is presumed to be used for general electric equipment, not for the applications

which require very high reliability (including medical equipment directly concerning people's life,

aerospace equipment, or nuclear control equipment). Also, when using this product for the equip-

ment concerned with the control and safety of the transportation means, the traffic signal equip-

ment, or various Types of safety equipment, please do it after applying appropriate measures to the

product.

6.)Despite our utmost efforts to improve the quality and reliability of the product, faults will occur

with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are

encouraged to have sufficiently redundant or error preventive design applied to the use of the prod-

uct so as not to have our product cause any social or public damage.

7.)Please note that this product is not designed to be radiation-proof.

8.)Customers are asked, if required, to judge by themselves if this product falls under the category

of strategic goods under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

E-mail: sales@thine.co.jp